ti-cpufreq.c 8.0 KB

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  1. /*
  2. * TI CPUFreq/OPP hw-supported driver
  3. *
  4. * Copyright (C) 2016-2017 Texas Instruments, Inc.
  5. * Dave Gerlach <d-gerlach@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/io.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/of.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/pm_opp.h>
  24. #include <linux/regmap.h>
  25. #include <linux/slab.h>
  26. #define REVISION_MASK 0xF
  27. #define REVISION_SHIFT 28
  28. #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
  29. #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
  30. #define DRA7_EFUSE_HAS_OD_MPU_OPP 11
  31. #define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
  32. #define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
  33. #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
  34. #define DRA7_EFUSE_OD_MPU_OPP BIT(1)
  35. #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
  36. #define VERSION_COUNT 2
  37. struct ti_cpufreq_data;
  38. struct ti_cpufreq_soc_data {
  39. unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
  40. unsigned long efuse);
  41. unsigned long efuse_fallback;
  42. unsigned long efuse_offset;
  43. unsigned long efuse_mask;
  44. unsigned long efuse_shift;
  45. unsigned long rev_offset;
  46. bool multi_regulator;
  47. };
  48. struct ti_cpufreq_data {
  49. struct device *cpu_dev;
  50. struct device_node *opp_node;
  51. struct regmap *syscon;
  52. const struct ti_cpufreq_soc_data *soc_data;
  53. struct opp_table *opp_table;
  54. };
  55. static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
  56. unsigned long efuse)
  57. {
  58. if (!efuse)
  59. efuse = opp_data->soc_data->efuse_fallback;
  60. /* AM335x and AM437x use "OPP disable" bits, so invert */
  61. return ~efuse;
  62. }
  63. static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
  64. unsigned long efuse)
  65. {
  66. unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
  67. /*
  68. * The efuse on dra7 and am57 parts contains a specific
  69. * value indicating the highest available OPP.
  70. */
  71. switch (efuse) {
  72. case DRA7_EFUSE_HAS_ALL_MPU_OPP:
  73. case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
  74. calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
  75. case DRA7_EFUSE_HAS_OD_MPU_OPP:
  76. calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
  77. }
  78. return calculated_efuse;
  79. }
  80. static struct ti_cpufreq_soc_data am3x_soc_data = {
  81. .efuse_xlate = amx3_efuse_xlate,
  82. .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
  83. .efuse_offset = 0x07fc,
  84. .efuse_mask = 0x1fff,
  85. .rev_offset = 0x600,
  86. .multi_regulator = false,
  87. };
  88. static struct ti_cpufreq_soc_data am4x_soc_data = {
  89. .efuse_xlate = amx3_efuse_xlate,
  90. .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
  91. .efuse_offset = 0x0610,
  92. .efuse_mask = 0x3f,
  93. .rev_offset = 0x600,
  94. .multi_regulator = false,
  95. };
  96. static struct ti_cpufreq_soc_data dra7_soc_data = {
  97. .efuse_xlate = dra7_efuse_xlate,
  98. .efuse_offset = 0x020c,
  99. .efuse_mask = 0xf80000,
  100. .efuse_shift = 19,
  101. .rev_offset = 0x204,
  102. .multi_regulator = true,
  103. };
  104. /**
  105. * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
  106. * @opp_data: pointer to ti_cpufreq_data context
  107. * @efuse_value: Set to the value parsed from efuse
  108. *
  109. * Returns error code if efuse not read properly.
  110. */
  111. static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
  112. u32 *efuse_value)
  113. {
  114. struct device *dev = opp_data->cpu_dev;
  115. u32 efuse;
  116. int ret;
  117. ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
  118. &efuse);
  119. if (ret) {
  120. dev_err(dev,
  121. "Failed to read the efuse value from syscon: %d\n",
  122. ret);
  123. return ret;
  124. }
  125. efuse = (efuse & opp_data->soc_data->efuse_mask);
  126. efuse >>= opp_data->soc_data->efuse_shift;
  127. *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
  128. return 0;
  129. }
  130. /**
  131. * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
  132. * @opp_data: pointer to ti_cpufreq_data context
  133. * @revision_value: Set to the value parsed from revision register
  134. *
  135. * Returns error code if revision not read properly.
  136. */
  137. static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
  138. u32 *revision_value)
  139. {
  140. struct device *dev = opp_data->cpu_dev;
  141. u32 revision;
  142. int ret;
  143. ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
  144. &revision);
  145. if (ret) {
  146. dev_err(dev,
  147. "Failed to read the revision number from syscon: %d\n",
  148. ret);
  149. return ret;
  150. }
  151. *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
  152. return 0;
  153. }
  154. static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data)
  155. {
  156. struct device *dev = opp_data->cpu_dev;
  157. struct device_node *np = opp_data->opp_node;
  158. opp_data->syscon = syscon_regmap_lookup_by_phandle(np,
  159. "syscon");
  160. if (IS_ERR(opp_data->syscon)) {
  161. dev_err(dev,
  162. "\"syscon\" is missing, cannot use OPPv2 table.\n");
  163. return PTR_ERR(opp_data->syscon);
  164. }
  165. return 0;
  166. }
  167. static const struct of_device_id ti_cpufreq_of_match[] = {
  168. { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
  169. { .compatible = "ti,am43", .data = &am4x_soc_data, },
  170. { .compatible = "ti,dra7", .data = &dra7_soc_data },
  171. {},
  172. };
  173. static const struct of_device_id *ti_cpufreq_match_node(void)
  174. {
  175. struct device_node *np;
  176. const struct of_device_id *match;
  177. np = of_find_node_by_path("/");
  178. match = of_match_node(ti_cpufreq_of_match, np);
  179. of_node_put(np);
  180. return match;
  181. }
  182. static int ti_cpufreq_probe(struct platform_device *pdev)
  183. {
  184. u32 version[VERSION_COUNT];
  185. const struct of_device_id *match;
  186. struct opp_table *ti_opp_table;
  187. struct ti_cpufreq_data *opp_data;
  188. const char * const reg_names[] = {"vdd", "vbb"};
  189. int ret;
  190. match = dev_get_platdata(&pdev->dev);
  191. if (!match)
  192. return -ENODEV;
  193. opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL);
  194. if (!opp_data)
  195. return -ENOMEM;
  196. opp_data->soc_data = match->data;
  197. opp_data->cpu_dev = get_cpu_device(0);
  198. if (!opp_data->cpu_dev) {
  199. pr_err("%s: Failed to get device for CPU0\n", __func__);
  200. return -ENODEV;
  201. }
  202. opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
  203. if (!opp_data->opp_node) {
  204. dev_info(opp_data->cpu_dev,
  205. "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
  206. goto register_cpufreq_dt;
  207. }
  208. ret = ti_cpufreq_setup_syscon_register(opp_data);
  209. if (ret)
  210. goto fail_put_node;
  211. /*
  212. * OPPs determine whether or not they are supported based on
  213. * two metrics:
  214. * 0 - SoC Revision
  215. * 1 - eFuse value
  216. */
  217. ret = ti_cpufreq_get_rev(opp_data, &version[0]);
  218. if (ret)
  219. goto fail_put_node;
  220. ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
  221. if (ret)
  222. goto fail_put_node;
  223. ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
  224. version, VERSION_COUNT);
  225. if (IS_ERR(ti_opp_table)) {
  226. dev_err(opp_data->cpu_dev,
  227. "Failed to set supported hardware\n");
  228. ret = PTR_ERR(ti_opp_table);
  229. goto fail_put_node;
  230. }
  231. opp_data->opp_table = ti_opp_table;
  232. if (opp_data->soc_data->multi_regulator) {
  233. ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
  234. reg_names,
  235. ARRAY_SIZE(reg_names));
  236. if (IS_ERR(ti_opp_table)) {
  237. dev_pm_opp_put_supported_hw(opp_data->opp_table);
  238. ret = PTR_ERR(ti_opp_table);
  239. goto fail_put_node;
  240. }
  241. }
  242. of_node_put(opp_data->opp_node);
  243. register_cpufreq_dt:
  244. platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
  245. return 0;
  246. fail_put_node:
  247. of_node_put(opp_data->opp_node);
  248. return ret;
  249. }
  250. static int ti_cpufreq_init(void)
  251. {
  252. const struct of_device_id *match;
  253. /* Check to ensure we are on a compatible platform */
  254. match = ti_cpufreq_match_node();
  255. if (match)
  256. platform_device_register_data(NULL, "ti-cpufreq", -1, match,
  257. sizeof(*match));
  258. return 0;
  259. }
  260. module_init(ti_cpufreq_init);
  261. static struct platform_driver ti_cpufreq_driver = {
  262. .probe = ti_cpufreq_probe,
  263. .driver = {
  264. .name = "ti-cpufreq",
  265. },
  266. };
  267. builtin_platform_driver(ti_cpufreq_driver);
  268. MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
  269. MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
  270. MODULE_LICENSE("GPL v2");