coda-bit.c 66 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/log2.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/videodev2.h>
  22. #include <media/v4l2-common.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-fh.h>
  25. #include <media/v4l2-mem2mem.h>
  26. #include <media/videobuf2-v4l2.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #include <media/videobuf2-vmalloc.h>
  29. #include "coda.h"
  30. #include "imx-vdoa.h"
  31. #define CREATE_TRACE_POINTS
  32. #include "trace.h"
  33. #define CODA_PARA_BUF_SIZE (10 * 1024)
  34. #define CODA7_PS_BUF_SIZE 0x28000
  35. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  36. #define CODA_DEFAULT_GAMMA 4096
  37. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  38. static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  39. static inline int coda_is_initialized(struct coda_dev *dev)
  40. {
  41. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  42. }
  43. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  44. {
  45. return coda_read(dev, CODA_REG_BIT_BUSY);
  46. }
  47. static int coda_wait_timeout(struct coda_dev *dev)
  48. {
  49. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  50. while (coda_isbusy(dev)) {
  51. if (time_after(jiffies, timeout))
  52. return -ETIMEDOUT;
  53. }
  54. return 0;
  55. }
  56. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  57. {
  58. struct coda_dev *dev = ctx->dev;
  59. if (dev->devtype->product == CODA_HX4 ||
  60. dev->devtype->product == CODA_7541 ||
  61. dev->devtype->product == CODA_960) {
  62. /* Restore context related registers to CODA */
  63. coda_write(dev, ctx->bit_stream_param,
  64. CODA_REG_BIT_BIT_STREAM_PARAM);
  65. coda_write(dev, ctx->frm_dis_flg,
  66. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  67. coda_write(dev, ctx->frame_mem_ctrl,
  68. CODA_REG_BIT_FRAME_MEM_CTRL);
  69. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  70. }
  71. if (dev->devtype->product == CODA_960) {
  72. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  73. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  74. }
  75. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  76. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  77. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  78. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  79. trace_coda_bit_run(ctx, cmd);
  80. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  81. }
  82. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  83. {
  84. struct coda_dev *dev = ctx->dev;
  85. int ret;
  86. coda_command_async(ctx, cmd);
  87. ret = coda_wait_timeout(dev);
  88. trace_coda_bit_done(ctx);
  89. return ret;
  90. }
  91. int coda_hw_reset(struct coda_ctx *ctx)
  92. {
  93. struct coda_dev *dev = ctx->dev;
  94. unsigned long timeout;
  95. unsigned int idx;
  96. int ret;
  97. if (!dev->rstc)
  98. return -ENOENT;
  99. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  100. if (dev->devtype->product == CODA_960) {
  101. timeout = jiffies + msecs_to_jiffies(100);
  102. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  103. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  104. if (time_after(jiffies, timeout))
  105. return -ETIME;
  106. cpu_relax();
  107. }
  108. }
  109. ret = reset_control_reset(dev->rstc);
  110. if (ret < 0)
  111. return ret;
  112. if (dev->devtype->product == CODA_960)
  113. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  114. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  115. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  116. ret = coda_wait_timeout(dev);
  117. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  118. return ret;
  119. }
  120. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  121. {
  122. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  123. struct coda_dev *dev = ctx->dev;
  124. u32 rd_ptr;
  125. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  126. kfifo->out = (kfifo->in & ~kfifo->mask) |
  127. (rd_ptr - ctx->bitstream.paddr);
  128. if (kfifo->out > kfifo->in)
  129. kfifo->out -= kfifo->mask + 1;
  130. }
  131. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  132. {
  133. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  134. struct coda_dev *dev = ctx->dev;
  135. u32 rd_ptr, wr_ptr;
  136. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  137. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  138. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  139. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  140. }
  141. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  142. {
  143. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  144. struct coda_dev *dev = ctx->dev;
  145. u32 wr_ptr;
  146. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  147. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  148. }
  149. static int coda_bitstream_pad(struct coda_ctx *ctx, u32 size)
  150. {
  151. unsigned char *buf;
  152. u32 n;
  153. if (size < 6)
  154. size = 6;
  155. buf = kmalloc(size, GFP_KERNEL);
  156. if (!buf)
  157. return -ENOMEM;
  158. coda_h264_filler_nal(size, buf);
  159. n = kfifo_in(&ctx->bitstream_fifo, buf, size);
  160. kfree(buf);
  161. return (n < size) ? -ENOSPC : 0;
  162. }
  163. static int coda_bitstream_queue(struct coda_ctx *ctx,
  164. struct vb2_v4l2_buffer *src_buf)
  165. {
  166. u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
  167. u32 n;
  168. n = kfifo_in(&ctx->bitstream_fifo,
  169. vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
  170. if (n < src_size)
  171. return -ENOSPC;
  172. src_buf->sequence = ctx->qsequence++;
  173. return 0;
  174. }
  175. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  176. struct vb2_v4l2_buffer *src_buf)
  177. {
  178. unsigned long payload = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
  179. int ret;
  180. if (coda_get_bitstream_payload(ctx) + payload + 512 >=
  181. ctx->bitstream.size)
  182. return false;
  183. if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
  184. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  185. return true;
  186. }
  187. /* Add zero padding before the first H.264 buffer, if it is too small */
  188. if (ctx->qsequence == 0 && payload < 512 &&
  189. ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
  190. coda_bitstream_pad(ctx, 512 - payload);
  191. ret = coda_bitstream_queue(ctx, src_buf);
  192. if (ret < 0) {
  193. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  194. return false;
  195. }
  196. /* Sync read pointer to device */
  197. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  198. coda_kfifo_sync_to_device_write(ctx);
  199. ctx->hold = false;
  200. return true;
  201. }
  202. void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list)
  203. {
  204. struct vb2_v4l2_buffer *src_buf;
  205. struct coda_buffer_meta *meta;
  206. unsigned long flags;
  207. u32 start;
  208. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
  209. return;
  210. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  211. /*
  212. * Only queue two JPEGs into the bitstream buffer to keep
  213. * latency low. We need at least one complete buffer and the
  214. * header of another buffer (for prescan) in the bitstream.
  215. */
  216. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  217. ctx->num_metas > 1)
  218. break;
  219. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  220. /* Drop frames that do not start/end with a SOI/EOI markers */
  221. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  222. !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
  223. v4l2_err(&ctx->dev->v4l2_dev,
  224. "dropping invalid JPEG frame %d\n",
  225. ctx->qsequence);
  226. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  227. if (buffer_list) {
  228. struct v4l2_m2m_buffer *m2m_buf;
  229. m2m_buf = container_of(src_buf,
  230. struct v4l2_m2m_buffer,
  231. vb);
  232. list_add_tail(&m2m_buf->list, buffer_list);
  233. } else {
  234. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
  235. }
  236. continue;
  237. }
  238. /* Dump empty buffers */
  239. if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
  240. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  241. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  242. continue;
  243. }
  244. /* Buffer start position */
  245. start = ctx->bitstream_fifo.kfifo.in &
  246. ctx->bitstream_fifo.kfifo.mask;
  247. if (coda_bitstream_try_queue(ctx, src_buf)) {
  248. /*
  249. * Source buffer is queued in the bitstream ringbuffer;
  250. * queue the timestamp and mark source buffer as done
  251. */
  252. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  253. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  254. if (meta) {
  255. meta->sequence = src_buf->sequence;
  256. meta->timecode = src_buf->timecode;
  257. meta->timestamp = src_buf->vb2_buf.timestamp;
  258. meta->start = start;
  259. meta->end = ctx->bitstream_fifo.kfifo.in &
  260. ctx->bitstream_fifo.kfifo.mask;
  261. spin_lock_irqsave(&ctx->buffer_meta_lock,
  262. flags);
  263. list_add_tail(&meta->list,
  264. &ctx->buffer_meta_list);
  265. ctx->num_metas++;
  266. spin_unlock_irqrestore(&ctx->buffer_meta_lock,
  267. flags);
  268. trace_coda_bit_queue(ctx, src_buf, meta);
  269. }
  270. if (buffer_list) {
  271. struct v4l2_m2m_buffer *m2m_buf;
  272. m2m_buf = container_of(src_buf,
  273. struct v4l2_m2m_buffer,
  274. vb);
  275. list_add_tail(&m2m_buf->list, buffer_list);
  276. } else {
  277. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  278. }
  279. } else {
  280. break;
  281. }
  282. }
  283. }
  284. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  285. {
  286. struct coda_dev *dev = ctx->dev;
  287. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  288. /* If this context is currently running, update the hardware flag */
  289. if ((dev->devtype->product == CODA_960) &&
  290. coda_isbusy(dev) &&
  291. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  292. coda_write(dev, ctx->bit_stream_param,
  293. CODA_REG_BIT_BIT_STREAM_PARAM);
  294. }
  295. }
  296. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  297. {
  298. struct coda_dev *dev = ctx->dev;
  299. u32 *p = ctx->parabuf.vaddr;
  300. if (dev->devtype->product == CODA_DX6)
  301. p[index] = value;
  302. else
  303. p[index ^ 1] = value;
  304. }
  305. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  306. struct coda_aux_buf *buf, size_t size,
  307. const char *name)
  308. {
  309. return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
  310. }
  311. static void coda_free_framebuffers(struct coda_ctx *ctx)
  312. {
  313. int i;
  314. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  315. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  316. }
  317. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  318. struct coda_q_data *q_data, u32 fourcc)
  319. {
  320. struct coda_dev *dev = ctx->dev;
  321. unsigned int ysize, ycbcr_size;
  322. int ret;
  323. int i;
  324. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  325. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 ||
  326. ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 ||
  327. ctx->codec->dst_fourcc == V4L2_PIX_FMT_MPEG4)
  328. ysize = round_up(q_data->rect.width, 16) *
  329. round_up(q_data->rect.height, 16);
  330. else
  331. ysize = round_up(q_data->rect.width, 8) * q_data->rect.height;
  332. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  333. ycbcr_size = round_up(ysize, 4096) + ysize / 2;
  334. else
  335. ycbcr_size = ysize + ysize / 2;
  336. /* Allocate frame buffers */
  337. for (i = 0; i < ctx->num_internal_frames; i++) {
  338. size_t size = ycbcr_size;
  339. char *name;
  340. /* Add space for mvcol buffers */
  341. if (dev->devtype->product != CODA_DX6 &&
  342. (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  343. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)))
  344. size += ysize / 4;
  345. name = kasprintf(GFP_KERNEL, "fb%d", i);
  346. if (!name) {
  347. coda_free_framebuffers(ctx);
  348. return -ENOMEM;
  349. }
  350. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  351. size, name);
  352. kfree(name);
  353. if (ret < 0) {
  354. coda_free_framebuffers(ctx);
  355. return ret;
  356. }
  357. }
  358. /* Register frame buffers in the parameter buffer */
  359. for (i = 0; i < ctx->num_internal_frames; i++) {
  360. u32 y, cb, cr, mvcol;
  361. /* Start addresses of Y, Cb, Cr planes */
  362. y = ctx->internal_frames[i].paddr;
  363. cb = y + ysize;
  364. cr = y + ysize + ysize/4;
  365. mvcol = y + ysize + ysize/4 + ysize/4;
  366. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
  367. cb = round_up(cb, 4096);
  368. mvcol = cb + ysize/2;
  369. cr = 0;
  370. /* Packed 20-bit MSB of base addresses */
  371. /* YYYYYCCC, CCyyyyyc, cccc.... */
  372. y = (y & 0xfffff000) | cb >> 20;
  373. cb = (cb & 0x000ff000) << 12;
  374. }
  375. coda_parabuf_write(ctx, i * 3 + 0, y);
  376. coda_parabuf_write(ctx, i * 3 + 1, cb);
  377. coda_parabuf_write(ctx, i * 3 + 2, cr);
  378. if (dev->devtype->product == CODA_DX6)
  379. continue;
  380. /* mvcol buffer for h.264 and mpeg4 */
  381. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
  382. coda_parabuf_write(ctx, 96 + i, mvcol);
  383. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)
  384. coda_parabuf_write(ctx, 97, mvcol);
  385. }
  386. return 0;
  387. }
  388. static void coda_free_context_buffers(struct coda_ctx *ctx)
  389. {
  390. struct coda_dev *dev = ctx->dev;
  391. coda_free_aux_buf(dev, &ctx->slicebuf);
  392. coda_free_aux_buf(dev, &ctx->psbuf);
  393. if (dev->devtype->product != CODA_DX6)
  394. coda_free_aux_buf(dev, &ctx->workbuf);
  395. coda_free_aux_buf(dev, &ctx->parabuf);
  396. }
  397. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  398. struct coda_q_data *q_data)
  399. {
  400. struct coda_dev *dev = ctx->dev;
  401. size_t size;
  402. int ret;
  403. if (!ctx->parabuf.vaddr) {
  404. ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
  405. CODA_PARA_BUF_SIZE, "parabuf");
  406. if (ret < 0)
  407. return ret;
  408. }
  409. if (dev->devtype->product == CODA_DX6)
  410. return 0;
  411. if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
  412. /* worst case slice size */
  413. size = (DIV_ROUND_UP(q_data->rect.width, 16) *
  414. DIV_ROUND_UP(q_data->rect.height, 16)) * 3200 / 8 + 512;
  415. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  416. "slicebuf");
  417. if (ret < 0)
  418. goto err;
  419. }
  420. if (!ctx->psbuf.vaddr && (dev->devtype->product == CODA_HX4 ||
  421. dev->devtype->product == CODA_7541)) {
  422. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  423. CODA7_PS_BUF_SIZE, "psbuf");
  424. if (ret < 0)
  425. goto err;
  426. }
  427. if (!ctx->workbuf.vaddr) {
  428. size = dev->devtype->workbuf_size;
  429. if (dev->devtype->product == CODA_960 &&
  430. q_data->fourcc == V4L2_PIX_FMT_H264)
  431. size += CODA9_PS_SAVE_SIZE;
  432. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
  433. "workbuf");
  434. if (ret < 0)
  435. goto err;
  436. }
  437. return 0;
  438. err:
  439. coda_free_context_buffers(ctx);
  440. return ret;
  441. }
  442. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
  443. int header_code, u8 *header, int *size)
  444. {
  445. struct vb2_buffer *vb = &buf->vb2_buf;
  446. struct coda_dev *dev = ctx->dev;
  447. struct coda_q_data *q_data_src;
  448. struct v4l2_rect *r;
  449. size_t bufsize;
  450. int ret;
  451. int i;
  452. if (dev->devtype->product == CODA_960)
  453. memset(vb2_plane_vaddr(vb, 0), 0, 64);
  454. coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
  455. CODA_CMD_ENC_HEADER_BB_START);
  456. bufsize = vb2_plane_size(vb, 0);
  457. if (dev->devtype->product == CODA_960)
  458. bufsize /= 1024;
  459. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  460. if (dev->devtype->product == CODA_960 &&
  461. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 &&
  462. header_code == CODA_HEADER_H264_SPS) {
  463. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  464. r = &q_data_src->rect;
  465. if (r->width % 16 || r->height % 16) {
  466. u32 crop_right = round_up(r->width, 16) - r->width;
  467. u32 crop_bottom = round_up(r->height, 16) - r->height;
  468. coda_write(dev, crop_right,
  469. CODA9_CMD_ENC_HEADER_FRAME_CROP_H);
  470. coda_write(dev, crop_bottom,
  471. CODA9_CMD_ENC_HEADER_FRAME_CROP_V);
  472. header_code |= CODA9_HEADER_FRAME_CROP;
  473. }
  474. }
  475. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  476. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  477. if (ret < 0) {
  478. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  479. return ret;
  480. }
  481. if (dev->devtype->product == CODA_960) {
  482. for (i = 63; i > 0; i--)
  483. if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
  484. break;
  485. *size = i + 1;
  486. } else {
  487. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  488. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  489. }
  490. memcpy(header, vb2_plane_vaddr(vb, 0), *size);
  491. return 0;
  492. }
  493. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  494. {
  495. phys_addr_t ret;
  496. size = round_up(size, 1024);
  497. if (size > iram->remaining)
  498. return 0;
  499. iram->remaining -= size;
  500. ret = iram->next_paddr;
  501. iram->next_paddr += size;
  502. return ret;
  503. }
  504. static void coda_setup_iram(struct coda_ctx *ctx)
  505. {
  506. struct coda_iram_info *iram_info = &ctx->iram_info;
  507. struct coda_dev *dev = ctx->dev;
  508. int w64, w128;
  509. int mb_width;
  510. int dbk_bits;
  511. int bit_bits;
  512. int ip_bits;
  513. int me_bits;
  514. memset(iram_info, 0, sizeof(*iram_info));
  515. iram_info->next_paddr = dev->iram.paddr;
  516. iram_info->remaining = dev->iram.size;
  517. if (!dev->iram.vaddr)
  518. return;
  519. switch (dev->devtype->product) {
  520. case CODA_HX4:
  521. dbk_bits = CODA7_USE_HOST_DBK_ENABLE;
  522. bit_bits = CODA7_USE_HOST_BIT_ENABLE;
  523. ip_bits = CODA7_USE_HOST_IP_ENABLE;
  524. me_bits = CODA7_USE_HOST_ME_ENABLE;
  525. break;
  526. case CODA_7541:
  527. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  528. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  529. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  530. me_bits = CODA7_USE_HOST_ME_ENABLE | CODA7_USE_ME_ENABLE;
  531. break;
  532. case CODA_960:
  533. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  534. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  535. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  536. me_bits = 0;
  537. break;
  538. default: /* CODA_DX6 */
  539. return;
  540. }
  541. if (ctx->inst_type == CODA_INST_ENCODER) {
  542. struct coda_q_data *q_data_src;
  543. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  544. mb_width = DIV_ROUND_UP(q_data_src->rect.width, 16);
  545. w128 = mb_width * 128;
  546. w64 = mb_width * 64;
  547. /* Prioritize in case IRAM is too small for everything */
  548. if (dev->devtype->product == CODA_HX4 ||
  549. dev->devtype->product == CODA_7541) {
  550. iram_info->search_ram_size = round_up(mb_width * 16 *
  551. 36 + 2048, 1024);
  552. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  553. iram_info->search_ram_size);
  554. if (!iram_info->search_ram_paddr) {
  555. pr_err("IRAM is smaller than the search ram size\n");
  556. goto out;
  557. }
  558. iram_info->axi_sram_use |= me_bits;
  559. }
  560. /* Only H.264BP and H.263P3 are considered */
  561. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  562. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  563. if (!iram_info->buf_dbk_c_use)
  564. goto out;
  565. iram_info->axi_sram_use |= dbk_bits;
  566. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  567. if (!iram_info->buf_bit_use)
  568. goto out;
  569. iram_info->axi_sram_use |= bit_bits;
  570. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  571. if (!iram_info->buf_ip_ac_dc_use)
  572. goto out;
  573. iram_info->axi_sram_use |= ip_bits;
  574. /* OVL and BTP disabled for encoder */
  575. } else if (ctx->inst_type == CODA_INST_DECODER) {
  576. struct coda_q_data *q_data_dst;
  577. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  578. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  579. w128 = mb_width * 128;
  580. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  581. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  582. if (!iram_info->buf_dbk_c_use)
  583. goto out;
  584. iram_info->axi_sram_use |= dbk_bits;
  585. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  586. if (!iram_info->buf_bit_use)
  587. goto out;
  588. iram_info->axi_sram_use |= bit_bits;
  589. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  590. if (!iram_info->buf_ip_ac_dc_use)
  591. goto out;
  592. iram_info->axi_sram_use |= ip_bits;
  593. /* OVL and BTP unused as there is no VC1 support yet */
  594. }
  595. out:
  596. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  597. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  598. "IRAM smaller than needed\n");
  599. if (dev->devtype->product == CODA_HX4 ||
  600. dev->devtype->product == CODA_7541) {
  601. /* TODO - Enabling these causes picture errors on CODA7541 */
  602. if (ctx->inst_type == CODA_INST_DECODER) {
  603. /* fw 1.4.50 */
  604. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  605. CODA7_USE_IP_ENABLE);
  606. } else {
  607. /* fw 13.4.29 */
  608. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  609. CODA7_USE_HOST_DBK_ENABLE |
  610. CODA7_USE_IP_ENABLE |
  611. CODA7_USE_DBK_ENABLE);
  612. }
  613. }
  614. }
  615. static u32 coda_supported_firmwares[] = {
  616. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  617. CODA_FIRMWARE_VERNUM(CODA_HX4, 1, 4, 50),
  618. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  619. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  620. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 9),
  621. CODA_FIRMWARE_VERNUM(CODA_960, 2, 3, 10),
  622. CODA_FIRMWARE_VERNUM(CODA_960, 3, 1, 1),
  623. };
  624. static bool coda_firmware_supported(u32 vernum)
  625. {
  626. int i;
  627. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  628. if (vernum == coda_supported_firmwares[i])
  629. return true;
  630. return false;
  631. }
  632. int coda_check_firmware(struct coda_dev *dev)
  633. {
  634. u16 product, major, minor, release;
  635. u32 data;
  636. int ret;
  637. ret = clk_prepare_enable(dev->clk_per);
  638. if (ret)
  639. goto err_clk_per;
  640. ret = clk_prepare_enable(dev->clk_ahb);
  641. if (ret)
  642. goto err_clk_ahb;
  643. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  644. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  645. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  646. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  647. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  648. if (coda_wait_timeout(dev)) {
  649. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  650. ret = -EIO;
  651. goto err_run_cmd;
  652. }
  653. if (dev->devtype->product == CODA_960) {
  654. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  655. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  656. data);
  657. }
  658. /* Check we are compatible with the loaded firmware */
  659. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  660. product = CODA_FIRMWARE_PRODUCT(data);
  661. major = CODA_FIRMWARE_MAJOR(data);
  662. minor = CODA_FIRMWARE_MINOR(data);
  663. release = CODA_FIRMWARE_RELEASE(data);
  664. clk_disable_unprepare(dev->clk_per);
  665. clk_disable_unprepare(dev->clk_ahb);
  666. if (product != dev->devtype->product) {
  667. v4l2_err(&dev->v4l2_dev,
  668. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  669. coda_product_name(dev->devtype->product),
  670. coda_product_name(product), major, minor, release);
  671. return -EINVAL;
  672. }
  673. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  674. coda_product_name(product));
  675. if (coda_firmware_supported(data)) {
  676. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  677. major, minor, release);
  678. } else {
  679. v4l2_warn(&dev->v4l2_dev,
  680. "Unsupported firmware version: %u.%u.%u\n",
  681. major, minor, release);
  682. }
  683. return 0;
  684. err_run_cmd:
  685. clk_disable_unprepare(dev->clk_ahb);
  686. err_clk_ahb:
  687. clk_disable_unprepare(dev->clk_per);
  688. err_clk_per:
  689. return ret;
  690. }
  691. static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
  692. {
  693. u32 cache_size, cache_config;
  694. if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
  695. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  696. cache_size = 0x20262024;
  697. cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
  698. } else {
  699. /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
  700. cache_size = 0x02440243;
  701. cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
  702. }
  703. coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  704. if (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {
  705. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  706. 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  707. 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  708. } else {
  709. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  710. 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  711. 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  712. }
  713. coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  714. }
  715. /*
  716. * Encoder context operations
  717. */
  718. static int coda_encoder_reqbufs(struct coda_ctx *ctx,
  719. struct v4l2_requestbuffers *rb)
  720. {
  721. struct coda_q_data *q_data_src;
  722. int ret;
  723. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  724. return 0;
  725. if (rb->count) {
  726. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  727. ret = coda_alloc_context_buffers(ctx, q_data_src);
  728. if (ret < 0)
  729. return ret;
  730. } else {
  731. coda_free_context_buffers(ctx);
  732. }
  733. return 0;
  734. }
  735. static int coda_start_encoding(struct coda_ctx *ctx)
  736. {
  737. struct coda_dev *dev = ctx->dev;
  738. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  739. struct coda_q_data *q_data_src, *q_data_dst;
  740. u32 bitstream_buf, bitstream_size;
  741. struct vb2_v4l2_buffer *buf;
  742. int gamma, ret, value;
  743. u32 dst_fourcc;
  744. int num_fb;
  745. u32 stride;
  746. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  747. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  748. dst_fourcc = q_data_dst->fourcc;
  749. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  750. bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
  751. bitstream_size = q_data_dst->sizeimage;
  752. if (!coda_is_initialized(dev)) {
  753. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  754. return -EFAULT;
  755. }
  756. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  757. if (!ctx->params.jpeg_qmat_tab[0])
  758. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  759. if (!ctx->params.jpeg_qmat_tab[1])
  760. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  761. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  762. }
  763. mutex_lock(&dev->coda_mutex);
  764. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  765. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  766. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  767. switch (dev->devtype->product) {
  768. case CODA_DX6:
  769. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  770. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  771. break;
  772. case CODA_960:
  773. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  774. /* fallthrough */
  775. case CODA_HX4:
  776. case CODA_7541:
  777. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  778. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  779. break;
  780. }
  781. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  782. CODA9_FRAME_TILED2LINEAR);
  783. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  784. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  785. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  786. ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
  787. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  788. if (dev->devtype->product == CODA_DX6) {
  789. /* Configure the coda */
  790. coda_write(dev, dev->iram.paddr,
  791. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  792. }
  793. /* Could set rotation here if needed */
  794. value = 0;
  795. switch (dev->devtype->product) {
  796. case CODA_DX6:
  797. value = (q_data_src->rect.width & CODADX6_PICWIDTH_MASK)
  798. << CODADX6_PICWIDTH_OFFSET;
  799. value |= (q_data_src->rect.height & CODADX6_PICHEIGHT_MASK)
  800. << CODA_PICHEIGHT_OFFSET;
  801. break;
  802. case CODA_HX4:
  803. case CODA_7541:
  804. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  805. value = (round_up(q_data_src->rect.width, 16) &
  806. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  807. value |= (round_up(q_data_src->rect.height, 16) &
  808. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  809. break;
  810. }
  811. /* fallthrough */
  812. case CODA_960:
  813. value = (q_data_src->rect.width & CODA7_PICWIDTH_MASK)
  814. << CODA7_PICWIDTH_OFFSET;
  815. value |= (q_data_src->rect.height & CODA7_PICHEIGHT_MASK)
  816. << CODA_PICHEIGHT_OFFSET;
  817. }
  818. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  819. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  820. ctx->params.framerate = 0;
  821. coda_write(dev, ctx->params.framerate,
  822. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  823. ctx->params.codec_mode = ctx->codec->mode;
  824. switch (dst_fourcc) {
  825. case V4L2_PIX_FMT_MPEG4:
  826. if (dev->devtype->product == CODA_960)
  827. coda_write(dev, CODA9_STD_MPEG4,
  828. CODA_CMD_ENC_SEQ_COD_STD);
  829. else
  830. coda_write(dev, CODA_STD_MPEG4,
  831. CODA_CMD_ENC_SEQ_COD_STD);
  832. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  833. break;
  834. case V4L2_PIX_FMT_H264:
  835. if (dev->devtype->product == CODA_960)
  836. coda_write(dev, CODA9_STD_H264,
  837. CODA_CMD_ENC_SEQ_COD_STD);
  838. else
  839. coda_write(dev, CODA_STD_H264,
  840. CODA_CMD_ENC_SEQ_COD_STD);
  841. value = ((ctx->params.h264_disable_deblocking_filter_idc &
  842. CODA_264PARAM_DISABLEDEBLK_MASK) <<
  843. CODA_264PARAM_DISABLEDEBLK_OFFSET) |
  844. ((ctx->params.h264_slice_alpha_c0_offset_div2 &
  845. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  846. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  847. ((ctx->params.h264_slice_beta_offset_div2 &
  848. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  849. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  850. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  851. break;
  852. case V4L2_PIX_FMT_JPEG:
  853. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  854. coda_write(dev, ctx->params.jpeg_restart_interval,
  855. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  856. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  857. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  858. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  859. coda_jpeg_write_tables(ctx);
  860. break;
  861. default:
  862. v4l2_err(v4l2_dev,
  863. "dst format (0x%08x) invalid.\n", dst_fourcc);
  864. ret = -EINVAL;
  865. goto out;
  866. }
  867. /*
  868. * slice mode and GOP size registers are used for thumb size/offset
  869. * in JPEG mode
  870. */
  871. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  872. switch (ctx->params.slice_mode) {
  873. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  874. value = 0;
  875. break;
  876. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  877. value = (ctx->params.slice_max_mb &
  878. CODA_SLICING_SIZE_MASK)
  879. << CODA_SLICING_SIZE_OFFSET;
  880. value |= (1 & CODA_SLICING_UNIT_MASK)
  881. << CODA_SLICING_UNIT_OFFSET;
  882. value |= 1 & CODA_SLICING_MODE_MASK;
  883. break;
  884. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  885. value = (ctx->params.slice_max_bits &
  886. CODA_SLICING_SIZE_MASK)
  887. << CODA_SLICING_SIZE_OFFSET;
  888. value |= (0 & CODA_SLICING_UNIT_MASK)
  889. << CODA_SLICING_UNIT_OFFSET;
  890. value |= 1 & CODA_SLICING_MODE_MASK;
  891. break;
  892. }
  893. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  894. value = ctx->params.gop_size;
  895. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  896. }
  897. if (ctx->params.bitrate) {
  898. /* Rate control enabled */
  899. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  900. << CODA_RATECONTROL_BITRATE_OFFSET;
  901. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  902. value |= (ctx->params.vbv_delay &
  903. CODA_RATECONTROL_INITIALDELAY_MASK)
  904. << CODA_RATECONTROL_INITIALDELAY_OFFSET;
  905. if (dev->devtype->product == CODA_960)
  906. value |= BIT(31); /* disable autoskip */
  907. } else {
  908. value = 0;
  909. }
  910. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  911. coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  912. coda_write(dev, ctx->params.intra_refresh,
  913. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  914. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  915. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  916. value = 0;
  917. if (dev->devtype->product == CODA_960)
  918. gamma = CODA9_DEFAULT_GAMMA;
  919. else
  920. gamma = CODA_DEFAULT_GAMMA;
  921. if (gamma > 0) {
  922. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  923. CODA_CMD_ENC_SEQ_RC_GAMMA);
  924. }
  925. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  926. coda_write(dev,
  927. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  928. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  929. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  930. }
  931. if (dev->devtype->product == CODA_960) {
  932. if (ctx->params.h264_max_qp)
  933. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  934. if (CODA_DEFAULT_GAMMA > 0)
  935. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  936. } else {
  937. if (CODA_DEFAULT_GAMMA > 0) {
  938. if (dev->devtype->product == CODA_DX6)
  939. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  940. else
  941. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  942. }
  943. if (ctx->params.h264_min_qp)
  944. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  945. if (ctx->params.h264_max_qp)
  946. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  947. }
  948. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  949. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  950. coda_setup_iram(ctx);
  951. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  952. switch (dev->devtype->product) {
  953. case CODA_DX6:
  954. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  955. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  956. break;
  957. case CODA_HX4:
  958. case CODA_7541:
  959. coda_write(dev, ctx->iram_info.search_ram_paddr,
  960. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  961. coda_write(dev, ctx->iram_info.search_ram_size,
  962. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  963. break;
  964. case CODA_960:
  965. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  966. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  967. }
  968. }
  969. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  970. if (ret < 0) {
  971. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  972. goto out;
  973. }
  974. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  975. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  976. ret = -EFAULT;
  977. goto out;
  978. }
  979. ctx->initialized = 1;
  980. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  981. if (dev->devtype->product == CODA_960)
  982. ctx->num_internal_frames = 4;
  983. else
  984. ctx->num_internal_frames = 2;
  985. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  986. if (ret < 0) {
  987. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  988. goto out;
  989. }
  990. num_fb = 2;
  991. stride = q_data_src->bytesperline;
  992. } else {
  993. ctx->num_internal_frames = 0;
  994. num_fb = 0;
  995. stride = 0;
  996. }
  997. coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
  998. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  999. if (dev->devtype->product == CODA_HX4 ||
  1000. dev->devtype->product == CODA_7541) {
  1001. coda_write(dev, q_data_src->bytesperline,
  1002. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  1003. }
  1004. if (dev->devtype->product != CODA_DX6) {
  1005. coda_write(dev, ctx->iram_info.buf_bit_use,
  1006. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1007. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1008. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1009. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1010. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1011. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1012. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1013. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1014. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1015. if (dev->devtype->product == CODA_960) {
  1016. coda_write(dev, ctx->iram_info.buf_btp_use,
  1017. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1018. coda9_set_frame_cache(ctx, q_data_src->fourcc);
  1019. /* FIXME */
  1020. coda_write(dev, ctx->internal_frames[2].paddr,
  1021. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  1022. coda_write(dev, ctx->internal_frames[3].paddr,
  1023. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  1024. }
  1025. }
  1026. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  1027. if (ret < 0) {
  1028. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1029. goto out;
  1030. }
  1031. /* Save stream headers */
  1032. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1033. switch (dst_fourcc) {
  1034. case V4L2_PIX_FMT_H264:
  1035. /*
  1036. * Get SPS in the first frame and copy it to an
  1037. * intermediate buffer.
  1038. */
  1039. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  1040. &ctx->vpu_header[0][0],
  1041. &ctx->vpu_header_size[0]);
  1042. if (ret < 0)
  1043. goto out;
  1044. /*
  1045. * If visible width or height are not aligned to macroblock
  1046. * size, the crop_right and crop_bottom SPS fields must be set
  1047. * to the difference between visible and coded size. This is
  1048. * only supported by CODA960 firmware. All others do not allow
  1049. * writing frame cropping parameters, so we have to manually
  1050. * fix up the SPS RBSP (Sequence Parameter Set Raw Byte
  1051. * Sequence Payload) ourselves.
  1052. */
  1053. if (ctx->dev->devtype->product != CODA_960 &&
  1054. ((q_data_src->rect.width % 16) ||
  1055. (q_data_src->rect.height % 16))) {
  1056. ret = coda_h264_sps_fixup(ctx, q_data_src->rect.width,
  1057. q_data_src->rect.height,
  1058. &ctx->vpu_header[0][0],
  1059. &ctx->vpu_header_size[0],
  1060. sizeof(ctx->vpu_header[0]));
  1061. if (ret < 0)
  1062. goto out;
  1063. }
  1064. /*
  1065. * Get PPS in the first frame and copy it to an
  1066. * intermediate buffer.
  1067. */
  1068. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  1069. &ctx->vpu_header[1][0],
  1070. &ctx->vpu_header_size[1]);
  1071. if (ret < 0)
  1072. goto out;
  1073. /*
  1074. * Length of H.264 headers is variable and thus it might not be
  1075. * aligned for the coda to append the encoded frame. In that is
  1076. * the case a filler NAL must be added to header 2.
  1077. */
  1078. ctx->vpu_header_size[2] = coda_h264_padding(
  1079. (ctx->vpu_header_size[0] +
  1080. ctx->vpu_header_size[1]),
  1081. ctx->vpu_header[2]);
  1082. break;
  1083. case V4L2_PIX_FMT_MPEG4:
  1084. /*
  1085. * Get VOS in the first frame and copy it to an
  1086. * intermediate buffer
  1087. */
  1088. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  1089. &ctx->vpu_header[0][0],
  1090. &ctx->vpu_header_size[0]);
  1091. if (ret < 0)
  1092. goto out;
  1093. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  1094. &ctx->vpu_header[1][0],
  1095. &ctx->vpu_header_size[1]);
  1096. if (ret < 0)
  1097. goto out;
  1098. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  1099. &ctx->vpu_header[2][0],
  1100. &ctx->vpu_header_size[2]);
  1101. if (ret < 0)
  1102. goto out;
  1103. break;
  1104. default:
  1105. /* No more formats need to save headers at the moment */
  1106. break;
  1107. }
  1108. out:
  1109. mutex_unlock(&dev->coda_mutex);
  1110. return ret;
  1111. }
  1112. static int coda_prepare_encode(struct coda_ctx *ctx)
  1113. {
  1114. struct coda_q_data *q_data_src, *q_data_dst;
  1115. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  1116. struct coda_dev *dev = ctx->dev;
  1117. int force_ipicture;
  1118. int quant_param = 0;
  1119. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  1120. u32 rot_mode = 0;
  1121. u32 dst_fourcc;
  1122. u32 reg;
  1123. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  1124. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1125. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1126. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1127. dst_fourcc = q_data_dst->fourcc;
  1128. src_buf->sequence = ctx->osequence;
  1129. dst_buf->sequence = ctx->osequence;
  1130. ctx->osequence++;
  1131. force_ipicture = ctx->params.force_ipicture;
  1132. if (force_ipicture)
  1133. ctx->params.force_ipicture = false;
  1134. else if (ctx->params.gop_size != 0 &&
  1135. (src_buf->sequence % ctx->params.gop_size) == 0)
  1136. force_ipicture = 1;
  1137. /*
  1138. * Workaround coda firmware BUG that only marks the first
  1139. * frame as IDR. This is a problem for some decoders that can't
  1140. * recover when a frame is lost.
  1141. */
  1142. if (!force_ipicture) {
  1143. src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
  1144. src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1145. } else {
  1146. src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
  1147. src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
  1148. }
  1149. if (dev->devtype->product == CODA_960)
  1150. coda_set_gdi_regs(ctx);
  1151. /*
  1152. * Copy headers in front of the first frame and forced I frames for
  1153. * H.264 only. In MPEG4 they are already copied by the CODA.
  1154. */
  1155. if (src_buf->sequence == 0 || force_ipicture) {
  1156. pic_stream_buffer_addr =
  1157. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
  1158. ctx->vpu_header_size[0] +
  1159. ctx->vpu_header_size[1] +
  1160. ctx->vpu_header_size[2];
  1161. pic_stream_buffer_size = q_data_dst->sizeimage -
  1162. ctx->vpu_header_size[0] -
  1163. ctx->vpu_header_size[1] -
  1164. ctx->vpu_header_size[2];
  1165. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
  1166. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  1167. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
  1168. + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
  1169. ctx->vpu_header_size[1]);
  1170. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
  1171. + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
  1172. &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
  1173. } else {
  1174. pic_stream_buffer_addr =
  1175. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
  1176. pic_stream_buffer_size = q_data_dst->sizeimage;
  1177. }
  1178. if (force_ipicture) {
  1179. switch (dst_fourcc) {
  1180. case V4L2_PIX_FMT_H264:
  1181. quant_param = ctx->params.h264_intra_qp;
  1182. break;
  1183. case V4L2_PIX_FMT_MPEG4:
  1184. quant_param = ctx->params.mpeg4_intra_qp;
  1185. break;
  1186. case V4L2_PIX_FMT_JPEG:
  1187. quant_param = 30;
  1188. break;
  1189. default:
  1190. v4l2_warn(&ctx->dev->v4l2_dev,
  1191. "cannot set intra qp, fmt not supported\n");
  1192. break;
  1193. }
  1194. } else {
  1195. switch (dst_fourcc) {
  1196. case V4L2_PIX_FMT_H264:
  1197. quant_param = ctx->params.h264_inter_qp;
  1198. break;
  1199. case V4L2_PIX_FMT_MPEG4:
  1200. quant_param = ctx->params.mpeg4_inter_qp;
  1201. break;
  1202. default:
  1203. v4l2_warn(&ctx->dev->v4l2_dev,
  1204. "cannot set inter qp, fmt not supported\n");
  1205. break;
  1206. }
  1207. }
  1208. /* submit */
  1209. if (ctx->params.rot_mode)
  1210. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1211. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1212. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1213. if (dev->devtype->product == CODA_960) {
  1214. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1215. coda_write(dev, q_data_src->bytesperline,
  1216. CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1217. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1218. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1219. } else {
  1220. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1221. }
  1222. coda_write_base(ctx, q_data_src, src_buf, reg);
  1223. coda_write(dev, force_ipicture << 1 & 0x2,
  1224. CODA_CMD_ENC_PIC_OPTION);
  1225. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1226. coda_write(dev, pic_stream_buffer_size / 1024,
  1227. CODA_CMD_ENC_PIC_BB_SIZE);
  1228. if (!ctx->streamon_out) {
  1229. /* After streamoff on the output side, set stream end flag */
  1230. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1231. coda_write(dev, ctx->bit_stream_param,
  1232. CODA_REG_BIT_BIT_STREAM_PARAM);
  1233. }
  1234. if (dev->devtype->product != CODA_DX6)
  1235. coda_write(dev, ctx->iram_info.axi_sram_use,
  1236. CODA7_REG_BIT_AXI_SRAM_USE);
  1237. trace_coda_enc_pic_run(ctx, src_buf);
  1238. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1239. return 0;
  1240. }
  1241. static void coda_finish_encode(struct coda_ctx *ctx)
  1242. {
  1243. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  1244. struct coda_dev *dev = ctx->dev;
  1245. u32 wr_ptr, start_ptr;
  1246. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1247. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1248. trace_coda_enc_pic_done(ctx, dst_buf);
  1249. /* Get results from the coda */
  1250. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1251. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1252. /* Calculate bytesused field */
  1253. if (dst_buf->sequence == 0 ||
  1254. src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
  1255. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
  1256. ctx->vpu_header_size[0] +
  1257. ctx->vpu_header_size[1] +
  1258. ctx->vpu_header_size[2]);
  1259. } else {
  1260. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
  1261. }
  1262. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1263. wr_ptr - start_ptr);
  1264. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1265. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1266. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1267. dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
  1268. dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
  1269. } else {
  1270. dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
  1271. dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1272. }
  1273. dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
  1274. dst_buf->field = src_buf->field;
  1275. dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1276. dst_buf->flags |=
  1277. src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1278. dst_buf->timecode = src_buf->timecode;
  1279. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1280. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1281. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
  1282. ctx->gopcounter--;
  1283. if (ctx->gopcounter < 0)
  1284. ctx->gopcounter = ctx->params.gop_size - 1;
  1285. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1286. "job finished: encoding frame (%d) (%s)\n",
  1287. dst_buf->sequence,
  1288. (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1289. "KEYFRAME" : "PFRAME");
  1290. }
  1291. static void coda_seq_end_work(struct work_struct *work)
  1292. {
  1293. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1294. struct coda_dev *dev = ctx->dev;
  1295. mutex_lock(&ctx->buffer_mutex);
  1296. mutex_lock(&dev->coda_mutex);
  1297. if (ctx->initialized == 0)
  1298. goto out;
  1299. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1300. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1301. __func__);
  1302. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1303. v4l2_err(&dev->v4l2_dev,
  1304. "CODA_COMMAND_SEQ_END failed\n");
  1305. }
  1306. /*
  1307. * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
  1308. * from the output stream after the h.264 decoder has run. Resetting the
  1309. * hardware after the decoder has finished seems to help.
  1310. */
  1311. if (dev->devtype->product == CODA_960)
  1312. coda_hw_reset(ctx);
  1313. kfifo_init(&ctx->bitstream_fifo,
  1314. ctx->bitstream.vaddr, ctx->bitstream.size);
  1315. coda_free_framebuffers(ctx);
  1316. ctx->initialized = 0;
  1317. out:
  1318. mutex_unlock(&dev->coda_mutex);
  1319. mutex_unlock(&ctx->buffer_mutex);
  1320. }
  1321. static void coda_bit_release(struct coda_ctx *ctx)
  1322. {
  1323. mutex_lock(&ctx->buffer_mutex);
  1324. coda_free_framebuffers(ctx);
  1325. coda_free_context_buffers(ctx);
  1326. coda_free_bitstream_buffer(ctx);
  1327. mutex_unlock(&ctx->buffer_mutex);
  1328. }
  1329. const struct coda_context_ops coda_bit_encode_ops = {
  1330. .queue_init = coda_encoder_queue_init,
  1331. .reqbufs = coda_encoder_reqbufs,
  1332. .start_streaming = coda_start_encoding,
  1333. .prepare_run = coda_prepare_encode,
  1334. .finish_run = coda_finish_encode,
  1335. .seq_end_work = coda_seq_end_work,
  1336. .release = coda_bit_release,
  1337. };
  1338. /*
  1339. * Decoder context operations
  1340. */
  1341. static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
  1342. struct coda_q_data *q_data)
  1343. {
  1344. if (ctx->bitstream.vaddr)
  1345. return 0;
  1346. ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
  1347. ctx->bitstream.vaddr = dma_alloc_wc(&ctx->dev->plat_dev->dev,
  1348. ctx->bitstream.size,
  1349. &ctx->bitstream.paddr, GFP_KERNEL);
  1350. if (!ctx->bitstream.vaddr) {
  1351. v4l2_err(&ctx->dev->v4l2_dev,
  1352. "failed to allocate bitstream ringbuffer");
  1353. return -ENOMEM;
  1354. }
  1355. kfifo_init(&ctx->bitstream_fifo,
  1356. ctx->bitstream.vaddr, ctx->bitstream.size);
  1357. return 0;
  1358. }
  1359. static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
  1360. {
  1361. if (ctx->bitstream.vaddr == NULL)
  1362. return;
  1363. dma_free_wc(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1364. ctx->bitstream.vaddr, ctx->bitstream.paddr);
  1365. ctx->bitstream.vaddr = NULL;
  1366. kfifo_init(&ctx->bitstream_fifo, NULL, 0);
  1367. }
  1368. static int coda_decoder_reqbufs(struct coda_ctx *ctx,
  1369. struct v4l2_requestbuffers *rb)
  1370. {
  1371. struct coda_q_data *q_data_src;
  1372. int ret;
  1373. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1374. return 0;
  1375. if (rb->count) {
  1376. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1377. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1378. if (ret < 0)
  1379. return ret;
  1380. ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
  1381. if (ret < 0) {
  1382. coda_free_context_buffers(ctx);
  1383. return ret;
  1384. }
  1385. } else {
  1386. coda_free_bitstream_buffer(ctx);
  1387. coda_free_context_buffers(ctx);
  1388. }
  1389. return 0;
  1390. }
  1391. static bool coda_reorder_enable(struct coda_ctx *ctx)
  1392. {
  1393. struct coda_dev *dev = ctx->dev;
  1394. int profile;
  1395. if (dev->devtype->product != CODA_HX4 &&
  1396. dev->devtype->product != CODA_7541 &&
  1397. dev->devtype->product != CODA_960)
  1398. return false;
  1399. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1400. return false;
  1401. if (ctx->codec->src_fourcc != V4L2_PIX_FMT_H264)
  1402. return true;
  1403. profile = coda_h264_profile(ctx->params.h264_profile_idc);
  1404. if (profile < 0)
  1405. v4l2_warn(&dev->v4l2_dev, "Unknown H264 Profile: %u\n",
  1406. ctx->params.h264_profile_idc);
  1407. /* Baseline profile does not support reordering */
  1408. return profile > V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
  1409. }
  1410. static int __coda_start_decoding(struct coda_ctx *ctx)
  1411. {
  1412. struct coda_q_data *q_data_src, *q_data_dst;
  1413. u32 bitstream_buf, bitstream_size;
  1414. struct coda_dev *dev = ctx->dev;
  1415. int width, height;
  1416. u32 src_fourcc, dst_fourcc;
  1417. u32 val;
  1418. int ret;
  1419. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1420. "Video Data Order Adapter: %s\n",
  1421. ctx->use_vdoa ? "Enabled" : "Disabled");
  1422. /* Start decoding */
  1423. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1424. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1425. bitstream_buf = ctx->bitstream.paddr;
  1426. bitstream_size = ctx->bitstream.size;
  1427. src_fourcc = q_data_src->fourcc;
  1428. dst_fourcc = q_data_dst->fourcc;
  1429. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1430. /* Update coda bitstream read and write pointers from kfifo */
  1431. coda_kfifo_sync_to_device_full(ctx);
  1432. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  1433. CODA9_FRAME_TILED2LINEAR);
  1434. if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
  1435. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1436. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  1437. ctx->frame_mem_ctrl |= (0x3 << 9) |
  1438. ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
  1439. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1440. ctx->display_idx = -1;
  1441. ctx->frm_dis_flg = 0;
  1442. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1443. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1444. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1445. val = 0;
  1446. if (coda_reorder_enable(ctx))
  1447. val |= CODA_REORDER_ENABLE;
  1448. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1449. val |= CODA_NO_INT_ENABLE;
  1450. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1451. ctx->params.codec_mode = ctx->codec->mode;
  1452. if (dev->devtype->product == CODA_960 &&
  1453. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1454. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1455. else
  1456. ctx->params.codec_mode_aux = 0;
  1457. if (src_fourcc == V4L2_PIX_FMT_MPEG4) {
  1458. coda_write(dev, CODA_MP4_CLASS_MPEG4,
  1459. CODA_CMD_DEC_SEQ_MP4_ASP_CLASS);
  1460. }
  1461. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1462. if (dev->devtype->product == CODA_HX4 ||
  1463. dev->devtype->product == CODA_7541) {
  1464. coda_write(dev, ctx->psbuf.paddr,
  1465. CODA_CMD_DEC_SEQ_PS_BB_START);
  1466. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1467. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1468. }
  1469. if (dev->devtype->product == CODA_960) {
  1470. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1471. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1472. }
  1473. }
  1474. if (src_fourcc == V4L2_PIX_FMT_JPEG)
  1475. coda_write(dev, 0, CODA_CMD_DEC_SEQ_JPG_THUMB_EN);
  1476. if (dev->devtype->product != CODA_960)
  1477. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1478. ctx->bit_stream_param = CODA_BIT_DEC_SEQ_INIT_ESCAPE;
  1479. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  1480. ctx->bit_stream_param = 0;
  1481. if (ret) {
  1482. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1483. return ret;
  1484. }
  1485. ctx->sequence_offset = ~0U;
  1486. ctx->initialized = 1;
  1487. /* Update kfifo out pointer from coda bitstream read pointer */
  1488. coda_kfifo_sync_from_device(ctx);
  1489. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1490. v4l2_err(&dev->v4l2_dev,
  1491. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1492. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1493. return -EAGAIN;
  1494. }
  1495. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1496. if (dev->devtype->product == CODA_DX6) {
  1497. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1498. height = val & CODADX6_PICHEIGHT_MASK;
  1499. } else {
  1500. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1501. height = val & CODA7_PICHEIGHT_MASK;
  1502. }
  1503. if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
  1504. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1505. width, height, q_data_dst->bytesperline,
  1506. q_data_dst->height);
  1507. return -EINVAL;
  1508. }
  1509. width = round_up(width, 16);
  1510. height = round_up(height, 16);
  1511. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1512. __func__, ctx->idx, width, height);
  1513. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1514. /*
  1515. * If the VDOA is used, the decoder needs one additional frame,
  1516. * because the frames are freed when the next frame is decoded.
  1517. * Otherwise there are visible errors in the decoded frames (green
  1518. * regions in displayed frames) and a broken order of frames (earlier
  1519. * frames are sporadically displayed after later frames).
  1520. */
  1521. if (ctx->use_vdoa)
  1522. ctx->num_internal_frames += 1;
  1523. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1524. v4l2_err(&dev->v4l2_dev,
  1525. "not enough framebuffers to decode (%d < %d)\n",
  1526. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1527. return -EINVAL;
  1528. }
  1529. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1530. u32 left_right;
  1531. u32 top_bottom;
  1532. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1533. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1534. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1535. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1536. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1537. (left_right & 0x3ff);
  1538. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1539. (top_bottom & 0x3ff);
  1540. }
  1541. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1542. if (ret < 0) {
  1543. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1544. return ret;
  1545. }
  1546. /* Tell the decoder how many frame buffers we allocated. */
  1547. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1548. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1549. if (dev->devtype->product != CODA_DX6) {
  1550. /* Set secondary AXI IRAM */
  1551. coda_setup_iram(ctx);
  1552. coda_write(dev, ctx->iram_info.buf_bit_use,
  1553. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1554. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1555. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1556. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1557. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1558. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1559. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1560. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1561. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1562. if (dev->devtype->product == CODA_960) {
  1563. coda_write(dev, ctx->iram_info.buf_btp_use,
  1564. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1565. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1566. coda9_set_frame_cache(ctx, dst_fourcc);
  1567. }
  1568. }
  1569. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1570. coda_write(dev, ctx->slicebuf.paddr,
  1571. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1572. coda_write(dev, ctx->slicebuf.size / 1024,
  1573. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1574. }
  1575. if (dev->devtype->product == CODA_HX4 ||
  1576. dev->devtype->product == CODA_7541) {
  1577. int max_mb_x = 1920 / 16;
  1578. int max_mb_y = 1088 / 16;
  1579. int max_mb_num = max_mb_x * max_mb_y;
  1580. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1581. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1582. } else if (dev->devtype->product == CODA_960) {
  1583. int max_mb_x = 1920 / 16;
  1584. int max_mb_y = 1088 / 16;
  1585. int max_mb_num = max_mb_x * max_mb_y;
  1586. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1587. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1588. }
  1589. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1590. v4l2_err(&ctx->dev->v4l2_dev,
  1591. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1592. return -ETIMEDOUT;
  1593. }
  1594. return 0;
  1595. }
  1596. static int coda_start_decoding(struct coda_ctx *ctx)
  1597. {
  1598. struct coda_dev *dev = ctx->dev;
  1599. int ret;
  1600. mutex_lock(&dev->coda_mutex);
  1601. ret = __coda_start_decoding(ctx);
  1602. mutex_unlock(&dev->coda_mutex);
  1603. return ret;
  1604. }
  1605. static int coda_prepare_decode(struct coda_ctx *ctx)
  1606. {
  1607. struct vb2_v4l2_buffer *dst_buf;
  1608. struct coda_dev *dev = ctx->dev;
  1609. struct coda_q_data *q_data_dst;
  1610. struct coda_buffer_meta *meta;
  1611. unsigned long flags;
  1612. u32 rot_mode = 0;
  1613. u32 reg_addr, reg_stride;
  1614. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1615. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1616. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1617. mutex_lock(&ctx->bitstream_mutex);
  1618. coda_fill_bitstream(ctx, NULL);
  1619. mutex_unlock(&ctx->bitstream_mutex);
  1620. if (coda_get_bitstream_payload(ctx) < 512 &&
  1621. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1622. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1623. "bitstream payload: %d, skipping\n",
  1624. coda_get_bitstream_payload(ctx));
  1625. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1626. return -EAGAIN;
  1627. }
  1628. /* Run coda_start_decoding (again) if not yet initialized */
  1629. if (!ctx->initialized) {
  1630. int ret = __coda_start_decoding(ctx);
  1631. if (ret < 0) {
  1632. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1633. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1634. return -EAGAIN;
  1635. } else {
  1636. ctx->initialized = 1;
  1637. }
  1638. }
  1639. if (dev->devtype->product == CODA_960)
  1640. coda_set_gdi_regs(ctx);
  1641. if (ctx->use_vdoa &&
  1642. ctx->display_idx >= 0 &&
  1643. ctx->display_idx < ctx->num_internal_frames) {
  1644. vdoa_device_run(ctx->vdoa,
  1645. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0),
  1646. ctx->internal_frames[ctx->display_idx].paddr);
  1647. } else {
  1648. if (dev->devtype->product == CODA_960) {
  1649. /*
  1650. * The CODA960 seems to have an internal list of
  1651. * buffers with 64 entries that includes the
  1652. * registered frame buffers as well as the rotator
  1653. * buffer output.
  1654. *
  1655. * ROT_INDEX needs to be < 0x40, but >
  1656. * ctx->num_internal_frames.
  1657. */
  1658. coda_write(dev,
  1659. CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
  1660. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1661. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1662. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1663. } else {
  1664. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1665. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1666. }
  1667. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1668. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1669. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1670. }
  1671. coda_write(dev, rot_mode, CODA_CMD_DEC_PIC_ROT_MODE);
  1672. switch (dev->devtype->product) {
  1673. case CODA_DX6:
  1674. /* TBD */
  1675. case CODA_HX4:
  1676. case CODA_7541:
  1677. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1678. break;
  1679. case CODA_960:
  1680. /* 'hardcode to use interrupt disable mode'? */
  1681. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1682. break;
  1683. }
  1684. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1685. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1686. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1687. if (dev->devtype->product != CODA_DX6)
  1688. coda_write(dev, ctx->iram_info.axi_sram_use,
  1689. CODA7_REG_BIT_AXI_SRAM_USE);
  1690. spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
  1691. meta = list_first_entry_or_null(&ctx->buffer_meta_list,
  1692. struct coda_buffer_meta, list);
  1693. if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1694. /* If this is the last buffer in the bitstream, add padding */
  1695. if (meta->end == (ctx->bitstream_fifo.kfifo.in &
  1696. ctx->bitstream_fifo.kfifo.mask)) {
  1697. static unsigned char buf[512];
  1698. unsigned int pad;
  1699. /* Pad to multiple of 256 and then add 256 more */
  1700. pad = ((0 - meta->end) & 0xff) + 256;
  1701. memset(buf, 0xff, sizeof(buf));
  1702. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1703. }
  1704. }
  1705. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1706. coda_kfifo_sync_to_device_full(ctx);
  1707. /* Clear decode success flag */
  1708. coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
  1709. /* Clear error return value */
  1710. coda_write(dev, 0, CODA_RET_DEC_PIC_ERR_MB);
  1711. trace_coda_dec_pic_run(ctx, meta);
  1712. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1713. return 0;
  1714. }
  1715. static void coda_finish_decode(struct coda_ctx *ctx)
  1716. {
  1717. struct coda_dev *dev = ctx->dev;
  1718. struct coda_q_data *q_data_src;
  1719. struct coda_q_data *q_data_dst;
  1720. struct vb2_v4l2_buffer *dst_buf;
  1721. struct coda_buffer_meta *meta;
  1722. unsigned long payload;
  1723. unsigned long flags;
  1724. int width, height;
  1725. int decoded_idx;
  1726. int display_idx;
  1727. u32 src_fourcc;
  1728. int success;
  1729. u32 err_mb;
  1730. int err_vdoa = 0;
  1731. u32 val;
  1732. /* Update kfifo out pointer from coda bitstream read pointer */
  1733. coda_kfifo_sync_from_device(ctx);
  1734. /*
  1735. * in stream-end mode, the read pointer can overshoot the write pointer
  1736. * by up to 512 bytes
  1737. */
  1738. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1739. if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
  1740. kfifo_init(&ctx->bitstream_fifo,
  1741. ctx->bitstream.vaddr, ctx->bitstream.size);
  1742. }
  1743. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1744. src_fourcc = q_data_src->fourcc;
  1745. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1746. if (val != 1)
  1747. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1748. success = val & 0x1;
  1749. if (!success)
  1750. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1751. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1752. if (val & (1 << 3))
  1753. v4l2_err(&dev->v4l2_dev,
  1754. "insufficient PS buffer space (%d bytes)\n",
  1755. ctx->psbuf.size);
  1756. if (val & (1 << 2))
  1757. v4l2_err(&dev->v4l2_dev,
  1758. "insufficient slice buffer space (%d bytes)\n",
  1759. ctx->slicebuf.size);
  1760. }
  1761. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1762. width = (val >> 16) & 0xffff;
  1763. height = val & 0xffff;
  1764. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1765. /* frame crop information */
  1766. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1767. u32 left_right;
  1768. u32 top_bottom;
  1769. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1770. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1771. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1772. /* Keep current crop information */
  1773. } else {
  1774. struct v4l2_rect *rect = &q_data_dst->rect;
  1775. rect->left = left_right >> 16 & 0xffff;
  1776. rect->top = top_bottom >> 16 & 0xffff;
  1777. rect->width = width - rect->left -
  1778. (left_right & 0xffff);
  1779. rect->height = height - rect->top -
  1780. (top_bottom & 0xffff);
  1781. }
  1782. } else {
  1783. /* no cropping */
  1784. }
  1785. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1786. if (err_mb > 0)
  1787. v4l2_err(&dev->v4l2_dev,
  1788. "errors in %d macroblocks\n", err_mb);
  1789. if (dev->devtype->product == CODA_HX4 ||
  1790. dev->devtype->product == CODA_7541) {
  1791. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1792. if (val == 0) {
  1793. /* not enough bitstream data */
  1794. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1795. "prescan failed: %d\n", val);
  1796. ctx->hold = true;
  1797. return;
  1798. }
  1799. }
  1800. /* Wait until the VDOA finished writing the previous display frame */
  1801. if (ctx->use_vdoa &&
  1802. ctx->display_idx >= 0 &&
  1803. ctx->display_idx < ctx->num_internal_frames) {
  1804. err_vdoa = vdoa_wait_for_completion(ctx->vdoa);
  1805. }
  1806. ctx->frm_dis_flg = coda_read(dev,
  1807. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1808. /* The previous display frame was copied out and can be overwritten */
  1809. if (ctx->display_idx >= 0 &&
  1810. ctx->display_idx < ctx->num_internal_frames) {
  1811. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1812. coda_write(dev, ctx->frm_dis_flg,
  1813. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1814. }
  1815. /*
  1816. * The index of the last decoded frame, not necessarily in
  1817. * display order, and the index of the next display frame.
  1818. * The latter could have been decoded in a previous run.
  1819. */
  1820. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1821. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1822. if (decoded_idx == -1) {
  1823. /* no frame was decoded, but we might have a display frame */
  1824. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1825. ctx->sequence_offset++;
  1826. else if (ctx->display_idx < 0)
  1827. ctx->hold = true;
  1828. } else if (decoded_idx == -2) {
  1829. if (ctx->display_idx >= 0 &&
  1830. ctx->display_idx < ctx->num_internal_frames)
  1831. ctx->sequence_offset++;
  1832. /* no frame was decoded, we still return remaining buffers */
  1833. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1834. v4l2_err(&dev->v4l2_dev,
  1835. "decoded frame index out of range: %d\n", decoded_idx);
  1836. } else {
  1837. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM);
  1838. if (ctx->sequence_offset == -1)
  1839. ctx->sequence_offset = val;
  1840. val -= ctx->sequence_offset;
  1841. spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
  1842. if (!list_empty(&ctx->buffer_meta_list)) {
  1843. meta = list_first_entry(&ctx->buffer_meta_list,
  1844. struct coda_buffer_meta, list);
  1845. list_del(&meta->list);
  1846. ctx->num_metas--;
  1847. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1848. /*
  1849. * Clamp counters to 16 bits for comparison, as the HW
  1850. * counter rolls over at this point for h.264. This
  1851. * may be different for other formats, but using 16 bits
  1852. * should be enough to detect most errors and saves us
  1853. * from doing different things based on the format.
  1854. */
  1855. if ((val & 0xffff) != (meta->sequence & 0xffff)) {
  1856. v4l2_err(&dev->v4l2_dev,
  1857. "sequence number mismatch (%d(%d) != %d)\n",
  1858. val, ctx->sequence_offset,
  1859. meta->sequence);
  1860. }
  1861. ctx->frame_metas[decoded_idx] = *meta;
  1862. kfree(meta);
  1863. } else {
  1864. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1865. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1866. memset(&ctx->frame_metas[decoded_idx], 0,
  1867. sizeof(struct coda_buffer_meta));
  1868. ctx->frame_metas[decoded_idx].sequence = val;
  1869. ctx->sequence_offset++;
  1870. }
  1871. trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
  1872. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1873. if (val == 0)
  1874. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1875. else if (val == 1)
  1876. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1877. else
  1878. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1879. ctx->frame_errors[decoded_idx] = err_mb;
  1880. }
  1881. if (display_idx == -1) {
  1882. /*
  1883. * no more frames to be decoded, but there could still
  1884. * be rotator output to dequeue
  1885. */
  1886. ctx->hold = true;
  1887. } else if (display_idx == -3) {
  1888. /* possibly prescan failure */
  1889. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1890. v4l2_err(&dev->v4l2_dev,
  1891. "presentation frame index out of range: %d\n",
  1892. display_idx);
  1893. }
  1894. /* If a frame was copied out, return it */
  1895. if (ctx->display_idx >= 0 &&
  1896. ctx->display_idx < ctx->num_internal_frames) {
  1897. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1898. dst_buf->sequence = ctx->osequence++;
  1899. dst_buf->field = V4L2_FIELD_NONE;
  1900. dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1901. V4L2_BUF_FLAG_PFRAME |
  1902. V4L2_BUF_FLAG_BFRAME);
  1903. dst_buf->flags |= ctx->frame_types[ctx->display_idx];
  1904. meta = &ctx->frame_metas[ctx->display_idx];
  1905. dst_buf->timecode = meta->timecode;
  1906. dst_buf->vb2_buf.timestamp = meta->timestamp;
  1907. trace_coda_dec_rot_done(ctx, dst_buf, meta);
  1908. switch (q_data_dst->fourcc) {
  1909. case V4L2_PIX_FMT_YUYV:
  1910. payload = width * height * 2;
  1911. break;
  1912. case V4L2_PIX_FMT_YUV420:
  1913. case V4L2_PIX_FMT_YVU420:
  1914. case V4L2_PIX_FMT_NV12:
  1915. default:
  1916. payload = width * height * 3 / 2;
  1917. break;
  1918. case V4L2_PIX_FMT_YUV422P:
  1919. payload = width * height * 2;
  1920. break;
  1921. }
  1922. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
  1923. if (ctx->frame_errors[ctx->display_idx] || err_vdoa)
  1924. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
  1925. else
  1926. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
  1927. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1928. "job finished: decoding frame (%d) (%s)\n",
  1929. dst_buf->sequence,
  1930. (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1931. "KEYFRAME" : "PFRAME");
  1932. } else {
  1933. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1934. "job finished: no frame decoded\n");
  1935. }
  1936. /* The rotator will copy the current display frame next time */
  1937. ctx->display_idx = display_idx;
  1938. }
  1939. static void coda_decode_timeout(struct coda_ctx *ctx)
  1940. {
  1941. struct vb2_v4l2_buffer *dst_buf;
  1942. /*
  1943. * For now this only handles the case where we would deadlock with
  1944. * userspace, i.e. userspace issued DEC_CMD_STOP and waits for EOS,
  1945. * but after a failed decode run we would hold the context and wait for
  1946. * userspace to queue more buffers.
  1947. */
  1948. if (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))
  1949. return;
  1950. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1951. dst_buf->sequence = ctx->qsequence - 1;
  1952. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
  1953. }
  1954. const struct coda_context_ops coda_bit_decode_ops = {
  1955. .queue_init = coda_decoder_queue_init,
  1956. .reqbufs = coda_decoder_reqbufs,
  1957. .start_streaming = coda_start_decoding,
  1958. .prepare_run = coda_prepare_decode,
  1959. .finish_run = coda_finish_decode,
  1960. .run_timeout = coda_decode_timeout,
  1961. .seq_end_work = coda_seq_end_work,
  1962. .release = coda_bit_release,
  1963. };
  1964. irqreturn_t coda_irq_handler(int irq, void *data)
  1965. {
  1966. struct coda_dev *dev = data;
  1967. struct coda_ctx *ctx;
  1968. /* read status register to attend the IRQ */
  1969. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1970. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1971. CODA_REG_BIT_INT_CLEAR);
  1972. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1973. if (ctx == NULL) {
  1974. v4l2_err(&dev->v4l2_dev,
  1975. "Instance released before the end of transaction\n");
  1976. return IRQ_HANDLED;
  1977. }
  1978. trace_coda_bit_done(ctx);
  1979. if (ctx->aborting) {
  1980. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1981. "task has been aborted\n");
  1982. }
  1983. if (coda_isbusy(ctx->dev)) {
  1984. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1985. "coda is still busy!!!!\n");
  1986. return IRQ_NONE;
  1987. }
  1988. complete(&ctx->completion);
  1989. return IRQ_HANDLED;
  1990. }