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port.h

port.h 15 KB
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  1. /*
    2. 

  2.  * Marvell 88E6xxx Switch Port Registers support
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2008 Marvell Semiconductor
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
    7. 

  7.  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License as published by
    11. 

  11.  * the Free Software Foundation; either version 2 of the License, or
    12. 

  12.  * (at your option) any later version.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef _MV88E6XXX_PORT_H
    16. 

  16. #define _MV88E6XXX_PORT_H
    17. 

  17. 

  18. #include "chip.h"
    19. 

  19. 

  20. /* Offset 0x00: Port Status Register */
    21. 

  21. #define MV88E6XXX_PORT_STS			0x00
    22. 

  22. #define MV88E6XXX_PORT_STS_PAUSE_EN		0x8000
    23. 

  23. #define MV88E6XXX_PORT_STS_MY_PAUSE		0x4000
    24. 

  24. #define MV88E6XXX_PORT_STS_HD_FLOW		0x2000
    25. 

  25. #define MV88E6XXX_PORT_STS_PHY_DETECT		0x1000
    26. 

  26. #define MV88E6XXX_PORT_STS_LINK			0x0800
    27. 

  27. #define MV88E6XXX_PORT_STS_DUPLEX		0x0400
    28. 

  28. #define MV88E6XXX_PORT_STS_SPEED_MASK		0x0300
    29. 

  29. #define MV88E6XXX_PORT_STS_SPEED_10		0x0000
    30. 

  30. #define MV88E6XXX_PORT_STS_SPEED_100		0x0100
    31. 

  31. #define MV88E6XXX_PORT_STS_SPEED_1000		0x0200
    32. 

  32. #define MV88E6XXX_PORT_STS_SPEED_10000		0x0300
    33. 

  33. #define MV88E6352_PORT_STS_EEE			0x0040
    34. 

  34. #define MV88E6165_PORT_STS_AM_DIS		0x0040
    35. 

  35. #define MV88E6185_PORT_STS_MGMII		0x0040
    36. 

  36. #define MV88E6XXX_PORT_STS_TX_PAUSED		0x0020
    37. 

  37. #define MV88E6XXX_PORT_STS_FLOW_CTL		0x0010
    38. 

  38. #define MV88E6XXX_PORT_STS_CMODE_MASK		0x000f
    39. 

  39. #define MV88E6XXX_PORT_STS_CMODE_100BASE_X	0x0008
    40. 

  40. #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X	0x0009
    41. 

  41. #define MV88E6XXX_PORT_STS_CMODE_SGMII		0x000a
    42. 

  42. #define MV88E6XXX_PORT_STS_CMODE_2500BASEX	0x000b
    43. 

  43. #define MV88E6XXX_PORT_STS_CMODE_XAUI		0x000c
    44. 

  44. #define MV88E6XXX_PORT_STS_CMODE_RXAUI		0x000d
    45. 

  45. #define MV88E6185_PORT_STS_CDUPLEX		0x0008
    46. 

  46. #define MV88E6185_PORT_STS_CMODE_MASK		0x0007
    47. 

  47. #define MV88E6185_PORT_STS_CMODE_GMII_FD	0x0000
    48. 

  48. #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS	0x0001
    49. 

  49. #define MV88E6185_PORT_STS_CMODE_MII_100	0x0002
    50. 

  50. #define MV88E6185_PORT_STS_CMODE_MII_10		0x0003
    51. 

  51. #define MV88E6185_PORT_STS_CMODE_SERDES		0x0004
    52. 

  52. #define MV88E6185_PORT_STS_CMODE_1000BASE_X	0x0005
    53. 

  53. #define MV88E6185_PORT_STS_CMODE_PHY		0x0006
    54. 

  54. #define MV88E6185_PORT_STS_CMODE_DISABLED	0x0007
    55. 

  55. #define MV88E6XXX_PORT_STS_CMODE_INVALID	0xff
    56. 

  56. 

  57. /* Offset 0x01: MAC (or PCS or Physical) Control Register */
    58. 

  58. #define MV88E6XXX_PORT_MAC_CTL				0x01
    59. 

  59. #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK	0x8000
    60. 

  60. #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK	0x4000
    61. 

  61. #define MV88E6185_PORT_MAC_CTL_SYNC_OK			0x4000
    62. 

  62. #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED		0x2000
    63. 

  63. #define MV88E6390_PORT_MAC_CTL_ALTSPEED			0x1000
    64. 

  64. #define MV88E6352_PORT_MAC_CTL_200BASE			0x1000
    65. 

  65. #define MV88E6185_PORT_MAC_CTL_AN_EN			0x0400
    66. 

  66. #define MV88E6185_PORT_MAC_CTL_AN_RESTART		0x0200
    67. 

  67. #define MV88E6185_PORT_MAC_CTL_AN_DONE			0x0100
    68. 

  68. #define MV88E6XXX_PORT_MAC_CTL_FC			0x0080
    69. 

  69. #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC			0x0040
    70. 

  70. #define MV88E6XXX_PORT_MAC_CTL_LINK_UP			0x0020
    71. 

  71. #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK		0x0010
    72. 

  72. #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL		0x0008
    73. 

  73. #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX		0x0004
    74. 

  74. #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK		0x0003
    75. 

  75. #define MV88E6XXX_PORT_MAC_CTL_SPEED_10			0x0000
    76. 

  76. #define MV88E6XXX_PORT_MAC_CTL_SPEED_100		0x0001
    77. 

  77. #define MV88E6065_PORT_MAC_CTL_SPEED_200		0x0002
    78. 

  78. #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000		0x0002
    79. 

  79. #define MV88E6390_PORT_MAC_CTL_SPEED_10000		0x0003
    80. 

  80. #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED		0x0003
    81. 

  81. 

  82. /* Offset 0x02: Jamming Control Register */
    83. 

  83. #define MV88E6097_PORT_JAM_CTL			0x02
    84. 

  84. #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK	0xff00
    85. 

  85. #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK	0x00ff
    86. 

  86. 

  87. /* Offset 0x02: Flow Control Register */
    88. 

  88. #define MV88E6390_PORT_FLOW_CTL			0x02
    89. 

  89. #define MV88E6390_PORT_FLOW_CTL_UPDATE		0x8000
    90. 

  90. #define MV88E6390_PORT_FLOW_CTL_PTR_MASK	0x7f00
    91. 

  91. #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN	0x0000
    92. 

  92. #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT	0x0100
    93. 

  93. #define MV88E6390_PORT_FLOW_CTL_DATA_MASK	0x00ff
    94. 

  94. 

  95. /* Offset 0x03: Switch Identifier Register */
    96. 

  96. #define MV88E6XXX_PORT_SWITCH_ID		0x03
    97. 

  97. #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK	0xfff0
    98. 

  98. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085	0x04a0
    99. 

  99. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095	0x0950
    100. 

  100. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097	0x0990
    101. 

  101. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X	0x0a00
    102. 

  102. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X	0x0a10
    103. 

  103. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131	0x1060
    104. 

  104. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320	0x1150
    105. 

  105. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123	0x1210
    106. 

  106. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161	0x1610
    107. 

  107. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165	0x1650
    108. 

  108. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171	0x1710
    109. 

  109. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172	0x1720
    110. 

  110. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175	0x1750
    111. 

  111. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176	0x1760
    112. 

  112. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190	0x1900
    113. 

  113. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191	0x1910
    114. 

  114. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185	0x1a70
    115. 

  115. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240	0x2400
    116. 

  116. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290	0x2900
    117. 

  117. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321	0x3100
    118. 

  118. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141	0x3400
    119. 

  119. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341	0x3410
    120. 

  120. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352	0x3520
    121. 

  121. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350	0x3710
    122. 

  122. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351	0x3750
    123. 

  123. #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390	0x3900
    124. 

  124. #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK	0x000f
    125. 

  125. 

  126. /* Offset 0x04: Port Control Register */
    127. 

  127. #define MV88E6XXX_PORT_CTL0					0x04
    128. 

  128. #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG			0x8000
    129. 

  129. #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK			0x4000
    130. 

  130. #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK			0x3000
    131. 

  131. #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED		0x0000
    132. 

  132. #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED		0x1000
    133. 

  133. #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED			0x2000
    134. 

  134. #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA		0x3000
    135. 

  135. #define MV88E6XXX_PORT_CTL0_HEADER				0x0800
    136. 

  136. #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP			0x0400
    137. 

  137. #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG				0x0200
    138. 

  138. #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK			0x0300
    139. 

  139. #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL			0x0000
    140. 

  140. #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA			0x0100
    141. 

  141. #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER			0x0200
    142. 

  142. #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA		0x0300
    143. 

  143. #define MV88E6XXX_PORT_CTL0_DSA_TAG				0x0100
    144. 

  144. #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL				0x0080
    145. 

  145. #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH				0x0040
    146. 

  146. #define MV88E6185_PORT_CTL0_USE_IP				0x0020
    147. 

  147. #define MV88E6185_PORT_CTL0_USE_TAG				0x0010
    148. 

  148. #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN			0x0004
    149. 

  149. #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK			0x000c
    150. 

  150. #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA		0x0000
    151. 

  151. #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	0x0004
    152. 

  152. #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	0x0008
    153. 

  153. #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA	0x000c
    154. 

  154. #define MV88E6XXX_PORT_CTL0_STATE_MASK				0x0003
    155. 

  155. #define MV88E6XXX_PORT_CTL0_STATE_DISABLED			0x0000
    156. 

  156. #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING			0x0001
    157. 

  157. #define MV88E6XXX_PORT_CTL0_STATE_LEARNING			0x0002
    158. 

  158. #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING			0x0003
    159. 

  159. 

  160. /* Offset 0x05: Port Control 1 */
    161. 

  161. #define MV88E6XXX_PORT_CTL1			0x05
    162. 

  162. #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT	0x8000
    163. 

  163. #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK	0x00ff
    164. 

  164. 

  165. /* Offset 0x06: Port Based VLAN Map */
    166. 

  166. #define MV88E6XXX_PORT_BASE_VLAN		0x06
    167. 

  167. #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK	0xf000
    168. 

  168. 

  169. /* Offset 0x07: Default Port VLAN ID & Priority */
    170. 

  170. #define MV88E6XXX_PORT_DEFAULT_VLAN		0x07
    171. 

  171. #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK	0x0fff
    172. 

  172. 

  173. /* Offset 0x08: Port Control 2 Register */
    174. 

  174. #define MV88E6XXX_PORT_CTL2				0x08
    175. 

  175. #define MV88E6XXX_PORT_CTL2_IGNORE_FCS			0x8000
    176. 

  176. #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE		0x4000
    177. 

  177. #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE		0x2000
    178. 

  178. #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE		0x1000
    179. 

  179. #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK		0x3000
    180. 

  180. #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522		0x0000
    181. 

  181. #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048		0x1000
    182. 

  182. #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240		0x2000
    183. 

  183. #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK		0x0c00
    184. 

  184. #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED		0x0000
    185. 

  185. #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK		0x0400
    186. 

  186. #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK		0x0800
    187. 

  187. #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE		0x0c00
    188. 

  188. #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED		0x0200
    189. 

  189. #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED		0x0100
    190. 

  190. #define MV88E6XXX_PORT_CTL2_MAP_DA			0x0080
    191. 

  191. #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD		0x0040
    192. 

  192. #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR		0x0020
    193. 

  193. #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR		0x0010
    194. 

  194. #define MV88E6095_PORT_CTL2_CPU_PORT_MASK		0x000f
    195. 

  195. 

  196. /* Offset 0x09: Egress Rate Control */
    197. 

  197. #define MV88E6XXX_PORT_EGRESS_RATE_CTL1		0x09
    198. 

  198. 

  199. /* Offset 0x0A: Egress Rate Control 2 */
    200. 

  200. #define MV88E6XXX_PORT_EGRESS_RATE_CTL2		0x0a
    201. 

  201. 

  202. /* Offset 0x0B: Port Association Vector */
    203. 

  203. #define MV88E6XXX_PORT_ASSOC_VECTOR			0x0b
    204. 

  204. #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1		0x8000
    205. 

  205. #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT		0x4000
    206. 

  206. #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT		0x2000
    207. 

  207. #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG	0x1000
    208. 

  208. #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED	0x0800
    209. 

  209. 

  210. /* Offset 0x0C: Port ATU Control */
    211. 

  211. #define MV88E6XXX_PORT_ATU_CTL		0x0c
    212. 

  212. 

  213. /* Offset 0x0D: Priority Override Register */
    214. 

  214. #define MV88E6XXX_PORT_PRI_OVERRIDE	0x0d
    215. 

  215. 

  216. /* Offset 0x0E: Policy Control Register */
    217. 

  217. #define MV88E6XXX_PORT_POLICY_CTL	0x0e
    218. 

  218. 

  219. /* Offset 0x0F: Port Special Ether Type */
    220. 

  220. #define MV88E6XXX_PORT_ETH_TYPE		0x0f
    221. 

  221. #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT	0x9100
    222. 

  222. 

  223. /* Offset 0x10: InDiscards Low Counter */
    224. 

  224. #define MV88E6XXX_PORT_IN_DISCARD_LO	0x10
    225. 

  225. 

  226. /* Offset 0x11: InDiscards High Counter */
    227. 

  227. #define MV88E6XXX_PORT_IN_DISCARD_HI	0x11
    228. 

  228. 

  229. /* Offset 0x12: InFiltered Counter */
    230. 

  230. #define MV88E6XXX_PORT_IN_FILTERED	0x12
    231. 

  231. 

  232. /* Offset 0x13: OutFiltered Counter */
    233. 

  233. #define MV88E6XXX_PORT_OUT_FILTERED	0x13
    234. 

  234. 

  235. /* Offset 0x18: IEEE Priority Mapping Table */
    236. 

  236. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE			0x18
    237. 

  237. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE		0x8000
    238. 

  238. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK			0x7000
    239. 

  239. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		0x0000
    240. 

  240. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	0x1000
    241. 

  241. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	0x2000
    242. 

  242. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP	0x3000
    243. 

  243. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	0x5000
    244. 

  244. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	0x6000
    245. 

  245. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	0x7000
    246. 

  246. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK		0x0e00
    247. 

  247. #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK		0x01ff
    248. 

  248. 

  249. /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
    250. 

  250. #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123	0x18
    251. 

  251. 

  252. /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
    253. 

  253. #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567	0x19
    254. 

  254. 

  255. /* Offset 0x1a: Magic undocumented errata register */
    256. 

  256. #define PORT_RESERVED_1A			0x1a
    257. 

  257. #define PORT_RESERVED_1A_BUSY			BIT(15)
    258. 

  258. #define PORT_RESERVED_1A_WRITE			BIT(14)
    259. 

  259. #define PORT_RESERVED_1A_READ			0
    260. 

  260. #define PORT_RESERVED_1A_PORT_SHIFT		5
    261. 

  261. #define PORT_RESERVED_1A_BLOCK			(0xf << 10)
    262. 

  262. #define PORT_RESERVED_1A_CTRL_PORT		4
    263. 

  263. #define PORT_RESERVED_1A_DATA_PORT		5
    264. 

  264. 

  265. int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
    266. 

  266. 			u16 *val);
    267. 

  267. int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
    268. 

  268. 			 u16 val);
    269. 

  269. 

  270. int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
    271. 

  271. 			     int pause);
    272. 

  272. int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
    273. 

  273. 				   phy_interface_t mode);
    274. 

  274. int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
    275. 

  275. 				   phy_interface_t mode);
    276. 

  276. 

  277. int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
    278. 

  278. 

  279. int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
    280. 

  280. 

  281. int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
    282. 

  282. int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
    283. 

  283. int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
    284. 

  284. int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
    285. 

  285. int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
    286. 

  286. int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
    287. 

  287. 

  288. int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
    289. 

  289. 

  290. int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
    291. 

  291. 

  292. int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
    293. 

  293. int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
    294. 

  294. 

  295. int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
    296. 

  296. int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
    297. 

  297. 

  298. int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
    299. 

  299. 				  u16 mode);
    300. 

  300. int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
    301. 

  301. int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
    302. 

  302. int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
    303. 

  303. 				   enum mv88e6xxx_egress_mode mode);
    304. 

  304. int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
    305. 

  305. 				  enum mv88e6xxx_frame_mode mode);
    306. 

  306. int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
    307. 

  307. 				  enum mv88e6xxx_frame_mode mode);
    308. 

  308. int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
    309. 

  309. 				     bool unicast, bool multicast);
    310. 

  310. int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
    311. 

  311. 				     bool unicast, bool multicast);
    312. 

  312. int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
    313. 

  313. 				  u16 etype);
    314. 

  314. int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
    315. 

  315. 				    bool message_port);
    316. 

  316. int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
    317. 

  317. 				  size_t size);
    318. 

  318. int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
    319. 

  319. int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
    320. 

  320. int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
    321. 

  321. 			       u8 out);
    322. 

  322. int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
    323. 

  323. 			       u8 out);
    324. 

  324. int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
    325. 

  325. 			      phy_interface_t mode);
    326. 

  326. int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
    327. 

  327. int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
    328. 

  328. int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
    329. 

  329. 			      struct phylink_link_state *state);
    330. 

  330. int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
    331. 

  331. 			      struct phylink_link_state *state);
    332. 

  332. int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
    333. 

  333. int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
    334. 

  334. 				     int upstream_port);
    335. 

  335. 

  336. int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
    337. 

  337. int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
    338. 

  338. 

  339. #endif /* _MV88E6XXX_PORT_H */
    340.