qca_spi.c 24 KB

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  1. /*
  2. * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
  3. * Copyright (c) 2014, I2SE GmbH
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software
  6. * for any purpose with or without fee is hereby granted, provided
  7. * that the above copyright notice and this permission notice appear
  8. * in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
  13. * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
  14. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  15. * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
  16. * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. /* This module implements the Qualcomm Atheros SPI protocol for
  20. * kernel-based SPI device; it is essentially an Ethernet-to-SPI
  21. * serial converter;
  22. */
  23. #include <linux/errno.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/if_arp.h>
  26. #include <linux/if_ether.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/jiffies.h>
  30. #include <linux/kernel.h>
  31. #include <linux/kthread.h>
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/of.h>
  36. #include <linux/of_device.h>
  37. #include <linux/of_net.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/spi/spi.h>
  41. #include <linux/types.h>
  42. #include "qca_7k.h"
  43. #include "qca_7k_common.h"
  44. #include "qca_debug.h"
  45. #include "qca_spi.h"
  46. #define MAX_DMA_BURST_LEN 5000
  47. /* Modules parameters */
  48. #define QCASPI_CLK_SPEED_MIN 1000000
  49. #define QCASPI_CLK_SPEED_MAX 16000000
  50. #define QCASPI_CLK_SPEED 8000000
  51. static int qcaspi_clkspeed;
  52. module_param(qcaspi_clkspeed, int, 0);
  53. MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
  54. #define QCASPI_BURST_LEN_MIN 1
  55. #define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
  56. static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
  57. module_param(qcaspi_burst_len, int, 0);
  58. MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
  59. #define QCASPI_PLUGGABLE_MIN 0
  60. #define QCASPI_PLUGGABLE_MAX 1
  61. static int qcaspi_pluggable = QCASPI_PLUGGABLE_MIN;
  62. module_param(qcaspi_pluggable, int, 0);
  63. MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
  64. #define QCASPI_TX_TIMEOUT (1 * HZ)
  65. #define QCASPI_QCA7K_REBOOT_TIME_MS 1000
  66. static void
  67. start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
  68. {
  69. *intr_cause = 0;
  70. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  71. qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  72. netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
  73. }
  74. static void
  75. end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
  76. {
  77. u16 intr_enable = (SPI_INT_CPU_ON |
  78. SPI_INT_PKT_AVLBL |
  79. SPI_INT_RDBUF_ERR |
  80. SPI_INT_WRBUF_ERR);
  81. qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  82. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable);
  83. netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
  84. }
  85. static u32
  86. qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
  87. {
  88. __be16 cmd;
  89. struct spi_message msg;
  90. struct spi_transfer transfer[2];
  91. int ret;
  92. memset(&transfer, 0, sizeof(transfer));
  93. spi_message_init(&msg);
  94. cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  95. transfer[0].tx_buf = &cmd;
  96. transfer[0].len = QCASPI_CMD_LEN;
  97. transfer[1].tx_buf = src;
  98. transfer[1].len = len;
  99. spi_message_add_tail(&transfer[0], &msg);
  100. spi_message_add_tail(&transfer[1], &msg);
  101. ret = spi_sync(qca->spi_dev, &msg);
  102. if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
  103. qcaspi_spi_error(qca);
  104. return 0;
  105. }
  106. return len;
  107. }
  108. static u32
  109. qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
  110. {
  111. struct spi_message msg;
  112. struct spi_transfer transfer;
  113. int ret;
  114. memset(&transfer, 0, sizeof(transfer));
  115. spi_message_init(&msg);
  116. transfer.tx_buf = src;
  117. transfer.len = len;
  118. spi_message_add_tail(&transfer, &msg);
  119. ret = spi_sync(qca->spi_dev, &msg);
  120. if (ret || (msg.actual_length != len)) {
  121. qcaspi_spi_error(qca);
  122. return 0;
  123. }
  124. return len;
  125. }
  126. static u32
  127. qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
  128. {
  129. struct spi_message msg;
  130. __be16 cmd;
  131. struct spi_transfer transfer[2];
  132. int ret;
  133. memset(&transfer, 0, sizeof(transfer));
  134. spi_message_init(&msg);
  135. cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  136. transfer[0].tx_buf = &cmd;
  137. transfer[0].len = QCASPI_CMD_LEN;
  138. transfer[1].rx_buf = dst;
  139. transfer[1].len = len;
  140. spi_message_add_tail(&transfer[0], &msg);
  141. spi_message_add_tail(&transfer[1], &msg);
  142. ret = spi_sync(qca->spi_dev, &msg);
  143. if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
  144. qcaspi_spi_error(qca);
  145. return 0;
  146. }
  147. return len;
  148. }
  149. static u32
  150. qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
  151. {
  152. struct spi_message msg;
  153. struct spi_transfer transfer;
  154. int ret;
  155. memset(&transfer, 0, sizeof(transfer));
  156. spi_message_init(&msg);
  157. transfer.rx_buf = dst;
  158. transfer.len = len;
  159. spi_message_add_tail(&transfer, &msg);
  160. ret = spi_sync(qca->spi_dev, &msg);
  161. if (ret || (msg.actual_length != len)) {
  162. qcaspi_spi_error(qca);
  163. return 0;
  164. }
  165. return len;
  166. }
  167. static int
  168. qcaspi_tx_cmd(struct qcaspi *qca, u16 cmd)
  169. {
  170. __be16 tx_data;
  171. struct spi_message msg;
  172. struct spi_transfer transfer;
  173. int ret;
  174. memset(&transfer, 0, sizeof(transfer));
  175. spi_message_init(&msg);
  176. tx_data = cpu_to_be16(cmd);
  177. transfer.len = sizeof(cmd);
  178. transfer.tx_buf = &tx_data;
  179. spi_message_add_tail(&transfer, &msg);
  180. ret = spi_sync(qca->spi_dev, &msg);
  181. if (!ret)
  182. ret = msg.status;
  183. if (ret)
  184. qcaspi_spi_error(qca);
  185. return ret;
  186. }
  187. static int
  188. qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
  189. {
  190. u32 count;
  191. u32 written;
  192. u32 offset;
  193. u32 len;
  194. len = skb->len;
  195. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len);
  196. if (qca->legacy_mode)
  197. qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  198. offset = 0;
  199. while (len) {
  200. count = len;
  201. if (count > qca->burst_len)
  202. count = qca->burst_len;
  203. if (qca->legacy_mode) {
  204. written = qcaspi_write_legacy(qca,
  205. skb->data + offset,
  206. count);
  207. } else {
  208. written = qcaspi_write_burst(qca,
  209. skb->data + offset,
  210. count);
  211. }
  212. if (written != count)
  213. return -1;
  214. offset += count;
  215. len -= count;
  216. }
  217. return 0;
  218. }
  219. static int
  220. qcaspi_transmit(struct qcaspi *qca)
  221. {
  222. struct net_device_stats *n_stats = &qca->net_dev->stats;
  223. u16 available = 0;
  224. u32 pkt_len;
  225. u16 new_head;
  226. u16 packets = 0;
  227. if (qca->txr.skb[qca->txr.head] == NULL)
  228. return 0;
  229. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
  230. while (qca->txr.skb[qca->txr.head]) {
  231. pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
  232. if (available < pkt_len) {
  233. if (packets == 0)
  234. qca->stats.write_buf_miss++;
  235. break;
  236. }
  237. if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
  238. qca->stats.write_err++;
  239. return -1;
  240. }
  241. packets++;
  242. n_stats->tx_packets++;
  243. n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
  244. available -= pkt_len;
  245. /* remove the skb from the queue */
  246. /* XXX After inconsistent lock states netif_tx_lock()
  247. * has been replaced by netif_tx_lock_bh() and so on.
  248. */
  249. netif_tx_lock_bh(qca->net_dev);
  250. dev_kfree_skb(qca->txr.skb[qca->txr.head]);
  251. qca->txr.skb[qca->txr.head] = NULL;
  252. qca->txr.size -= pkt_len;
  253. new_head = qca->txr.head + 1;
  254. if (new_head >= qca->txr.count)
  255. new_head = 0;
  256. qca->txr.head = new_head;
  257. if (netif_queue_stopped(qca->net_dev))
  258. netif_wake_queue(qca->net_dev);
  259. netif_tx_unlock_bh(qca->net_dev);
  260. }
  261. return 0;
  262. }
  263. static int
  264. qcaspi_receive(struct qcaspi *qca)
  265. {
  266. struct net_device *net_dev = qca->net_dev;
  267. struct net_device_stats *n_stats = &net_dev->stats;
  268. u16 available = 0;
  269. u32 bytes_read;
  270. u8 *cp;
  271. /* Allocate rx SKB if we don't have one available. */
  272. if (!qca->rx_skb) {
  273. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  274. net_dev->mtu +
  275. VLAN_ETH_HLEN);
  276. if (!qca->rx_skb) {
  277. netdev_dbg(net_dev, "out of RX resources\n");
  278. qca->stats.out_of_mem++;
  279. return -1;
  280. }
  281. }
  282. /* Read the packet size. */
  283. qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
  284. netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %08x\n",
  285. available);
  286. if (available == 0) {
  287. netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
  288. return -1;
  289. }
  290. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available);
  291. if (qca->legacy_mode)
  292. qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  293. while (available) {
  294. u32 count = available;
  295. if (count > qca->burst_len)
  296. count = qca->burst_len;
  297. if (qca->legacy_mode) {
  298. bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
  299. count);
  300. } else {
  301. bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
  302. count);
  303. }
  304. netdev_dbg(net_dev, "available: %d, byte read: %d\n",
  305. available, bytes_read);
  306. if (bytes_read) {
  307. available -= bytes_read;
  308. } else {
  309. qca->stats.read_err++;
  310. return -1;
  311. }
  312. cp = qca->rx_buffer;
  313. while ((bytes_read--) && (qca->rx_skb)) {
  314. s32 retcode;
  315. retcode = qcafrm_fsm_decode(&qca->frm_handle,
  316. qca->rx_skb->data,
  317. skb_tailroom(qca->rx_skb),
  318. *cp);
  319. cp++;
  320. switch (retcode) {
  321. case QCAFRM_GATHER:
  322. case QCAFRM_NOHEAD:
  323. break;
  324. case QCAFRM_NOTAIL:
  325. netdev_dbg(net_dev, "no RX tail\n");
  326. n_stats->rx_errors++;
  327. n_stats->rx_dropped++;
  328. break;
  329. case QCAFRM_INVLEN:
  330. netdev_dbg(net_dev, "invalid RX length\n");
  331. n_stats->rx_errors++;
  332. n_stats->rx_dropped++;
  333. break;
  334. default:
  335. qca->rx_skb->dev = qca->net_dev;
  336. n_stats->rx_packets++;
  337. n_stats->rx_bytes += retcode;
  338. skb_put(qca->rx_skb, retcode);
  339. qca->rx_skb->protocol = eth_type_trans(
  340. qca->rx_skb, qca->rx_skb->dev);
  341. qca->rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
  342. netif_rx_ni(qca->rx_skb);
  343. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  344. net_dev->mtu + VLAN_ETH_HLEN);
  345. if (!qca->rx_skb) {
  346. netdev_dbg(net_dev, "out of RX resources\n");
  347. n_stats->rx_errors++;
  348. qca->stats.out_of_mem++;
  349. break;
  350. }
  351. }
  352. }
  353. }
  354. return 0;
  355. }
  356. /* Check that tx ring stores only so much bytes
  357. * that fit into the internal QCA buffer.
  358. */
  359. static int
  360. qcaspi_tx_ring_has_space(struct tx_ring *txr)
  361. {
  362. if (txr->skb[txr->tail])
  363. return 0;
  364. return (txr->size + QCAFRM_MAX_LEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
  365. }
  366. /* Flush the tx ring. This function is only safe to
  367. * call from the qcaspi_spi_thread.
  368. */
  369. static void
  370. qcaspi_flush_tx_ring(struct qcaspi *qca)
  371. {
  372. int i;
  373. /* XXX After inconsistent lock states netif_tx_lock()
  374. * has been replaced by netif_tx_lock_bh() and so on.
  375. */
  376. netif_tx_lock_bh(qca->net_dev);
  377. for (i = 0; i < TX_RING_MAX_LEN; i++) {
  378. if (qca->txr.skb[i]) {
  379. dev_kfree_skb(qca->txr.skb[i]);
  380. qca->txr.skb[i] = NULL;
  381. qca->net_dev->stats.tx_dropped++;
  382. }
  383. }
  384. qca->txr.tail = 0;
  385. qca->txr.head = 0;
  386. qca->txr.size = 0;
  387. netif_tx_unlock_bh(qca->net_dev);
  388. }
  389. static void
  390. qcaspi_qca7k_sync(struct qcaspi *qca, int event)
  391. {
  392. u16 signature = 0;
  393. u16 spi_config;
  394. u16 wrbuf_space = 0;
  395. if (event == QCASPI_EVENT_CPUON) {
  396. /* Read signature twice, if not valid
  397. * go back to unknown state.
  398. */
  399. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  400. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  401. if (signature != QCASPI_GOOD_SIGNATURE) {
  402. qca->sync = QCASPI_SYNC_UNKNOWN;
  403. netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
  404. } else {
  405. /* ensure that the WRBUF is empty */
  406. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
  407. &wrbuf_space);
  408. if (wrbuf_space != QCASPI_HW_BUF_LEN) {
  409. netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
  410. qca->sync = QCASPI_SYNC_UNKNOWN;
  411. } else {
  412. netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
  413. qca->sync = QCASPI_SYNC_READY;
  414. return;
  415. }
  416. }
  417. }
  418. switch (qca->sync) {
  419. case QCASPI_SYNC_READY:
  420. /* Read signature, if not valid go to unknown state. */
  421. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  422. if (signature != QCASPI_GOOD_SIGNATURE) {
  423. qca->sync = QCASPI_SYNC_UNKNOWN;
  424. netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
  425. /* don't reset right away */
  426. return;
  427. }
  428. break;
  429. case QCASPI_SYNC_UNKNOWN:
  430. /* Read signature, if not valid stay in unknown state */
  431. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  432. if (signature != QCASPI_GOOD_SIGNATURE) {
  433. netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
  434. return;
  435. }
  436. /* TODO: use GPIO to reset QCA7000 in legacy mode*/
  437. netdev_dbg(qca->net_dev, "sync: resetting device.\n");
  438. qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
  439. spi_config |= QCASPI_SLAVE_RESET_BIT;
  440. qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config);
  441. qca->sync = QCASPI_SYNC_RESET;
  442. qca->stats.trig_reset++;
  443. qca->reset_count = 0;
  444. break;
  445. case QCASPI_SYNC_RESET:
  446. qca->reset_count++;
  447. netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
  448. qca->reset_count);
  449. if (qca->reset_count >= QCASPI_RESET_TIMEOUT) {
  450. /* reset did not seem to take place, try again */
  451. qca->sync = QCASPI_SYNC_UNKNOWN;
  452. qca->stats.reset_timeout++;
  453. netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
  454. }
  455. break;
  456. }
  457. }
  458. static int
  459. qcaspi_spi_thread(void *data)
  460. {
  461. struct qcaspi *qca = data;
  462. u16 intr_cause = 0;
  463. netdev_info(qca->net_dev, "SPI thread created\n");
  464. while (!kthread_should_stop()) {
  465. set_current_state(TASK_INTERRUPTIBLE);
  466. if ((qca->intr_req == qca->intr_svc) &&
  467. (qca->txr.skb[qca->txr.head] == NULL) &&
  468. (qca->sync == QCASPI_SYNC_READY))
  469. schedule();
  470. set_current_state(TASK_RUNNING);
  471. netdev_dbg(qca->net_dev, "have work to do. int: %d, tx_skb: %p\n",
  472. qca->intr_req - qca->intr_svc,
  473. qca->txr.skb[qca->txr.head]);
  474. qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
  475. if (qca->sync != QCASPI_SYNC_READY) {
  476. netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
  477. (unsigned int)qca->sync);
  478. netif_stop_queue(qca->net_dev);
  479. netif_carrier_off(qca->net_dev);
  480. qcaspi_flush_tx_ring(qca);
  481. msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
  482. }
  483. if (qca->intr_svc != qca->intr_req) {
  484. qca->intr_svc = qca->intr_req;
  485. start_spi_intr_handling(qca, &intr_cause);
  486. if (intr_cause & SPI_INT_CPU_ON) {
  487. qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
  488. /* not synced. */
  489. if (qca->sync != QCASPI_SYNC_READY)
  490. continue;
  491. qca->stats.device_reset++;
  492. netif_wake_queue(qca->net_dev);
  493. netif_carrier_on(qca->net_dev);
  494. }
  495. if (intr_cause & SPI_INT_RDBUF_ERR) {
  496. /* restart sync */
  497. netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
  498. qca->stats.read_buf_err++;
  499. qca->sync = QCASPI_SYNC_UNKNOWN;
  500. continue;
  501. }
  502. if (intr_cause & SPI_INT_WRBUF_ERR) {
  503. /* restart sync */
  504. netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
  505. qca->stats.write_buf_err++;
  506. qca->sync = QCASPI_SYNC_UNKNOWN;
  507. continue;
  508. }
  509. /* can only handle other interrupts
  510. * if sync has occurred
  511. */
  512. if (qca->sync == QCASPI_SYNC_READY) {
  513. if (intr_cause & SPI_INT_PKT_AVLBL)
  514. qcaspi_receive(qca);
  515. }
  516. end_spi_intr_handling(qca, intr_cause);
  517. }
  518. if (qca->sync == QCASPI_SYNC_READY)
  519. qcaspi_transmit(qca);
  520. }
  521. set_current_state(TASK_RUNNING);
  522. netdev_info(qca->net_dev, "SPI thread exit\n");
  523. return 0;
  524. }
  525. static irqreturn_t
  526. qcaspi_intr_handler(int irq, void *data)
  527. {
  528. struct qcaspi *qca = data;
  529. qca->intr_req++;
  530. if (qca->spi_thread &&
  531. qca->spi_thread->state != TASK_RUNNING)
  532. wake_up_process(qca->spi_thread);
  533. return IRQ_HANDLED;
  534. }
  535. static int
  536. qcaspi_netdev_open(struct net_device *dev)
  537. {
  538. struct qcaspi *qca = netdev_priv(dev);
  539. int ret = 0;
  540. if (!qca)
  541. return -EINVAL;
  542. qca->intr_req = 1;
  543. qca->intr_svc = 0;
  544. qca->sync = QCASPI_SYNC_UNKNOWN;
  545. qcafrm_fsm_init_spi(&qca->frm_handle);
  546. qca->spi_thread = kthread_run((void *)qcaspi_spi_thread,
  547. qca, "%s", dev->name);
  548. if (IS_ERR(qca->spi_thread)) {
  549. netdev_err(dev, "%s: unable to start kernel thread.\n",
  550. QCASPI_DRV_NAME);
  551. return PTR_ERR(qca->spi_thread);
  552. }
  553. ret = request_irq(qca->spi_dev->irq, qcaspi_intr_handler, 0,
  554. dev->name, qca);
  555. if (ret) {
  556. netdev_err(dev, "%s: unable to get IRQ %d (irqval=%d).\n",
  557. QCASPI_DRV_NAME, qca->spi_dev->irq, ret);
  558. kthread_stop(qca->spi_thread);
  559. return ret;
  560. }
  561. /* SPI thread takes care of TX queue */
  562. return 0;
  563. }
  564. static int
  565. qcaspi_netdev_close(struct net_device *dev)
  566. {
  567. struct qcaspi *qca = netdev_priv(dev);
  568. netif_stop_queue(dev);
  569. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  570. free_irq(qca->spi_dev->irq, qca);
  571. kthread_stop(qca->spi_thread);
  572. qca->spi_thread = NULL;
  573. qcaspi_flush_tx_ring(qca);
  574. return 0;
  575. }
  576. static netdev_tx_t
  577. qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
  578. {
  579. u32 frame_len;
  580. u8 *ptmp;
  581. struct qcaspi *qca = netdev_priv(dev);
  582. u16 new_tail;
  583. struct sk_buff *tskb;
  584. u8 pad_len = 0;
  585. if (skb->len < QCAFRM_MIN_LEN)
  586. pad_len = QCAFRM_MIN_LEN - skb->len;
  587. if (qca->txr.skb[qca->txr.tail]) {
  588. netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
  589. netif_stop_queue(qca->net_dev);
  590. qca->stats.ring_full++;
  591. return NETDEV_TX_BUSY;
  592. }
  593. if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
  594. (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
  595. tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
  596. QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
  597. if (!tskb) {
  598. qca->stats.out_of_mem++;
  599. return NETDEV_TX_BUSY;
  600. }
  601. dev_kfree_skb(skb);
  602. skb = tskb;
  603. }
  604. frame_len = skb->len + pad_len;
  605. ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
  606. qcafrm_create_header(ptmp, frame_len);
  607. if (pad_len) {
  608. ptmp = skb_put_zero(skb, pad_len);
  609. }
  610. ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
  611. qcafrm_create_footer(ptmp);
  612. netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
  613. skb->len);
  614. qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
  615. new_tail = qca->txr.tail + 1;
  616. if (new_tail >= qca->txr.count)
  617. new_tail = 0;
  618. qca->txr.skb[qca->txr.tail] = skb;
  619. qca->txr.tail = new_tail;
  620. if (!qcaspi_tx_ring_has_space(&qca->txr)) {
  621. netif_stop_queue(qca->net_dev);
  622. qca->stats.ring_full++;
  623. }
  624. netif_trans_update(dev);
  625. if (qca->spi_thread &&
  626. qca->spi_thread->state != TASK_RUNNING)
  627. wake_up_process(qca->spi_thread);
  628. return NETDEV_TX_OK;
  629. }
  630. static void
  631. qcaspi_netdev_tx_timeout(struct net_device *dev)
  632. {
  633. struct qcaspi *qca = netdev_priv(dev);
  634. netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
  635. jiffies, jiffies - dev_trans_start(dev));
  636. qca->net_dev->stats.tx_errors++;
  637. /* Trigger tx queue flush and QCA7000 reset */
  638. qca->sync = QCASPI_SYNC_UNKNOWN;
  639. if (qca->spi_thread)
  640. wake_up_process(qca->spi_thread);
  641. }
  642. static int
  643. qcaspi_netdev_init(struct net_device *dev)
  644. {
  645. struct qcaspi *qca = netdev_priv(dev);
  646. dev->mtu = QCAFRM_MAX_MTU;
  647. dev->type = ARPHRD_ETHER;
  648. qca->clkspeed = qcaspi_clkspeed;
  649. qca->burst_len = qcaspi_burst_len;
  650. qca->spi_thread = NULL;
  651. qca->buffer_size = (dev->mtu + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
  652. QCAFRM_FOOTER_LEN + 4) * 4;
  653. memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
  654. qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
  655. if (!qca->rx_buffer)
  656. return -ENOBUFS;
  657. qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu +
  658. VLAN_ETH_HLEN);
  659. if (!qca->rx_skb) {
  660. kfree(qca->rx_buffer);
  661. netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
  662. return -ENOBUFS;
  663. }
  664. return 0;
  665. }
  666. static void
  667. qcaspi_netdev_uninit(struct net_device *dev)
  668. {
  669. struct qcaspi *qca = netdev_priv(dev);
  670. kfree(qca->rx_buffer);
  671. qca->buffer_size = 0;
  672. if (qca->rx_skb)
  673. dev_kfree_skb(qca->rx_skb);
  674. }
  675. static const struct net_device_ops qcaspi_netdev_ops = {
  676. .ndo_init = qcaspi_netdev_init,
  677. .ndo_uninit = qcaspi_netdev_uninit,
  678. .ndo_open = qcaspi_netdev_open,
  679. .ndo_stop = qcaspi_netdev_close,
  680. .ndo_start_xmit = qcaspi_netdev_xmit,
  681. .ndo_set_mac_address = eth_mac_addr,
  682. .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
  683. .ndo_validate_addr = eth_validate_addr,
  684. };
  685. static void
  686. qcaspi_netdev_setup(struct net_device *dev)
  687. {
  688. struct qcaspi *qca = NULL;
  689. dev->netdev_ops = &qcaspi_netdev_ops;
  690. qcaspi_set_ethtool_ops(dev);
  691. dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
  692. dev->priv_flags &= ~IFF_TX_SKB_SHARING;
  693. dev->tx_queue_len = 100;
  694. /* MTU range: 46 - 1500 */
  695. dev->min_mtu = QCAFRM_MIN_MTU;
  696. dev->max_mtu = QCAFRM_MAX_MTU;
  697. qca = netdev_priv(dev);
  698. memset(qca, 0, sizeof(struct qcaspi));
  699. memset(&qca->txr, 0, sizeof(qca->txr));
  700. qca->txr.count = TX_RING_MAX_LEN;
  701. }
  702. static const struct of_device_id qca_spi_of_match[] = {
  703. { .compatible = "qca,qca7000" },
  704. { /* sentinel */ }
  705. };
  706. MODULE_DEVICE_TABLE(of, qca_spi_of_match);
  707. static int
  708. qca_spi_probe(struct spi_device *spi)
  709. {
  710. struct qcaspi *qca = NULL;
  711. struct net_device *qcaspi_devs = NULL;
  712. u8 legacy_mode = 0;
  713. u16 signature;
  714. const char *mac;
  715. if (!spi->dev.of_node) {
  716. dev_err(&spi->dev, "Missing device tree\n");
  717. return -EINVAL;
  718. }
  719. legacy_mode = of_property_read_bool(spi->dev.of_node,
  720. "qca,legacy-mode");
  721. if (qcaspi_clkspeed == 0) {
  722. if (spi->max_speed_hz)
  723. qcaspi_clkspeed = spi->max_speed_hz;
  724. else
  725. qcaspi_clkspeed = QCASPI_CLK_SPEED;
  726. }
  727. if ((qcaspi_clkspeed < QCASPI_CLK_SPEED_MIN) ||
  728. (qcaspi_clkspeed > QCASPI_CLK_SPEED_MAX)) {
  729. dev_err(&spi->dev, "Invalid clkspeed: %d\n",
  730. qcaspi_clkspeed);
  731. return -EINVAL;
  732. }
  733. if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
  734. (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
  735. dev_err(&spi->dev, "Invalid burst len: %d\n",
  736. qcaspi_burst_len);
  737. return -EINVAL;
  738. }
  739. if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
  740. (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
  741. dev_err(&spi->dev, "Invalid pluggable: %d\n",
  742. qcaspi_pluggable);
  743. return -EINVAL;
  744. }
  745. dev_info(&spi->dev, "ver=%s, clkspeed=%d, burst_len=%d, pluggable=%d\n",
  746. QCASPI_DRV_VERSION,
  747. qcaspi_clkspeed,
  748. qcaspi_burst_len,
  749. qcaspi_pluggable);
  750. spi->mode = SPI_MODE_3;
  751. spi->max_speed_hz = qcaspi_clkspeed;
  752. if (spi_setup(spi) < 0) {
  753. dev_err(&spi->dev, "Unable to setup SPI device\n");
  754. return -EFAULT;
  755. }
  756. qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
  757. if (!qcaspi_devs)
  758. return -ENOMEM;
  759. qcaspi_netdev_setup(qcaspi_devs);
  760. SET_NETDEV_DEV(qcaspi_devs, &spi->dev);
  761. qca = netdev_priv(qcaspi_devs);
  762. if (!qca) {
  763. free_netdev(qcaspi_devs);
  764. dev_err(&spi->dev, "Fail to retrieve private structure\n");
  765. return -ENOMEM;
  766. }
  767. qca->net_dev = qcaspi_devs;
  768. qca->spi_dev = spi;
  769. qca->legacy_mode = legacy_mode;
  770. spi_set_drvdata(spi, qcaspi_devs);
  771. mac = of_get_mac_address(spi->dev.of_node);
  772. if (mac)
  773. ether_addr_copy(qca->net_dev->dev_addr, mac);
  774. if (!is_valid_ether_addr(qca->net_dev->dev_addr)) {
  775. eth_hw_addr_random(qca->net_dev);
  776. dev_info(&spi->dev, "Using random MAC address: %pM\n",
  777. qca->net_dev->dev_addr);
  778. }
  779. netif_carrier_off(qca->net_dev);
  780. if (!qcaspi_pluggable) {
  781. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  782. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  783. if (signature != QCASPI_GOOD_SIGNATURE) {
  784. dev_err(&spi->dev, "Invalid signature (0x%04X)\n",
  785. signature);
  786. free_netdev(qcaspi_devs);
  787. return -EFAULT;
  788. }
  789. }
  790. if (register_netdev(qcaspi_devs)) {
  791. dev_err(&spi->dev, "Unable to register net device %s\n",
  792. qcaspi_devs->name);
  793. free_netdev(qcaspi_devs);
  794. return -EFAULT;
  795. }
  796. qcaspi_init_device_debugfs(qca);
  797. return 0;
  798. }
  799. static int
  800. qca_spi_remove(struct spi_device *spi)
  801. {
  802. struct net_device *qcaspi_devs = spi_get_drvdata(spi);
  803. struct qcaspi *qca = netdev_priv(qcaspi_devs);
  804. qcaspi_remove_device_debugfs(qca);
  805. unregister_netdev(qcaspi_devs);
  806. free_netdev(qcaspi_devs);
  807. return 0;
  808. }
  809. static const struct spi_device_id qca_spi_id[] = {
  810. { "qca7000", 0 },
  811. { /* sentinel */ }
  812. };
  813. MODULE_DEVICE_TABLE(spi, qca_spi_id);
  814. static struct spi_driver qca_spi_driver = {
  815. .driver = {
  816. .name = QCASPI_DRV_NAME,
  817. .of_match_table = qca_spi_of_match,
  818. },
  819. .id_table = qca_spi_id,
  820. .probe = qca_spi_probe,
  821. .remove = qca_spi_remove,
  822. };
  823. module_spi_driver(qca_spi_driver);
  824. MODULE_DESCRIPTION("Qualcomm Atheros QCA7000 SPI Driver");
  825. MODULE_AUTHOR("Qualcomm Atheros Communications");
  826. MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
  827. MODULE_LICENSE("Dual BSD/GPL");
  828. MODULE_VERSION(QCASPI_DRV_VERSION);