ddr.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. #include <asm/immap_85xx.h>
  8. #include <asm/processor.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. #include <asm/io.h>
  12. #include <asm/fsl_law.h>
  13. #ifndef CONFIG_SYS_DDR_RAW_TIMING
  14. #define CONFIG_SYS_DRAM_SIZE 1024
  15. fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  16. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  17. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  18. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  19. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  20. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  21. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  22. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  23. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  24. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  25. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  26. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  27. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  28. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  29. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  30. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  31. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  32. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  33. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  34. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  35. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  36. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
  37. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  38. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  39. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  40. };
  41. fixed_ddr_parm_t fixed_ddr_parm_0[] = {
  42. {750, 850, &ddr_cfg_regs_800},
  43. {0, 0, NULL}
  44. };
  45. unsigned long get_sdram_size(void)
  46. {
  47. return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
  48. }
  49. /*
  50. * Fixed sdram init -- doesn't use serial presence detect.
  51. */
  52. phys_size_t fixed_sdram(void)
  53. {
  54. int i;
  55. char buf[32];
  56. fsl_ddr_cfg_regs_t ddr_cfg_regs;
  57. phys_size_t ddr_size;
  58. ulong ddr_freq, ddr_freq_mhz;
  59. ddr_freq = get_ddr_freq(0);
  60. ddr_freq_mhz = ddr_freq / 1000000;
  61. printf("Configuring DDR for %s MT/s data rate\n",
  62. strmhz(buf, ddr_freq));
  63. for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
  64. if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
  65. (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
  66. memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
  67. sizeof(ddr_cfg_regs));
  68. break;
  69. }
  70. }
  71. if (fixed_ddr_parm_0[i].max_freq == 0) {
  72. panic("Unsupported DDR data rate %s MT/s data rate\n",
  73. strmhz(buf, ddr_freq));
  74. }
  75. ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  76. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  77. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
  78. LAW_TRGT_IF_DDR_1) < 0) {
  79. printf("ERROR setting Local Access Windows for DDR\n");
  80. return 0;
  81. }
  82. return ddr_size;
  83. }
  84. #else /* CONFIG_SYS_DDR_RAW_TIMING */
  85. /* Micron MT41J256M8HX-15E */
  86. dimm_params_t ddr_raw_timing = {
  87. .n_ranks = 1,
  88. .rank_density = 1073741824u,
  89. .capacity = 1073741824u,
  90. .primary_sdram_width = 32,
  91. .ec_sdram_width = 0,
  92. .registered_dimm = 0,
  93. .mirrored_dimm = 0,
  94. .n_row_addr = 15,
  95. .n_col_addr = 10,
  96. .n_banks_per_sdram_device = 8,
  97. .edc_config = 0,
  98. .burst_lengths_bitmask = 0x0c,
  99. .tckmin_x_ps = 1870,
  100. .caslat_x = 0x1e << 4, /* 5,6,7,8 */
  101. .taa_ps = 13125,
  102. .twr_ps = 15000,
  103. .trcd_ps = 13125,
  104. .trrd_ps = 7500,
  105. .trp_ps = 13125,
  106. .tras_ps = 37500,
  107. .trc_ps = 50625,
  108. .trfc_ps = 160000,
  109. .twtr_ps = 7500,
  110. .trtp_ps = 7500,
  111. .refresh_rate_ps = 7800000,
  112. .tfaw_ps = 37500,
  113. };
  114. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  115. unsigned int controller_number,
  116. unsigned int dimm_number)
  117. {
  118. const char dimm_model[] = "Fixed DDR on board";
  119. if ((controller_number == 0) && (dimm_number == 0)) {
  120. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  121. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  122. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  123. }
  124. return 0;
  125. }
  126. void fsl_ddr_board_options(memctl_options_t *popts,
  127. dimm_params_t *pdimm,
  128. unsigned int ctrl_num)
  129. {
  130. int i;
  131. popts->clk_adjust = 6;
  132. popts->cpo_override = 0x1f;
  133. popts->write_data_delay = 2;
  134. popts->half_strength_driver_enable = 1;
  135. /* Write leveling override */
  136. popts->wrlvl_en = 1;
  137. popts->wrlvl_override = 1;
  138. popts->wrlvl_sample = 0xf;
  139. popts->wrlvl_start = 0x8;
  140. popts->trwt_override = 1;
  141. popts->trwt = 0;
  142. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  143. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  144. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  145. }
  146. }
  147. #endif /* CONFIG_SYS_DDR_RAW_TIMING */