diu.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  5. */
  6. #include <asm/io.h>
  7. #include <common.h>
  8. #include <command.h>
  9. #include <fsl_diu_fb.h>
  10. #include <linux/ctype.h>
  11. #include <video_fb.h>
  12. #include "../common/diu_ch7301.h"
  13. #include "cpld.h"
  14. #include "t104xrdb.h"
  15. /*
  16. * DIU Area Descriptor
  17. *
  18. * Note that we need to byte-swap the value before it's written to the AD
  19. * register. So even though the registers don't look like they're in the same
  20. * bit positions as they are on the MPC8610, the same value is written to the
  21. * AD register on the MPC8610 and on the P1022.
  22. */
  23. #define AD_BYTE_F 0x10000000
  24. #define AD_ALPHA_C_SHIFT 25
  25. #define AD_BLUE_C_SHIFT 23
  26. #define AD_GREEN_C_SHIFT 21
  27. #define AD_RED_C_SHIFT 19
  28. #define AD_PIXEL_S_SHIFT 16
  29. #define AD_COMP_3_SHIFT 12
  30. #define AD_COMP_2_SHIFT 8
  31. #define AD_COMP_1_SHIFT 4
  32. #define AD_COMP_0_SHIFT 0
  33. void diu_set_pixel_clock(unsigned int pixclock)
  34. {
  35. unsigned long speed_ccb, temp;
  36. u32 pixval;
  37. int ret;
  38. speed_ccb = get_bus_freq(0);
  39. temp = 1000000000 / pixclock;
  40. temp *= 1000;
  41. pixval = speed_ccb / temp;
  42. /* Program HDMI encoder */
  43. ret = diu_set_dvi_encoder(temp);
  44. if (ret) {
  45. puts("Failed to set DVI encoder\n");
  46. return;
  47. }
  48. /* Program pixel clock */
  49. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
  50. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  51. /* enable clock*/
  52. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
  53. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  54. }
  55. int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  56. {
  57. u32 pixel_format;
  58. u8 sw;
  59. /*Configure Display ouput port as HDMI*/
  60. sw = CPLD_READ(sfp_ctl_status);
  61. CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
  62. pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  63. (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  64. (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  65. (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  66. (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  67. printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
  68. return fsl_diu_init(xres, yres, pixel_format, 0);
  69. }