ena_netdev.h 9.1 KB

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  1. /*
  2. * Copyright 2015 Amazon.com, Inc. or its affiliates.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #ifndef ENA_H
  33. #define ENA_H
  34. #include <linux/bitops.h>
  35. #include <linux/etherdevice.h>
  36. #include <linux/inetdevice.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/skbuff.h>
  40. #include "ena_com.h"
  41. #include "ena_eth_com.h"
  42. #define DRV_MODULE_VER_MAJOR 1
  43. #define DRV_MODULE_VER_MINOR 5
  44. #define DRV_MODULE_VER_SUBMINOR 0
  45. #define DRV_MODULE_NAME "ena"
  46. #ifndef DRV_MODULE_VERSION
  47. #define DRV_MODULE_VERSION \
  48. __stringify(DRV_MODULE_VER_MAJOR) "." \
  49. __stringify(DRV_MODULE_VER_MINOR) "." \
  50. __stringify(DRV_MODULE_VER_SUBMINOR) "K"
  51. #endif
  52. #define DEVICE_NAME "Elastic Network Adapter (ENA)"
  53. /* 1 for AENQ + ADMIN */
  54. #define ENA_ADMIN_MSIX_VEC 1
  55. #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
  56. #define ENA_MIN_MSIX_VEC 2
  57. #define ENA_REG_BAR 0
  58. #define ENA_MEM_BAR 2
  59. #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
  60. #define ENA_DEFAULT_RING_SIZE (1024)
  61. #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2)
  62. #define ENA_DEFAULT_RX_COPYBREAK (128 - NET_IP_ALIGN)
  63. /* limit the buffer size to 600 bytes to handle MTU changes from very
  64. * small to very large, in which case the number of buffers per packet
  65. * could exceed ENA_PKT_MAX_BUFS
  66. */
  67. #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
  68. #define ENA_MIN_MTU 128
  69. #define ENA_NAME_MAX_LEN 20
  70. #define ENA_IRQNAME_SIZE 40
  71. #define ENA_PKT_MAX_BUFS 19
  72. #define ENA_RX_RSS_TABLE_LOG_SIZE 7
  73. #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  74. #define ENA_HASH_KEY_SIZE 40
  75. /* The number of tx packet completions that will be handled each NAPI poll
  76. * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
  77. */
  78. #define ENA_TX_POLL_BUDGET_DIVIDER 4
  79. /* Refill Rx queue when number of available descriptors is below
  80. * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER
  81. */
  82. #define ENA_RX_REFILL_THRESH_DIVIDER 8
  83. /* Number of queues to check for missing queues per timer service */
  84. #define ENA_MONITORED_TX_QUEUES 4
  85. /* Max timeout packets before device reset */
  86. #define MAX_NUM_OF_TIMEOUTED_PACKETS 128
  87. #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
  88. #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
  89. #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
  90. (((idx) + (n)) & ((ring_size) - 1))
  91. #define ENA_IO_TXQ_IDX(q) (2 * (q))
  92. #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
  93. #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
  94. #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
  95. #define ENA_MGMNT_IRQ_IDX 0
  96. #define ENA_IO_IRQ_FIRST_IDX 1
  97. #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
  98. /* ENA device should send keep alive msg every 1 sec.
  99. * We wait for 6 sec just to be on the safe side.
  100. */
  101. #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ)
  102. #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
  103. #define ENA_MMIO_DISABLE_REG_READ BIT(0)
  104. struct ena_irq {
  105. irq_handler_t handler;
  106. void *data;
  107. int cpu;
  108. u32 vector;
  109. cpumask_t affinity_hint_mask;
  110. char name[ENA_IRQNAME_SIZE];
  111. };
  112. struct ena_napi {
  113. struct napi_struct napi ____cacheline_aligned;
  114. struct ena_ring *tx_ring;
  115. struct ena_ring *rx_ring;
  116. u32 qid;
  117. };
  118. struct ena_tx_buffer {
  119. struct sk_buff *skb;
  120. /* num of ena desc for this specific skb
  121. * (includes data desc and metadata desc)
  122. */
  123. u32 tx_descs;
  124. /* num of buffers used by this skb */
  125. u32 num_of_bufs;
  126. /* Used for detect missing tx packets to limit the number of prints */
  127. u32 print_once;
  128. /* Save the last jiffies to detect missing tx packets
  129. *
  130. * sets to non zero value on ena_start_xmit and set to zero on
  131. * napi and timer_Service_routine.
  132. *
  133. * while this value is not protected by lock,
  134. * a given packet is not expected to be handled by ena_start_xmit
  135. * and by napi/timer_service at the same time.
  136. */
  137. unsigned long last_jiffies;
  138. struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
  139. } ____cacheline_aligned;
  140. struct ena_rx_buffer {
  141. struct sk_buff *skb;
  142. struct page *page;
  143. u32 page_offset;
  144. struct ena_com_buf ena_buf;
  145. } ____cacheline_aligned;
  146. struct ena_stats_tx {
  147. u64 cnt;
  148. u64 bytes;
  149. u64 queue_stop;
  150. u64 prepare_ctx_err;
  151. u64 queue_wakeup;
  152. u64 dma_mapping_err;
  153. u64 linearize;
  154. u64 linearize_failed;
  155. u64 napi_comp;
  156. u64 tx_poll;
  157. u64 doorbells;
  158. u64 bad_req_id;
  159. u64 missed_tx;
  160. };
  161. struct ena_stats_rx {
  162. u64 cnt;
  163. u64 bytes;
  164. u64 refil_partial;
  165. u64 bad_csum;
  166. u64 page_alloc_fail;
  167. u64 skb_alloc_fail;
  168. u64 dma_mapping_err;
  169. u64 bad_desc_num;
  170. u64 rx_copybreak_pkt;
  171. u64 bad_req_id;
  172. u64 empty_rx_ring;
  173. };
  174. struct ena_ring {
  175. union {
  176. /* Holds the empty requests for TX/RX
  177. * out of order completions
  178. */
  179. u16 *free_tx_ids;
  180. u16 *free_rx_ids;
  181. };
  182. union {
  183. struct ena_tx_buffer *tx_buffer_info;
  184. struct ena_rx_buffer *rx_buffer_info;
  185. };
  186. /* cache ptr to avoid using the adapter */
  187. struct device *dev;
  188. struct pci_dev *pdev;
  189. struct napi_struct *napi;
  190. struct net_device *netdev;
  191. struct ena_com_dev *ena_dev;
  192. struct ena_adapter *adapter;
  193. struct ena_com_io_cq *ena_com_io_cq;
  194. struct ena_com_io_sq *ena_com_io_sq;
  195. u16 next_to_use;
  196. u16 next_to_clean;
  197. u16 rx_copybreak;
  198. u16 qid;
  199. u16 mtu;
  200. u16 sgl_size;
  201. /* The maximum header length the device can handle */
  202. u8 tx_max_header_size;
  203. bool first_interrupt;
  204. u16 no_interrupt_event_cnt;
  205. /* cpu for TPH */
  206. int cpu;
  207. /* number of tx/rx_buffer_info's entries */
  208. int ring_size;
  209. enum ena_admin_placement_policy_type tx_mem_queue_type;
  210. struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
  211. u32 smoothed_interval;
  212. u32 per_napi_packets;
  213. u32 per_napi_bytes;
  214. enum ena_intr_moder_level moder_tbl_idx;
  215. struct u64_stats_sync syncp;
  216. union {
  217. struct ena_stats_tx tx_stats;
  218. struct ena_stats_rx rx_stats;
  219. };
  220. int empty_rx_queue;
  221. } ____cacheline_aligned;
  222. struct ena_stats_dev {
  223. u64 tx_timeout;
  224. u64 suspend;
  225. u64 resume;
  226. u64 wd_expired;
  227. u64 interface_up;
  228. u64 interface_down;
  229. u64 admin_q_pause;
  230. u64 rx_drops;
  231. };
  232. enum ena_flags_t {
  233. ENA_FLAG_DEVICE_RUNNING,
  234. ENA_FLAG_DEV_UP,
  235. ENA_FLAG_LINK_UP,
  236. ENA_FLAG_MSIX_ENABLED,
  237. ENA_FLAG_TRIGGER_RESET,
  238. ENA_FLAG_ONGOING_RESET
  239. };
  240. /* adapter specific private data structure */
  241. struct ena_adapter {
  242. struct ena_com_dev *ena_dev;
  243. /* OS defined structs */
  244. struct net_device *netdev;
  245. struct pci_dev *pdev;
  246. /* rx packets that shorter that this len will be copied to the skb
  247. * header
  248. */
  249. u32 rx_copybreak;
  250. u32 max_mtu;
  251. int num_queues;
  252. int msix_vecs;
  253. u32 missing_tx_completion_threshold;
  254. u32 tx_usecs, rx_usecs; /* interrupt moderation */
  255. u32 tx_frames, rx_frames; /* interrupt moderation */
  256. u32 tx_ring_size;
  257. u32 rx_ring_size;
  258. u32 msg_enable;
  259. u16 max_tx_sgl_size;
  260. u16 max_rx_sgl_size;
  261. u8 mac_addr[ETH_ALEN];
  262. unsigned long keep_alive_timeout;
  263. unsigned long missing_tx_completion_to;
  264. char name[ENA_NAME_MAX_LEN];
  265. unsigned long flags;
  266. /* TX */
  267. struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
  268. ____cacheline_aligned_in_smp;
  269. /* RX */
  270. struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
  271. ____cacheline_aligned_in_smp;
  272. struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
  273. struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
  274. /* timer service */
  275. struct work_struct reset_task;
  276. struct timer_list timer_service;
  277. bool wd_state;
  278. bool dev_up_before_reset;
  279. unsigned long last_keep_alive_jiffies;
  280. struct u64_stats_sync syncp;
  281. struct ena_stats_dev dev_stats;
  282. /* last queue index that was checked for uncompleted tx packets */
  283. u32 last_monitored_tx_qid;
  284. enum ena_regs_reset_reason_types reset_reason;
  285. };
  286. void ena_set_ethtool_ops(struct net_device *netdev);
  287. void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
  288. void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
  289. int ena_get_sset_count(struct net_device *netdev, int sset);
  290. /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
  291. * driver passas 0.
  292. * Since the max packet size the ENA handles is ~9kB limit the buffer length to
  293. * 16kB.
  294. */
  295. #if PAGE_SIZE > SZ_16K
  296. #define ENA_PAGE_SIZE SZ_16K
  297. #else
  298. #define ENA_PAGE_SIZE PAGE_SIZE
  299. #endif
  300. #endif /* !(ENA_H) */