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linux-arkmicro
/
u-boot
/
arch
/
sh
/
include
/
asm
/
cpu_sh7720.h

cpu_sh7720.h 5.1 KB
文件历史 原始文件

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * Copyright 2007 (C)
    4. 

  4.  * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
    5. 

  5.  *
    6. 

  6.  * Copyright 2008 (C)
    7. 

  7.  * Mark Jonas <mark.jonas@de.bosch.com>
    8. 

  8.  *
    9. 

  9.  * SH7720 Internal I/O register
    10. 

  10.  */
    11. 

  11. 

  12. #ifndef _ASM_CPU_SH7720_H_
    13. 

  13. #define _ASM_CPU_SH7720_H_
    14. 

  14. 

  15. #define CACHE_OC_NUM_WAYS	4
    16. 

  16. #define CCR_CACHE_INIT		0x0000000B
    17. 

  17. 

  18. /*	EXP	*/
    19. 

  19. #define TRA		0xFFFFFFD0
    20. 

  20. #define EXPEVT		0xFFFFFFD4
    21. 

  21. #define INTEVT		0xFFFFFFD8
    22. 

  22. 

  23. /*	MMU	*/
    24. 

  24. #define MMUCR		0xFFFFFFE0
    25. 

  25. #define PTEH		0xFFFFFFF0
    26. 

  26. #define PTEL		0xFFFFFFF4
    27. 

  27. #define TTB		0xFFFFFFF8
    28. 

  28. 

  29. /*	CACHE	*/
    30. 

  30. #define CCR		0xFFFFFFEC
    31. 

  31. 

  32. /*	INTC	*/
    33. 

  33. #define IPRF		0xA4080000
    34. 

  34. #define IPRG		0xA4080002
    35. 

  35. #define IPRH		0xA4080004
    36. 

  36. #define IPRI		0xA4080006
    37. 

  37. #define IPRJ		0xA4080008
    38. 

  38. #define IRR5		0xA4080020
    39. 

  39. #define IRR6		0xA4080022
    40. 

  40. #define IRR7		0xA4080024
    41. 

  41. #define IRR8		0xA4080026
    42. 

  42. #define IRR9		0xA4080028
    43. 

  43. #define IRR0		0xA4140004
    44. 

  44. #define IRR1		0xA4140006
    45. 

  45. #define IRR2		0xA4140008
    46. 

  46. #define IRR3		0xA414000A
    47. 

  47. #define IRR4		0xA414000C
    48. 

  48. #define ICR1		0xA4140010
    49. 

  49. #define ICR2		0xA4140012
    50. 

  50. #define PINTER		0xA4140014
    51. 

  51. #define IPRC		0xA4140016
    52. 

  52. #define IPRD		0xA4140018
    53. 

  53. #define IPRE		0xA414001A
    54. 

  54. #define ICR0		0xA414FEE0
    55. 

  55. #define IPRA		0xA414FEE2
    56. 

  56. #define IPRB		0xA414FEE4
    57. 

  57. 

  58. /*	BSC	*/
    59. 

  59. #define BSC_BASE	0xA4FD0000
    60. 

  60. #define CMNCR		(BSC_BASE + 0x00)
    61. 

  61. #define CS0BCR		(BSC_BASE + 0x04)
    62. 

  62. #define CS2BCR		(BSC_BASE + 0x08)
    63. 

  63. #define CS3BCR		(BSC_BASE + 0x0C)
    64. 

  64. #define CS4BCR		(BSC_BASE + 0x10)
    65. 

  65. #define CS5ABCR		(BSC_BASE + 0x14)
    66. 

  66. #define CS5BBCR		(BSC_BASE + 0x18)
    67. 

  67. #define CS6ABCR		(BSC_BASE + 0x1C)
    68. 

  68. #define CS6BBCR		(BSC_BASE + 0x20)
    69. 

  69. #define CS0WCR		(BSC_BASE + 0x24)
    70. 

  70. #define CS2WCR		(BSC_BASE + 0x28)
    71. 

  71. #define CS3WCR		(BSC_BASE + 0x2C)
    72. 

  72. #define CS4WCR		(BSC_BASE + 0x30)
    73. 

  73. #define CS5AWCR		(BSC_BASE + 0x34)
    74. 

  74. #define CS5BWCR		(BSC_BASE + 0x38)
    75. 

  75. #define CS6AWCR		(BSC_BASE + 0x3C)
    76. 

  76. #define CS6BWCR		(BSC_BASE + 0x40)
    77. 

  77. #define SDCR		(BSC_BASE + 0x44)
    78. 

  78. #define RTCSR		(BSC_BASE + 0x48)
    79. 

  79. #define RTCNR		(BSC_BASE + 0x4C)
    80. 

  80. #define RTCOR		(BSC_BASE + 0x50)
    81. 

  81. #define SDMR2		(BSC_BASE + 0x4000)
    82. 

  82. #define SDMR3		(BSC_BASE + 0x5000)
    83. 

  83. 

  84. /*	DMAC	*/
    85. 

  85. 

  86. /*	CPG	*/
    87. 

  87. #define UCLKCR		0xA40A0008
    88. 

  88. #define FRQCR		0xA415FF80
    89. 

  89. 

  90. /*	LOW POWER MODE	*/
    91. 

  91. 

  92. /*	TMU	*/
    93. 

  93. #define TMU_BASE	0xA412FE90
    94. 

  94. 

  95. /*	TPU	*/
    96. 

  96. #define TPU_BASE	0xA4480000
    97. 

  97. #define TPU_TSTR	(TPU_BASE + 0x00)
    98. 

  98. #define TPU_TCR0	(TPU_BASE + 0x10)
    99. 

  99. #define TPU_TMDR0	(TPU_BASE + 0x14)
    100. 

  100. #define TPU_TIOR0	(TPU_BASE + 0x18)
    101. 

  101. #define TPU_TIER0	(TPU_BASE + 0x1C)
    102. 

  102. #define TPU_TSR0	(TPU_BASE + 0x20)
    103. 

  103. #define TPU_TCNT0	(TPU_BASE + 0x24)
    104. 

  104. #define TPU_TGRA0	(TPU_BASE + 0x28)
    105. 

  105. #define TPU_TGRB0	(TPU_BASE + 0x2C)
    106. 

  106. #define TPU_TGRC0	(TPU_BASE + 0x30)
    107. 

  107. #define TPU_TGRD0	(TPU_BASE + 0x34)
    108. 

  108. #define TPU_TCR1	(TPU_BASE + 0x50)
    109. 

  109. #define TPU_TMDR1	(TPU_BASE + 0x54)
    110. 

  110. #define TPU_TIOR1	(TPU_BASE + 0x58)
    111. 

  111. #define TPU_TIER1	(TPU_BASE + 0x5C)
    112. 

  112. #define TPU_TSR1	(TPU_BASE + 0x60)
    113. 

  113. #define TPU_TCNT1	(TPU_BASE + 0x64)
    114. 

  114. #define TPU_TGRA1	(TPU_BASE + 0x68)
    115. 

  115. #define TPU_TGRB1	(TPU_BASE + 0x6C)
    116. 

  116. #define TPU_TGRC1	(TPU_BASE + 0x70)
    117. 

  117. #define TPU_TGRD1	(TPU_BASE + 0x74)
    118. 

  118. #define TPU_TCR2	(TPU_BASE + 0x90)
    119. 

  119. #define TPU_TMDR2	(TPU_BASE + 0x94)
    120. 

  120. #define TPU_TIOR2	(TPU_BASE + 0x98)
    121. 

  121. #define TPU_TIER2	(TPU_BASE + 0x9C)
    122. 

  122. #define TPU_TSR2	(TPU_BASE + 0xB0)
    123. 

  123. #define TPU_TCNT2	(TPU_BASE + 0xB4)
    124. 

  124. #define TPU_TGRA2	(TPU_BASE + 0xB8)
    125. 

  125. #define TPU_TGRB2	(TPU_BASE + 0xBC)
    126. 

  126. #define TPU_TGRC2	(TPU_BASE + 0xC0)
    127. 

  127. #define TPU_TGRD2	(TPU_BASE + 0xC4)
    128. 

  128. #define TPU_TCR3	(TPU_BASE + 0xD0)
    129. 

  129. #define TPU_TMDR3	(TPU_BASE + 0xD4)
    130. 

  130. #define TPU_TIOR3	(TPU_BASE + 0xD8)
    131. 

  131. #define TPU_TIER3	(TPU_BASE + 0xDC)
    132. 

  132. #define TPU_TSR3	(TPU_BASE + 0xE0)
    133. 

  133. #define TPU_TCNT3	(TPU_BASE + 0xE4)
    134. 

  134. #define TPU_TGRA3	(TPU_BASE + 0xE8)
    135. 

  135. #define TPU_TGRB3	(TPU_BASE + 0xEC)
    136. 

  136. #define TPU_TGRC3	(TPU_BASE + 0xF0)
    137. 

  137. #define TPU_TGRD3	(TPU_BASE + 0xF4)
    138. 

  138. 

  139. /*	CMT	*/
    140. 

  140. 

  141. /*	SIOF	*/
    142. 

  142. 

  143. /*	SCIF	*/
    144. 

  144. #define SCIF0_BASE	0xA4430000
    145. 

  145. 

  146. /*	SIM	*/
    147. 

  147. 

  148. /*	IrDA	*/
    149. 

  149. 

  150. /*	IIC	*/
    151. 

  151. 

  152. /*	LCDC	*/
    153. 

  153. 

  154. /*	USBF	*/
    155. 

  155. 

  156. /*	MMCIF	*/
    157. 

  157. 

  158. /*	PFC	*/
    159. 

  159. #define PFC_BASE	0xA4050100
    160. 

  160. #define PACR		(PFC_BASE + 0x00)
    161. 

  161. #define PBCR		(PFC_BASE + 0x02)
    162. 

  162. #define PCCR		(PFC_BASE + 0x04)
    163. 

  163. #define PDCR		(PFC_BASE + 0x06)
    164. 

  164. #define PECR		(PFC_BASE + 0x08)
    165. 

  165. #define PFCR		(PFC_BASE + 0x0A)
    166. 

  166. #define PGCR		(PFC_BASE + 0x0C)
    167. 

  167. #define PHCR		(PFC_BASE + 0x0E)
    168. 

  168. #define PJCR		(PFC_BASE + 0x10)
    169. 

  169. #define PKCR		(PFC_BASE + 0x12)
    170. 

  170. #define PLCR		(PFC_BASE + 0x14)
    171. 

  171. #define PMCR		(PFC_BASE + 0x16)
    172. 

  172. #define PPCR		(PFC_BASE + 0x18)
    173. 

  173. #define PRCR		(PFC_BASE + 0x1A)
    174. 

  174. #define PSCR		(PFC_BASE + 0x1C)
    175. 

  175. #define PTCR		(PFC_BASE + 0x1E)
    176. 

  176. #define PUCR		(PFC_BASE + 0x20)
    177. 

  177. #define PVCR		(PFC_BASE + 0x22)
    178. 

  178. #define PSELA		(PFC_BASE + 0x24)
    179. 

  179. #define PSELB		(PFC_BASE + 0x26)
    180. 

  180. #define PSELC		(PFC_BASE + 0x28)
    181. 

  181. #define PSELD		(PFC_BASE + 0x2A)
    182. 

  182. 

  183. /*	I/O Port	*/
    184. 

  184. #define PORT_BASE	0xA4050100
    185. 

  185. #define PADR		(PORT_BASE + 0x40)
    186. 

  186. #define PBDR		(PORT_BASE + 0x42)
    187. 

  187. #define PCDR		(PORT_BASE + 0x44)
    188. 

  188. #define PDDR		(PORT_BASE + 0x46)
    189. 

  189. #define PEDR		(PORT_BASE + 0x48)
    190. 

  190. #define PFDR		(PORT_BASE + 0x4A)
    191. 

  191. #define PGDR		(PORT_BASE + 0x4C)
    192. 

  192. #define PHDR		(PORT_BASE + 0x4E)
    193. 

  193. #define PJDR		(PORT_BASE + 0x50)
    194. 

  194. #define PKDR		(PORT_BASE + 0x52)
    195. 

  195. #define PLDR		(PORT_BASE + 0x54)
    196. 

  196. #define PMDR		(PORT_BASE + 0x56)
    197. 

  197. #define PPDR		(PORT_BASE + 0x58)
    198. 

  198. #define PRDR		(PORT_BASE + 0x5A)
    199. 

  199. #define PSDR		(PORT_BASE + 0x5C)
    200. 

  200. #define PTDR		(PORT_BASE + 0x5E)
    201. 

  201. #define PUDR		(PORT_BASE + 0x60)
    202. 

  202. #define PVDR		(PORT_BASE + 0x62)
    203. 

  203. 

  204. /*	H-UDI	*/
    205. 

  205. 

  206. #endif /* _ASM_CPU_SH7720_H_ */
    207.