ehci.c 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
  4. *
  5. * Original Author Guenter Gebhardt
  6. * Copyright (C) 2006 Micronas GmbH
  7. */
  8. #include <common.h>
  9. #include "vct.h"
  10. int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
  11. {
  12. int retval;
  13. u32 val;
  14. u32 addr;
  15. dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
  16. dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
  17. dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
  18. dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
  19. dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
  20. /* Wait until (DCGU_USBPHY_STAT == 7) */
  21. addr = DCGU_USBPHY_STAT(DCGU_BASE);
  22. val = reg_read(addr);
  23. while (val != 7)
  24. val = reg_read(addr);
  25. dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
  26. dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
  27. retval = scc_reset(SCC_USB_RW, 0);
  28. if (retval) {
  29. printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
  30. return retval;
  31. } else {
  32. retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
  33. if (retval) {
  34. printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
  35. retval);
  36. return retval;
  37. }
  38. }
  39. if (!retval) {
  40. /*
  41. * For the AGU bypass, where the SCC client provides full
  42. * physical address
  43. */
  44. scc_set_usb_address_generation_mode(1);
  45. scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
  46. USE_NO_FH, DMA_READ, 0);
  47. scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
  48. USE_NO_FH, DMA_WRITE, 0);
  49. scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
  50. USE_NO_FH, DMA_WRITE, 0);
  51. scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
  52. USE_NO_FH, DMA_READ, 0);
  53. /* Enable memory interface */
  54. scc_enable(SCC_USB_RW, 1);
  55. /* Start (start_cmd=0) DMAs */
  56. scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
  57. scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
  58. } else {
  59. printf("Cannot configure USB memory channel.\n");
  60. printf("USB can not access RAM. SCC configuration failed.\n");
  61. return retval;
  62. }
  63. /* Wait a short while */
  64. udelay(300000);
  65. reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
  66. /* Set EHCI structures and DATA in RAM */
  67. reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
  68. /* Set USBMODE to bigendian and set host mode */
  69. reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
  70. /*
  71. * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
  72. * 512 byte USB transfers on the bulk pipe to work properly.
  73. * Set USBH_BURSTSIZE to 0x00001c1c
  74. */
  75. reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
  76. /* Insert access register addresses */
  77. *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
  78. *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
  79. return 0;
  80. }