armada-37xx.dtsi 9.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree Include file for Marvell Armada 37xx family of SoCs.
  4. *
  5. * Copyright (C) 2016 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. *
  9. */
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. / {
  12. model = "Marvell Armada 37xx SoC";
  13. compatible = "marvell,armada3700";
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. aliases {
  18. serial0 = &uart0;
  19. serial1 = &uart1;
  20. };
  21. reserved-memory {
  22. #address-cells = <2>;
  23. #size-cells = <2>;
  24. ranges;
  25. /*
  26. * The PSCI firmware region depicted below is the default one
  27. * and should be updated by the bootloader.
  28. */
  29. psci-area@4000000 {
  30. reg = <0 0x4000000 0 0x200000>;
  31. no-map;
  32. };
  33. };
  34. cpus {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. cpu@0 {
  38. device_type = "cpu";
  39. compatible = "arm,cortex-a53", "arm,armv8";
  40. reg = <0>;
  41. clocks = <&nb_periph_clk 16>;
  42. enable-method = "psci";
  43. };
  44. };
  45. psci {
  46. compatible = "arm,psci-0.2";
  47. method = "smc";
  48. };
  49. timer {
  50. compatible = "arm,armv8-timer";
  51. interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
  52. <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
  53. <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
  54. <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
  55. };
  56. pmu {
  57. compatible = "arm,armv8-pmuv3";
  58. interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  59. };
  60. soc {
  61. compatible = "simple-bus";
  62. #address-cells = <2>;
  63. #size-cells = <2>;
  64. ranges;
  65. internal-regs@d0000000 {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "simple-bus";
  69. /* 32M internal register @ 0xd000_0000 */
  70. ranges = <0x0 0x0 0xd0000000 0x2000000>;
  71. spi0: spi@10600 {
  72. compatible = "marvell,armada-3700-spi";
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. reg = <0x10600 0xA00>;
  76. clocks = <&nb_periph_clk 7>;
  77. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  78. num-cs = <4>;
  79. status = "disabled";
  80. };
  81. i2c0: i2c@11000 {
  82. compatible = "marvell,armada-3700-i2c";
  83. reg = <0x11000 0x24>;
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. clocks = <&nb_periph_clk 10>;
  87. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  88. mrvl,i2c-fast-mode;
  89. status = "disabled";
  90. };
  91. i2c1: i2c@11080 {
  92. compatible = "marvell,armada-3700-i2c";
  93. reg = <0x11080 0x24>;
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. clocks = <&nb_periph_clk 9>;
  97. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  98. mrvl,i2c-fast-mode;
  99. status = "disabled";
  100. };
  101. avs: avs@11500 {
  102. compatible = "marvell,armada-3700-avs",
  103. "syscon";
  104. reg = <0x11500 0x40>;
  105. };
  106. uart0: serial@12000 {
  107. compatible = "marvell,armada-3700-uart";
  108. reg = <0x12000 0x200>;
  109. clocks = <&xtalclk>;
  110. interrupts =
  111. <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  112. <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  113. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  114. interrupt-names = "uart-sum", "uart-tx", "uart-rx";
  115. status = "disabled";
  116. };
  117. uart1: serial@12200 {
  118. compatible = "marvell,armada-3700-uart-ext";
  119. reg = <0x12200 0x30>;
  120. clocks = <&xtalclk>;
  121. interrupts =
  122. <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
  123. <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
  124. interrupt-names = "uart-tx", "uart-rx";
  125. status = "disabled";
  126. };
  127. nb_periph_clk: nb-periph-clk@13000 {
  128. compatible = "marvell,armada-3700-periph-clock-nb",
  129. "syscon";
  130. reg = <0x13000 0x100>;
  131. clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
  132. <&tbg 3>, <&xtalclk>;
  133. #clock-cells = <1>;
  134. };
  135. sb_periph_clk: sb-periph-clk@18000 {
  136. compatible = "marvell,armada-3700-periph-clock-sb";
  137. reg = <0x18000 0x100>;
  138. clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
  139. <&tbg 3>, <&xtalclk>;
  140. #clock-cells = <1>;
  141. };
  142. tbg: tbg@13200 {
  143. compatible = "marvell,armada-3700-tbg-clock";
  144. reg = <0x13200 0x100>;
  145. clocks = <&xtalclk>;
  146. #clock-cells = <1>;
  147. };
  148. pinctrl_nb: pinctrl@13800 {
  149. compatible = "marvell,armada3710-nb-pinctrl",
  150. "syscon", "simple-mfd";
  151. reg = <0x13800 0x100>, <0x13C00 0x20>;
  152. /* MPP1[19:0] */
  153. gpionb: gpio {
  154. #gpio-cells = <2>;
  155. gpio-ranges = <&pinctrl_nb 0 0 36>;
  156. gpio-controller;
  157. interrupt-controller;
  158. #interrupt-cells = <2>;
  159. interrupts =
  160. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  161. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  162. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  163. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  164. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  165. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  166. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  167. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  168. <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  169. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  170. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
  171. <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  172. };
  173. xtalclk: xtal-clk {
  174. compatible = "marvell,armada-3700-xtal-clock";
  175. clock-output-names = "xtal";
  176. #clock-cells = <0>;
  177. };
  178. spi_quad_pins: spi-quad-pins {
  179. groups = "spi_quad";
  180. function = "spi";
  181. };
  182. i2c1_pins: i2c1-pins {
  183. groups = "i2c1";
  184. function = "i2c";
  185. };
  186. i2c2_pins: i2c2-pins {
  187. groups = "i2c2";
  188. function = "i2c";
  189. };
  190. uart1_pins: uart1-pins {
  191. groups = "uart1";
  192. function = "uart";
  193. };
  194. uart2_pins: uart2-pins {
  195. groups = "uart2";
  196. function = "uart";
  197. };
  198. };
  199. nb_pm: syscon@14000 {
  200. compatible = "marvell,armada-3700-nb-pm",
  201. "syscon";
  202. reg = <0x14000 0x60>;
  203. };
  204. pinctrl_sb: pinctrl@18800 {
  205. compatible = "marvell,armada3710-sb-pinctrl",
  206. "syscon", "simple-mfd";
  207. reg = <0x18800 0x100>, <0x18C00 0x20>;
  208. /* MPP2[23:0] */
  209. gpiosb: gpio {
  210. #gpio-cells = <2>;
  211. gpio-ranges = <&pinctrl_sb 0 0 30>;
  212. gpio-controller;
  213. interrupt-controller;
  214. #interrupt-cells = <2>;
  215. interrupts =
  216. <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  217. <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
  218. <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
  219. <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
  220. <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
  221. };
  222. rgmii_pins: mii-pins {
  223. groups = "rgmii";
  224. function = "mii";
  225. };
  226. };
  227. eth0: ethernet@30000 {
  228. compatible = "marvell,armada-3700-neta";
  229. reg = <0x30000 0x4000>;
  230. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  231. clocks = <&sb_periph_clk 8>;
  232. status = "disabled";
  233. };
  234. mdio: mdio@32004 {
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. compatible = "marvell,orion-mdio";
  238. reg = <0x32004 0x4>;
  239. };
  240. eth1: ethernet@40000 {
  241. compatible = "marvell,armada-3700-neta";
  242. reg = <0x40000 0x4000>;
  243. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  244. clocks = <&sb_periph_clk 7>;
  245. status = "disabled";
  246. };
  247. usb3: usb@58000 {
  248. compatible = "marvell,armada3700-xhci",
  249. "generic-xhci";
  250. reg = <0x58000 0x4000>;
  251. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  252. clocks = <&sb_periph_clk 12>;
  253. status = "disabled";
  254. };
  255. usb2: usb@5e000 {
  256. compatible = "marvell,armada-3700-ehci";
  257. reg = <0x5e000 0x2000>;
  258. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  259. status = "disabled";
  260. };
  261. xor@60900 {
  262. compatible = "marvell,armada-3700-xor";
  263. reg = <0x60900 0x100>,
  264. <0x60b00 0x100>;
  265. xor10 {
  266. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  267. };
  268. xor11 {
  269. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  270. };
  271. };
  272. crypto: crypto@90000 {
  273. compatible = "inside-secure,safexcel-eip97ies";
  274. reg = <0x90000 0x20000>;
  275. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  276. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  277. <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  278. <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  279. <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  280. <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  281. interrupt-names = "mem", "ring0", "ring1",
  282. "ring2", "ring3", "eip";
  283. clocks = <&nb_periph_clk 15>;
  284. };
  285. sdhci1: sdhci@d0000 {
  286. compatible = "marvell,armada-3700-sdhci",
  287. "marvell,sdhci-xenon";
  288. reg = <0xd0000 0x300>,
  289. <0x1e808 0x4>;
  290. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  291. clocks = <&nb_periph_clk 0>;
  292. clock-names = "core";
  293. status = "disabled";
  294. };
  295. sdhci0: sdhci@d8000 {
  296. compatible = "marvell,armada-3700-sdhci",
  297. "marvell,sdhci-xenon";
  298. reg = <0xd8000 0x300>,
  299. <0x17808 0x4>;
  300. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  301. clocks = <&nb_periph_clk 0>;
  302. clock-names = "core";
  303. status = "disabled";
  304. };
  305. sata: sata@e0000 {
  306. compatible = "marvell,armada-3700-ahci";
  307. reg = <0xe0000 0x2000>;
  308. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  309. status = "disabled";
  310. };
  311. gic: interrupt-controller@1d00000 {
  312. compatible = "arm,gic-v3";
  313. #interrupt-cells = <3>;
  314. interrupt-controller;
  315. reg = <0x1d00000 0x10000>, /* GICD */
  316. <0x1d40000 0x40000>, /* GICR */
  317. <0x1d80000 0x2000>, /* GICC */
  318. <0x1d90000 0x2000>, /* GICH */
  319. <0x1da0000 0x20000>; /* GICV */
  320. interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  321. };
  322. };
  323. pcie0: pcie@d0070000 {
  324. compatible = "marvell,armada-3700-pcie";
  325. device_type = "pci";
  326. status = "disabled";
  327. reg = <0 0xd0070000 0 0x20000>;
  328. #address-cells = <3>;
  329. #size-cells = <2>;
  330. bus-range = <0x00 0xff>;
  331. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  332. #interrupt-cells = <1>;
  333. msi-parent = <&pcie0>;
  334. msi-controller;
  335. ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
  336. 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
  337. interrupt-map-mask = <0 0 0 7>;
  338. interrupt-map = <0 0 0 1 &pcie_intc 0>,
  339. <0 0 0 2 &pcie_intc 1>,
  340. <0 0 0 3 &pcie_intc 2>,
  341. <0 0 0 4 &pcie_intc 3>;
  342. pcie_intc: interrupt-controller {
  343. interrupt-controller;
  344. #interrupt-cells = <1>;
  345. };
  346. };
  347. };
  348. };