zynqmp-zcu111-revA.dts 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP ZCU111
  4. *
  5. * (C) Copyright 2017 - 2018, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk.dtsi"
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "ZynqMP ZCU111 RevA";
  16. compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
  17. aliases {
  18. ethernet0 = &gem3;
  19. i2c0 = &i2c0;
  20. i2c1 = &i2c1;
  21. mmc0 = &sdhci1;
  22. rtc0 = &rtc;
  23. serial0 = &uart0;
  24. serial1 = &dcc;
  25. };
  26. chosen {
  27. bootargs = "earlycon";
  28. stdout-path = "serial0:115200n8";
  29. };
  30. memory@0 {
  31. device_type = "memory";
  32. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  33. /* Another 4GB connected to PL */
  34. };
  35. gpio-keys {
  36. compatible = "gpio-keys";
  37. autorepeat;
  38. sw19 {
  39. label = "sw19";
  40. gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  41. linux,code = <KEY_DOWN>;
  42. gpio-key,wakeup;
  43. autorepeat;
  44. };
  45. };
  46. leds {
  47. compatible = "gpio-leds";
  48. heartbeat-led {
  49. label = "heartbeat";
  50. gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  51. linux,default-trigger = "heartbeat";
  52. };
  53. };
  54. };
  55. &dcc {
  56. status = "okay";
  57. };
  58. &fpd_dma_chan1 {
  59. status = "okay";
  60. };
  61. &fpd_dma_chan2 {
  62. status = "okay";
  63. };
  64. &fpd_dma_chan3 {
  65. status = "okay";
  66. };
  67. &fpd_dma_chan4 {
  68. status = "okay";
  69. };
  70. &fpd_dma_chan5 {
  71. status = "okay";
  72. };
  73. &fpd_dma_chan6 {
  74. status = "okay";
  75. };
  76. &fpd_dma_chan7 {
  77. status = "okay";
  78. };
  79. &fpd_dma_chan8 {
  80. status = "okay";
  81. };
  82. &gem3 {
  83. status = "okay";
  84. phy-handle = <&phy0>;
  85. phy-mode = "rgmii-id";
  86. phy0: phy@c {
  87. reg = <0xc>;
  88. ti,rx-internal-delay = <0x8>;
  89. ti,tx-internal-delay = <0xa>;
  90. ti,fifo-depth = <0x1>;
  91. };
  92. };
  93. &gpio {
  94. status = "okay";
  95. };
  96. &i2c0 {
  97. status = "okay";
  98. clock-frequency = <400000>;
  99. tca6416_u22: gpio@20 {
  100. compatible = "ti,tca6416";
  101. reg = <0x20>;
  102. gpio-controller; /* interrupt not connected */
  103. #gpio-cells = <2>;
  104. /*
  105. * IRQ not connected
  106. * Lines:
  107. * 0 - MAX6643_OT_B
  108. * 1 - MAX6643_FANFAIL_B
  109. * 2 - MIO26_PMU_INPUT_LS
  110. * 4 - SFP_SI5382_INT_ALM
  111. * 5 - IIC_MUX_RESET_B
  112. * 6 - GEM3_EXP_RESET_B
  113. * 10 - FMCP_HSPC_PRSNT_M2C_B
  114. * 11 - CLK_SPI_MUX_SEL0
  115. * 12 - CLK_SPI_MUX_SEL1
  116. * 16 - IRPS5401_ALERT_B
  117. * 17 - INA226_PMBUS_ALERT
  118. * 3, 7, 13-15 - not connected
  119. */
  120. };
  121. i2c-mux@75 { /* u23 */
  122. compatible = "nxp,pca9544";
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. reg = <0x75>;
  126. i2c@0 {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. reg = <0>;
  130. /* PS_PMBUS */
  131. /* PMBUS_ALERT done via pca9544 */
  132. ina226@40 { /* u67 */
  133. compatible = "ti,ina226";
  134. reg = <0x40>;
  135. shunt-resistor = <2000>;
  136. };
  137. ina226@41 { /* u59 */
  138. compatible = "ti,ina226";
  139. reg = <0x41>;
  140. shunt-resistor = <5000>;
  141. };
  142. ina226@42 { /* u61 */
  143. compatible = "ti,ina226";
  144. reg = <0x42>;
  145. shunt-resistor = <5000>;
  146. };
  147. ina226@43 { /* u60 */
  148. compatible = "ti,ina226";
  149. reg = <0x43>;
  150. shunt-resistor = <5000>;
  151. };
  152. ina226@45 { /* u64 */
  153. compatible = "ti,ina226";
  154. reg = <0x45>;
  155. shunt-resistor = <5000>;
  156. };
  157. ina226@46 { /* u69 */
  158. compatible = "ti,ina226";
  159. reg = <0x46>;
  160. shunt-resistor = <2000>;
  161. };
  162. ina226@47 { /* u66 */
  163. compatible = "ti,ina226";
  164. reg = <0x47>;
  165. shunt-resistor = <5000>;
  166. };
  167. ina226@48 { /* u65 */
  168. compatible = "ti,ina226";
  169. reg = <0x48>;
  170. shunt-resistor = <5000>;
  171. };
  172. ina226@49 { /* u63 */
  173. compatible = "ti,ina226";
  174. reg = <0x49>;
  175. shunt-resistor = <5000>;
  176. };
  177. ina226@4a { /* u3 */
  178. compatible = "ti,ina226";
  179. reg = <0x4a>;
  180. shunt-resistor = <5000>;
  181. };
  182. ina226@4b { /* u71 */
  183. compatible = "ti,ina226";
  184. reg = <0x4b>;
  185. shunt-resistor = <5000>;
  186. };
  187. ina226@4c { /* u77 */
  188. compatible = "ti,ina226";
  189. reg = <0x4c>;
  190. shunt-resistor = <5000>;
  191. };
  192. ina226@4d { /* u73 */
  193. compatible = "ti,ina226";
  194. reg = <0x4d>;
  195. shunt-resistor = <5000>;
  196. };
  197. ina226@4e { /* u79 */
  198. compatible = "ti,ina226";
  199. reg = <0x4e>;
  200. shunt-resistor = <5000>;
  201. };
  202. };
  203. i2c@1 {
  204. #address-cells = <1>;
  205. #size-cells = <0>;
  206. reg = <1>;
  207. /* NC */
  208. };
  209. i2c@2 {
  210. #address-cells = <1>;
  211. #size-cells = <0>;
  212. reg = <2>;
  213. irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
  214. reg = <0x43>;
  215. };
  216. irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
  217. reg = <0x44>;
  218. };
  219. irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
  220. reg = <0x45>;
  221. };
  222. /* u68 IR38064 +0 */
  223. /* u70 IR38060 +1 */
  224. /* u74 IR38060 +2 */
  225. /* u75 IR38060 +6 */
  226. /* J19 header too */
  227. };
  228. i2c@3 {
  229. #address-cells = <1>;
  230. #size-cells = <0>;
  231. reg = <3>;
  232. /* SYSMON */
  233. };
  234. };
  235. };
  236. &i2c1 {
  237. status = "okay";
  238. clock-frequency = <400000>;
  239. i2c-mux@74 { /* u26 */
  240. compatible = "nxp,pca9548";
  241. #address-cells = <1>;
  242. #size-cells = <0>;
  243. reg = <0x74>;
  244. i2c@0 {
  245. #address-cells = <1>;
  246. #size-cells = <0>;
  247. reg = <0>;
  248. /*
  249. * IIC_EEPROM 1kB memory which uses 256B blocks
  250. * where every block has different address.
  251. * 0 - 256B address 0x54
  252. * 256B - 512B address 0x55
  253. * 512B - 768B address 0x56
  254. * 768B - 1024B address 0x57
  255. */
  256. eeprom: eeprom@54 { /* u88 */
  257. compatible = "atmel,24c08";
  258. reg = <0x54>;
  259. };
  260. };
  261. i2c@1 {
  262. #address-cells = <1>;
  263. #size-cells = <0>;
  264. reg = <1>;
  265. si5341: clock-generator@36 { /* SI5341 - u46 */
  266. reg = <0x36>;
  267. };
  268. };
  269. i2c@2 {
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. reg = <2>;
  273. si570_1: clock-generator@5d { /* USER SI570 - u47 */
  274. #clock-cells = <0>;
  275. compatible = "silabs,si570";
  276. reg = <0x5d>;
  277. temperature-stability = <50>;
  278. factory-fout = <300000000>;
  279. clock-frequency = <300000000>;
  280. };
  281. };
  282. i2c@3 {
  283. #address-cells = <1>;
  284. #size-cells = <0>;
  285. reg = <3>;
  286. si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
  287. #clock-cells = <0>;
  288. compatible = "silabs,si570";
  289. reg = <0x5d>;
  290. temperature-stability = <50>;
  291. factory-fout = <156250000>;
  292. clock-frequency = <148500000>;
  293. };
  294. };
  295. i2c@4 {
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. reg = <4>;
  299. si5328: clock-generator@69 { /* SI5328 - u48 */
  300. reg = <0x69>;
  301. };
  302. };
  303. i2c@5 {
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. reg = <5>;
  307. sc18is603@2f { /* sc18is602 - u93 */
  308. compatible = "nxp,sc18is603";
  309. reg = <0x2f>;
  310. /* 4 gpios for CS not handled by driver */
  311. /*
  312. * USB2ANY cable or
  313. * LMK04208 - u90 or
  314. * LMX2594 - u102 or
  315. * LMX2594 - u103 or
  316. * LMX2594 - u104
  317. */
  318. };
  319. };
  320. i2c@6 {
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. reg = <6>;
  324. /* FMC connector */
  325. };
  326. /* 7 NC */
  327. };
  328. i2c-mux@75 {
  329. compatible = "nxp,pca9548"; /* u27 */
  330. #address-cells = <1>;
  331. #size-cells = <0>;
  332. reg = <0x75>;
  333. i2c@0 {
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. reg = <0>;
  337. /* FMCP_HSPC_IIC */
  338. };
  339. i2c@1 {
  340. #address-cells = <1>;
  341. #size-cells = <0>;
  342. reg = <1>;
  343. /* NC */
  344. };
  345. i2c@2 {
  346. #address-cells = <1>;
  347. #size-cells = <0>;
  348. reg = <2>;
  349. /* SYSMON */
  350. };
  351. i2c@3 {
  352. #address-cells = <1>;
  353. #size-cells = <0>;
  354. reg = <3>;
  355. /* DDR4 SODIMM */
  356. };
  357. i2c@4 {
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. reg = <4>;
  361. /* SFP3 */
  362. };
  363. i2c@5 {
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. reg = <5>;
  367. /* SFP2 */
  368. };
  369. i2c@6 {
  370. #address-cells = <1>;
  371. #size-cells = <0>;
  372. reg = <6>;
  373. /* SFP1 */
  374. };
  375. i2c@7 {
  376. #address-cells = <1>;
  377. #size-cells = <0>;
  378. reg = <7>;
  379. /* SFP0 */
  380. };
  381. };
  382. };
  383. &rtc {
  384. status = "okay";
  385. };
  386. &sata {
  387. status = "okay";
  388. /* SATA OOB timing settings */
  389. ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  390. ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  391. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  392. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  393. ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  394. ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  395. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  396. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  397. };
  398. /* SD1 with level shifter */
  399. &sdhci1 {
  400. status = "okay";
  401. no-1-8-v;
  402. };
  403. &uart0 {
  404. status = "okay";
  405. };
  406. /* ULPI SMSC USB3320 */
  407. &usb0 {
  408. status = "okay";
  409. };