cpu.c 2.1 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/system.h>
  8. #include <asm/armv8/mmu.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/mc_me_regs.h>
  11. #include "cpu.h"
  12. u32 cpu_mask(void)
  13. {
  14. return readl(MC_ME_CS);
  15. }
  16. #ifndef CONFIG_SYS_DCACHE_OFF
  17. #define S32V234_IRAM_BASE 0x3e800000UL
  18. #define S32V234_IRAM_SIZE 0x800000UL
  19. #define S32V234_DRAM_BASE1 0x80000000UL
  20. #define S32V234_DRAM_SIZE1 0x40000000UL
  21. #define S32V234_DRAM_BASE2 0xC0000000UL
  22. #define S32V234_DRAM_SIZE2 0x20000000UL
  23. #define S32V234_PERIPH_BASE 0x40000000UL
  24. #define S32V234_PERIPH_SIZE 0x40000000UL
  25. static struct mm_region s32v234_mem_map[] = {
  26. {
  27. .virt = S32V234_IRAM_BASE,
  28. .phys = S32V234_IRAM_BASE,
  29. .size = S32V234_IRAM_SIZE,
  30. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  31. PTE_BLOCK_OUTER_SHARE
  32. }, {
  33. .virt = S32V234_DRAM_BASE1,
  34. .phys = S32V234_DRAM_BASE1,
  35. .size = S32V234_DRAM_SIZE1,
  36. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  37. PTE_BLOCK_OUTER_SHARE
  38. }, {
  39. .virt = S32V234_PERIPH_BASE,
  40. .phys = S32V234_PERIPH_BASE,
  41. .size = S32V234_PERIPH_SIZE,
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43. PTE_BLOCK_NON_SHARE
  44. /* TODO: Do we need these? */
  45. /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
  46. }, {
  47. .virt = S32V234_DRAM_BASE2,
  48. .phys = S32V234_DRAM_BASE2,
  49. .size = S32V234_DRAM_SIZE2,
  50. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  51. PTE_BLOCK_OUTER_SHARE
  52. }, {
  53. /* List terminator */
  54. 0,
  55. }
  56. };
  57. struct mm_region *mem_map = s32v234_mem_map;
  58. #endif
  59. /*
  60. * Return the number of cores on this SOC.
  61. */
  62. int cpu_numcores(void)
  63. {
  64. int numcores;
  65. u32 mask;
  66. mask = cpu_mask();
  67. numcores = hweight32(cpu_mask());
  68. /* Verify if M4 is deactivated */
  69. if (mask & 0x1)
  70. numcores--;
  71. return numcores;
  72. }
  73. #if defined(CONFIG_ARCH_EARLY_INIT_R)
  74. int arch_early_init_r(void)
  75. {
  76. int rv;
  77. asm volatile ("dsb sy");
  78. rv = fsl_s32v234_wake_seconday_cores();
  79. if (rv)
  80. printf("Did not wake secondary cores\n");
  81. asm volatile ("sev");
  82. return 0;
  83. }
  84. #endif /* CONFIG_ARCH_EARLY_INIT_R */