timer.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/at91_pit.h>
  11. #include <asm/arch/clk.h>
  12. #include <div64.h>
  13. #if !defined(CONFIG_AT91FAMILY)
  14. # error You need to define CONFIG_AT91FAMILY in your board config!
  15. #endif
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /*
  18. * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  19. * setting the 20 bit counter period to its maximum (0xfffff).
  20. * (See the relevant data sheets to understand that this really works)
  21. *
  22. * We do also mimic the typical powerpc way of incrementing
  23. * two 32 bit registers called tbl and tbu.
  24. *
  25. * Those registers increment at 1/16 the main clock rate.
  26. */
  27. #define TIMER_LOAD_VAL 0xfffff
  28. /*
  29. * Use the PITC in full 32 bit incrementing mode
  30. */
  31. int timer_init(void)
  32. {
  33. at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
  34. at91_periph_clk_enable(ATMEL_ID_SYS);
  35. /* Enable PITC */
  36. writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  37. gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
  38. return 0;
  39. }
  40. /*
  41. * Return the number of timer ticks per second.
  42. */
  43. ulong get_tbclk(void)
  44. {
  45. return gd->arch.timer_rate_hz;
  46. }