cache.h 438 B

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
  4. * Scott McNutt <smcnutt@psyent.com>
  5. */
  6. #ifndef __ASM_NIOS2_CACHE_H_
  7. #define __ASM_NIOS2_CACHE_H_
  8. /*
  9. * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
  10. * 16, and 32 bytes. We default to the largest of these values for
  11. * alignment of DMA buffers.
  12. */
  13. #define ARCH_DMA_MINALIGN 32
  14. #endif /* __ASM_NIOS2_CACHE_H_ */