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linux-arkmicro
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u-boot
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arch
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include
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asm
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cpu_sh7785.h

cpu_sh7785.h 3.5 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. #ifndef	_ASM_CPU_SH7785_H_
    3. 

  3. #define	_ASM_CPU_SH7785_H_
    4. 

  4. 

  5. /*
    6. 

  6.  * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
    7. 

  7.  * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
    8. 

  8.  * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
    9. 

  9.  */
    10. 

  10. 

  11. #define	CACHE_OC_NUM_WAYS	1
    12. 

  12. #define	CCR_CACHE_INIT		0x0000090b
    13. 

  13. 

  14. /*	Exceptions	*/
    15. 

  15. #define	TRA		0xFF000020
    16. 

  16. #define	EXPEVT	0xFF000024
    17. 

  17. #define	INTEVT	0xFF000028
    18. 

  18. 

  19. /* Cache Controller */
    20. 

  20. #define	CCR	0xFF00001C
    21. 

  21. #define	QACR0	0xFF000038
    22. 

  22. #define	QACR1	0xFF00003C
    23. 

  23. #define	RAMCR	0xFF000074
    24. 

  24. 

  25. /* Watchdog Timer and Reset */
    26. 

  26. #define	WTCNT	WDTCNT
    27. 

  27. #define	WDTST	0xFFCC0000
    28. 

  28. #define	WDTCSR	0xFFCC0004
    29. 

  29. #define	WDTBST	0xFFCC0008
    30. 

  30. #define	WDTCNT	0xFFCC0010
    31. 

  31. #define	WDTBCNT	0xFFCC0018
    32. 

  32. 

  33. /* Timer Unit */
    34. 

  34. #define TMU_BASE	0xFFD80000
    35. 

  35. 

  36. /* Serial Communication	Interface with FIFO */
    37. 

  37. #define	SCIF1_BASE	0xffeb0000
    38. 

  38. 

  39. /* LBSC */
    40. 

  40. #define MMSELR		0xfc400020
    41. 

  41. #define LBSC_BASE	0xff800000
    42. 

  42. #define BCR		(LBSC_BASE + 0x1000)
    43. 

  43. #define CS0BCR		(LBSC_BASE + 0x2000)
    44. 

  44. #define CS1BCR		(LBSC_BASE + 0x2010)
    45. 

  45. #define CS2BCR		(LBSC_BASE + 0x2020)
    46. 

  46. #define CS3BCR		(LBSC_BASE + 0x2030)
    47. 

  47. #define CS4BCR		(LBSC_BASE + 0x2040)
    48. 

  48. #define CS5BCR		(LBSC_BASE + 0x2050)
    49. 

  49. #define CS6BCR		(LBSC_BASE + 0x2060)
    50. 

  50. #define CS0WCR		(LBSC_BASE + 0x2008)
    51. 

  51. #define CS1WCR		(LBSC_BASE + 0x2018)
    52. 

  52. #define CS2WCR		(LBSC_BASE + 0x2028)
    53. 

  53. #define CS3WCR		(LBSC_BASE + 0x2038)
    54. 

  54. #define CS4WCR		(LBSC_BASE + 0x2048)
    55. 

  55. #define CS5WCR		(LBSC_BASE + 0x2058)
    56. 

  56. #define CS6WCR		(LBSC_BASE + 0x2068)
    57. 

  57. #define CS5PCR		(LBSC_BASE + 0x2070)
    58. 

  58. #define CS6PCR		(LBSC_BASE + 0x2080)
    59. 

  59. 

  60. /* PCI	Controller */
    61. 

  61. #define	SH7780_PCIECR		0xFE000008
    62. 

  62. #define	SH7780_PCIVID		0xFE040000
    63. 

  63. #define	SH7780_PCIDID		0xFE040002
    64. 

  64. #define	SH7780_PCICMD		0xFE040004
    65. 

  65. #define	SH7780_PCISTATUS	0xFE040006
    66. 

  66. #define	SH7780_PCIRID		0xFE040008
    67. 

  67. #define	SH7780_PCIPIF		0xFE040009
    68. 

  68. #define	SH7780_PCISUB		0xFE04000A
    69. 

  69. #define	SH7780_PCIBCC		0xFE04000B
    70. 

  70. #define	SH7780_PCICLS		0xFE04000C
    71. 

  71. #define	SH7780_PCILTM		0xFE04000D
    72. 

  72. #define	SH7780_PCIHDR		0xFE04000E
    73. 

  73. #define	SH7780_PCIBIST		0xFE04000F
    74. 

  74. #define	SH7780_PCIIBAR		0xFE040010
    75. 

  75. #define	SH7780_PCIMBAR0		0xFE040014
    76. 

  76. #define	SH7780_PCIMBAR1		0xFE040018
    77. 

  77. #define	SH7780_PCISVID		0xFE04002C
    78. 

  78. #define	SH7780_PCISID		0xFE04002E
    79. 

  79. #define	SH7780_PCICP		0xFE040034
    80. 

  80. #define	SH7780_PCIINTLINE	0xFE04003C
    81. 

  81. #define	SH7780_PCIINTPIN	0xFE04003D
    82. 

  82. #define	SH7780_PCIMINGNT	0xFE04003E
    83. 

  83. #define	SH7780_PCIMAXLAT	0xFE04003F
    84. 

  84. #define	SH7780_PCICID		0xFE040040
    85. 

  85. #define	SH7780_PCINIP		0xFE040041
    86. 

  86. #define	SH7780_PCIPMC		0xFE040042
    87. 

  87. #define	SH7780_PCIPMCSR		0xFE040044
    88. 

  88. #define	SH7780_PCIPMCSRBSE	0xFE040046
    89. 

  89. #define	SH7780_PCI_CDD		0xFE040047
    90. 

  90. #define	SH7780_PCICR		0xFE040100
    91. 

  91. #define	SH7780_PCILSR0		0xFE040104
    92. 

  92. #define	SH7780_PCILSR1		0xFE040108
    93. 

  93. #define	SH7780_PCILAR0		0xFE04010C
    94. 

  94. #define	SH7780_PCILAR1		0xFE040110
    95. 

  95. #define	SH7780_PCIIR		0xFE040114
    96. 

  96. #define	SH7780_PCIIMR		0xFE040118
    97. 

  97. #define	SH7780_PCIAIR		0xFE04011C
    98. 

  98. #define	SH7780_PCICIR		0xFE040120
    99. 

  99. #define	SH7780_PCIAINT		0xFE040130
    100. 

  100. #define	SH7780_PCIAINTM		0xFE040134
    101. 

  101. #define	SH7780_PCIBMIR		0xFE040138
    102. 

  102. #define	SH7780_PCIPAR		0xFE0401C0
    103. 

  103. #define	SH7780_PCIPINT		0xFE0401CC
    104. 

  104. #define	SH7780_PCIPINTM		0xFE0401D0
    105. 

  105. #define	SH7780_PCIMBR0		0xFE0401E0
    106. 

  106. #define	SH7780_PCIMBMR0		0xFE0401E4
    107. 

  107. #define	SH7780_PCIMBR1		0xFE0401E8
    108. 

  108. #define	SH7780_PCIMBMR1		0xFE0401EC
    109. 

  109. #define	SH7780_PCIMBR2		0xFE0401F0
    110. 

  110. #define	SH7780_PCIMBMR2		0xFE0401F4
    111. 

  111. #define	SH7780_PCIIOBR		0xFE0401F8
    112. 

  112. #define	SH7780_PCIIOBMR		0xFE0401FC
    113. 

  113. #define	SH7780_PCICSCR0		0xFE040210
    114. 

  114. #define	SH7780_PCICSCR1		0xFE040214
    115. 

  115. #define	SH7780_PCICSAR0		0xFE040218
    116. 

  116. #define	SH7780_PCICSAR1		0xFE04021C
    117. 

  117. #define	SH7780_PCIPDR		0xFE040220
    118. 

  118. 

  119. #endif	/* _ASM_CPU_SH7780_H_ */
    120.