ls1012ardb.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #ifdef CONFIG_FSL_LS_PPA
  11. #include <asm/arch/ppa.h>
  12. #endif
  13. #include <asm/arch/mmu.h>
  14. #include <asm/arch/soc.h>
  15. #include <hwconfig.h>
  16. #include <ahci.h>
  17. #include <mmc.h>
  18. #include <scsi.h>
  19. #include <fsl_esdhc.h>
  20. #include <environment.h>
  21. #include <fsl_mmdc.h>
  22. #include <netdev.h>
  23. #include <fsl_sec.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int checkboard(void)
  26. {
  27. #ifdef CONFIG_TARGET_LS1012ARDB
  28. u8 in1;
  29. puts("Board: LS1012ARDB ");
  30. /* Initialize i2c early for Serial flash bank information */
  31. i2c_set_bus_num(0);
  32. if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
  33. printf("Error reading i2c boot information!\n");
  34. return 0; /* Don't want to hang() on this error */
  35. }
  36. puts("Version");
  37. switch (in1 & SW_REV_MASK) {
  38. case SW_REV_A:
  39. puts(": RevA");
  40. break;
  41. case SW_REV_B:
  42. puts(": RevB");
  43. break;
  44. case SW_REV_C:
  45. puts(": RevC");
  46. break;
  47. case SW_REV_C1:
  48. puts(": RevC1");
  49. break;
  50. case SW_REV_C2:
  51. puts(": RevC2");
  52. break;
  53. case SW_REV_D:
  54. puts(": RevD");
  55. break;
  56. case SW_REV_E:
  57. puts(": RevE");
  58. break;
  59. default:
  60. puts(": unknown");
  61. break;
  62. }
  63. printf(", boot from QSPI");
  64. if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
  65. puts(": emu\n");
  66. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
  67. puts(": bank1\n");
  68. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
  69. puts(": bank2\n");
  70. else
  71. puts("unknown\n");
  72. #else
  73. puts("Board: LS1012A2G5RDB ");
  74. #endif
  75. return 0;
  76. }
  77. int dram_init(void)
  78. {
  79. static const struct fsl_mmdc_info mparam = {
  80. 0x05180000, /* mdctl */
  81. 0x00030035, /* mdpdc */
  82. 0x12554000, /* mdotc */
  83. 0xbabf7954, /* mdcfg0 */
  84. 0xdb328f64, /* mdcfg1 */
  85. 0x01ff00db, /* mdcfg2 */
  86. 0x00001680, /* mdmisc */
  87. 0x0f3c8000, /* mdref */
  88. 0x00002000, /* mdrwd */
  89. 0x00bf1023, /* mdor */
  90. 0x0000003f, /* mdasp */
  91. 0x0000022a, /* mpodtctrl */
  92. 0xa1390003, /* mpzqhwctrl */
  93. };
  94. mmdc_init(&mparam);
  95. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  96. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  97. /* This will break-before-make MMU for DDR */
  98. update_early_mmu_table();
  99. #endif
  100. return 0;
  101. }
  102. int board_early_init_f(void)
  103. {
  104. fsl_lsch2_early_init_f();
  105. return 0;
  106. }
  107. int board_init(void)
  108. {
  109. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  110. CONFIG_SYS_CCI400_OFFSET);
  111. /*
  112. * Set CCI-400 control override register to enable barrier
  113. * transaction
  114. */
  115. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  116. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  117. erratum_a010315();
  118. #endif
  119. #ifdef CONFIG_ENV_IS_NOWHERE
  120. gd->env_addr = (ulong)&default_environment[0];
  121. #endif
  122. #ifdef CONFIG_FSL_CAAM
  123. sec_init();
  124. #endif
  125. #ifdef CONFIG_FSL_LS_PPA
  126. ppa_init();
  127. #endif
  128. return 0;
  129. }
  130. #ifdef CONFIG_TARGET_LS1012ARDB
  131. int esdhc_status_fixup(void *blob, const char *compat)
  132. {
  133. char esdhc1_path[] = "/soc/esdhc@1580000";
  134. bool sdhc2_en = false;
  135. u8 mux_sdhc2;
  136. u8 io = 0;
  137. i2c_set_bus_num(0);
  138. /* IO1[7:3] is the field of board revision info. */
  139. if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
  140. printf("Error reading i2c boot information!\n");
  141. return 0;
  142. }
  143. /* hwconfig method is used for RevD and later versions. */
  144. if ((io & SW_REV_MASK) <= SW_REV_D) {
  145. #ifdef CONFIG_HWCONFIG
  146. if (hwconfig("esdhc1"))
  147. sdhc2_en = true;
  148. #endif
  149. } else {
  150. /*
  151. * The I2C IO-expander for mux select is used to control
  152. * the muxing of various onboard interfaces.
  153. *
  154. * IO0[3:2] indicates SDHC2 interface demultiplexer
  155. * select lines.
  156. * 00 - SDIO wifi
  157. * 01 - GPIO (to Arduino)
  158. * 10 - eMMC Memory
  159. * 11 - SPI
  160. */
  161. if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
  162. printf("Error reading i2c boot information!\n");
  163. return 0;
  164. }
  165. mux_sdhc2 = (io & 0x0c) >> 2;
  166. /* Enable SDHC2 only when use SDIO wifi and eMMC */
  167. if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
  168. sdhc2_en = true;
  169. }
  170. if (sdhc2_en)
  171. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  172. sizeof("okay"), 1);
  173. else
  174. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  175. sizeof("disabled"), 1);
  176. return 0;
  177. }
  178. #endif
  179. int ft_board_setup(void *blob, bd_t *bd)
  180. {
  181. arch_fixup_fdt(blob);
  182. ft_cpu_setup(blob, bd);
  183. return 0;
  184. }