ap143.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/addrspace.h>
  8. #include <asm/types.h>
  9. #include <mach/ar71xx_regs.h>
  10. #include <mach/ddr.h>
  11. #include <mach/ath79.h>
  12. #include <debug_uart.h>
  13. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  14. void board_debug_uart_init(void)
  15. {
  16. void __iomem *regs;
  17. u32 val;
  18. regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
  19. MAP_NOCACHE);
  20. /*
  21. * GPIO9 as input, GPIO10 as output
  22. */
  23. val = readl(regs + AR71XX_GPIO_REG_OE);
  24. val |= QCA953X_GPIO(9);
  25. val &= ~QCA953X_GPIO(10);
  26. writel(val, regs + AR71XX_GPIO_REG_OE);
  27. /*
  28. * Enable GPIO10 as UART0_SOUT
  29. */
  30. val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
  31. val &= ~QCA953X_GPIO_MUX_MASK(16);
  32. val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
  33. writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
  34. /*
  35. * Enable GPIO9 as UART0_SIN
  36. */
  37. val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
  38. val &= ~QCA953X_GPIO_MUX_MASK(8);
  39. val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
  40. writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
  41. /*
  42. * Enable GPIO10 output
  43. */
  44. val = readl(regs + AR71XX_GPIO_REG_OUT);
  45. val |= QCA953X_GPIO(10);
  46. writel(val, regs + AR71XX_GPIO_REG_OUT);
  47. }
  48. #endif
  49. int board_early_init_f(void)
  50. {
  51. ddr_init();
  52. ath79_eth_reset();
  53. return 0;
  54. }