board_k2l.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K2L EVM : Board initialization
  4. *
  5. * (C) Copyright 2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <asm/arch/ddr3.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/ti-common/keystone_net.h>
  12. unsigned int get_external_clk(u32 clk)
  13. {
  14. unsigned int clk_freq;
  15. switch (clk) {
  16. case sys_clk:
  17. clk_freq = 122880000;
  18. break;
  19. case alt_core_clk:
  20. clk_freq = 100000000;
  21. break;
  22. case pa_clk:
  23. clk_freq = 122880000;
  24. break;
  25. case tetris_clk:
  26. clk_freq = 122880000;
  27. break;
  28. case ddr3a_clk:
  29. clk_freq = 100000000;
  30. break;
  31. default:
  32. clk_freq = 0;
  33. break;
  34. }
  35. return clk_freq;
  36. }
  37. static struct pll_init_data core_pll_config[NUM_SPDS] = {
  38. [SPD800] = CORE_PLL_799,
  39. [SPD1000] = CORE_PLL_1000,
  40. [SPD1200] = CORE_PLL_1198,
  41. };
  42. s16 divn_val[16] = {
  43. 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  44. };
  45. static struct pll_init_data tetris_pll_config[] = {
  46. [SPD800] = TETRIS_PLL_799,
  47. [SPD1000] = TETRIS_PLL_1000,
  48. [SPD1200] = TETRIS_PLL_1198,
  49. [SPD1350] = TETRIS_PLL_1352,
  50. [SPD1400] = TETRIS_PLL_1401,
  51. };
  52. static struct pll_init_data pa_pll_config =
  53. PASS_PLL_983;
  54. struct pll_init_data *get_pll_init_data(int pll)
  55. {
  56. int speed;
  57. struct pll_init_data *data;
  58. switch (pll) {
  59. case MAIN_PLL:
  60. speed = get_max_dev_speed(speeds);
  61. data = &core_pll_config[speed];
  62. break;
  63. case TETRIS_PLL:
  64. speed = get_max_arm_speed(speeds);
  65. data = &tetris_pll_config[speed];
  66. break;
  67. case PASS_PLL:
  68. data = &pa_pll_config;
  69. break;
  70. default:
  71. data = NULL;
  72. }
  73. return data;
  74. }
  75. #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  76. struct eth_priv_t eth_priv_cfg[] = {
  77. {
  78. .int_name = "K2L_EMAC",
  79. .rx_flow = 0,
  80. .phy_addr = 0,
  81. .slave_port = 1,
  82. .sgmii_link_type = SGMII_LINK_MAC_PHY,
  83. .phy_if = PHY_INTERFACE_MODE_SGMII,
  84. },
  85. {
  86. .int_name = "K2L_EMAC1",
  87. .rx_flow = 8,
  88. .phy_addr = 1,
  89. .slave_port = 2,
  90. .sgmii_link_type = SGMII_LINK_MAC_PHY,
  91. .phy_if = PHY_INTERFACE_MODE_SGMII,
  92. },
  93. {
  94. .int_name = "K2L_EMAC2",
  95. .rx_flow = 16,
  96. .phy_addr = 2,
  97. .slave_port = 3,
  98. .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  99. .phy_if = PHY_INTERFACE_MODE_SGMII,
  100. },
  101. {
  102. .int_name = "K2L_EMAC3",
  103. .rx_flow = 32,
  104. .phy_addr = 3,
  105. .slave_port = 4,
  106. .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  107. .phy_if = PHY_INTERFACE_MODE_SGMII,
  108. },
  109. };
  110. int get_num_eth_ports(void)
  111. {
  112. return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
  113. }
  114. #endif
  115. #ifdef CONFIG_BOARD_EARLY_INIT_F
  116. int board_early_init_f(void)
  117. {
  118. init_plls();
  119. return 0;
  120. }
  121. #endif
  122. #if defined(CONFIG_MULTI_DTB_FIT)
  123. int board_fit_config_name_match(const char *name)
  124. {
  125. if (!strcmp(name, "keystone-k2l-evm"))
  126. return 0;
  127. return -1;
  128. }
  129. #endif
  130. #ifdef CONFIG_SPL_BUILD
  131. void spl_init_keystone_plls(void)
  132. {
  133. init_plls();
  134. }
  135. #endif