pata_pxa.c 8.5 KB

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  1. /*
  2. * Generic PXA PATA driver
  3. *
  4. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2, or (at your option)
  9. * any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; see the file COPYING. If not, write to
  18. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/ata.h>
  24. #include <linux/libata.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/dmaengine.h>
  27. #include <linux/gpio.h>
  28. #include <linux/slab.h>
  29. #include <linux/completion.h>
  30. #include <scsi/scsi_host.h>
  31. #include <linux/platform_data/ata-pxa.h>
  32. #define DRV_NAME "pata_pxa"
  33. #define DRV_VERSION "0.1"
  34. struct pata_pxa_data {
  35. struct dma_chan *dma_chan;
  36. dma_cookie_t dma_cookie;
  37. struct completion dma_done;
  38. };
  39. /*
  40. * DMA interrupt handler.
  41. */
  42. static void pxa_ata_dma_irq(void *d)
  43. {
  44. struct pata_pxa_data *pd = d;
  45. enum dma_status status;
  46. status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
  47. if (status == DMA_ERROR || status == DMA_COMPLETE)
  48. complete(&pd->dma_done);
  49. }
  50. /*
  51. * Prepare taskfile for submission.
  52. */
  53. static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
  54. {
  55. struct pata_pxa_data *pd = qc->ap->private_data;
  56. struct dma_async_tx_descriptor *tx;
  57. enum dma_transfer_direction dir;
  58. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  59. return AC_ERR_OK;
  60. dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
  61. tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
  62. DMA_PREP_INTERRUPT);
  63. if (!tx) {
  64. ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
  65. return AC_ERR_OK;
  66. }
  67. tx->callback = pxa_ata_dma_irq;
  68. tx->callback_param = pd;
  69. pd->dma_cookie = dmaengine_submit(tx);
  70. return AC_ERR_OK;
  71. }
  72. /*
  73. * Configure the DMA controller, load the DMA descriptors, but don't start the
  74. * DMA controller yet. Only issue the ATA command.
  75. */
  76. static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
  77. {
  78. qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
  79. }
  80. /*
  81. * Execute the DMA transfer.
  82. */
  83. static void pxa_bmdma_start(struct ata_queued_cmd *qc)
  84. {
  85. struct pata_pxa_data *pd = qc->ap->private_data;
  86. init_completion(&pd->dma_done);
  87. dma_async_issue_pending(pd->dma_chan);
  88. }
  89. /*
  90. * Wait until the DMA transfer completes, then stop the DMA controller.
  91. */
  92. static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
  93. {
  94. struct pata_pxa_data *pd = qc->ap->private_data;
  95. enum dma_status status;
  96. status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
  97. if (status != DMA_ERROR && status != DMA_COMPLETE &&
  98. wait_for_completion_timeout(&pd->dma_done, HZ))
  99. ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
  100. dmaengine_terminate_all(pd->dma_chan);
  101. }
  102. /*
  103. * Read DMA status. The bmdma_stop() will take care of properly finishing the
  104. * DMA transfer so we always have DMA-complete interrupt here.
  105. */
  106. static unsigned char pxa_bmdma_status(struct ata_port *ap)
  107. {
  108. struct pata_pxa_data *pd = ap->private_data;
  109. unsigned char ret = ATA_DMA_INTR;
  110. struct dma_tx_state state;
  111. enum dma_status status;
  112. status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
  113. if (status != DMA_COMPLETE)
  114. ret |= ATA_DMA_ERR;
  115. return ret;
  116. }
  117. /*
  118. * No IRQ register present so we do nothing.
  119. */
  120. static void pxa_irq_clear(struct ata_port *ap)
  121. {
  122. }
  123. /*
  124. * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
  125. * unclear why ATAPI has DMA issues.
  126. */
  127. static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
  128. {
  129. return -EOPNOTSUPP;
  130. }
  131. static struct scsi_host_template pxa_ata_sht = {
  132. ATA_BMDMA_SHT(DRV_NAME),
  133. };
  134. static struct ata_port_operations pxa_ata_port_ops = {
  135. .inherits = &ata_bmdma_port_ops,
  136. .cable_detect = ata_cable_40wire,
  137. .bmdma_setup = pxa_bmdma_setup,
  138. .bmdma_start = pxa_bmdma_start,
  139. .bmdma_stop = pxa_bmdma_stop,
  140. .bmdma_status = pxa_bmdma_status,
  141. .check_atapi_dma = pxa_check_atapi_dma,
  142. .sff_irq_clear = pxa_irq_clear,
  143. .qc_prep = pxa_qc_prep,
  144. };
  145. static int pxa_ata_probe(struct platform_device *pdev)
  146. {
  147. struct ata_host *host;
  148. struct ata_port *ap;
  149. struct pata_pxa_data *data;
  150. struct resource *cmd_res;
  151. struct resource *ctl_res;
  152. struct resource *dma_res;
  153. struct resource *irq_res;
  154. struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
  155. struct dma_slave_config config;
  156. int ret = 0;
  157. /*
  158. * Resource validation, three resources are needed:
  159. * - CMD port base address
  160. * - CTL port base address
  161. * - DMA port base address
  162. * - IRQ pin
  163. */
  164. if (pdev->num_resources != 4) {
  165. dev_err(&pdev->dev, "invalid number of resources\n");
  166. return -EINVAL;
  167. }
  168. /*
  169. * CMD port base address
  170. */
  171. cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  172. if (unlikely(cmd_res == NULL))
  173. return -EINVAL;
  174. /*
  175. * CTL port base address
  176. */
  177. ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  178. if (unlikely(ctl_res == NULL))
  179. return -EINVAL;
  180. /*
  181. * DMA port base address
  182. */
  183. dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  184. if (unlikely(dma_res == NULL))
  185. return -EINVAL;
  186. /*
  187. * IRQ pin
  188. */
  189. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  190. if (unlikely(irq_res == NULL))
  191. return -EINVAL;
  192. /*
  193. * Allocate the host
  194. */
  195. host = ata_host_alloc(&pdev->dev, 1);
  196. if (!host)
  197. return -ENOMEM;
  198. ap = host->ports[0];
  199. ap->ops = &pxa_ata_port_ops;
  200. ap->pio_mask = ATA_PIO4;
  201. ap->mwdma_mask = ATA_MWDMA2;
  202. ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
  203. resource_size(cmd_res));
  204. ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
  205. resource_size(ctl_res));
  206. ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
  207. resource_size(dma_res));
  208. /*
  209. * Adjust register offsets
  210. */
  211. ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
  212. ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
  213. (ATA_REG_DATA << pdata->reg_shift);
  214. ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
  215. (ATA_REG_ERR << pdata->reg_shift);
  216. ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
  217. (ATA_REG_FEATURE << pdata->reg_shift);
  218. ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
  219. (ATA_REG_NSECT << pdata->reg_shift);
  220. ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
  221. (ATA_REG_LBAL << pdata->reg_shift);
  222. ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
  223. (ATA_REG_LBAM << pdata->reg_shift);
  224. ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
  225. (ATA_REG_LBAH << pdata->reg_shift);
  226. ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
  227. (ATA_REG_DEVICE << pdata->reg_shift);
  228. ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
  229. (ATA_REG_STATUS << pdata->reg_shift);
  230. ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
  231. (ATA_REG_CMD << pdata->reg_shift);
  232. /*
  233. * Allocate and load driver's internal data structure
  234. */
  235. data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
  236. GFP_KERNEL);
  237. if (!data)
  238. return -ENOMEM;
  239. ap->private_data = data;
  240. memset(&config, 0, sizeof(config));
  241. config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  242. config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  243. config.src_addr = dma_res->start;
  244. config.dst_addr = dma_res->start;
  245. config.src_maxburst = 32;
  246. config.dst_maxburst = 32;
  247. /*
  248. * Request the DMA channel
  249. */
  250. data->dma_chan =
  251. dma_request_slave_channel(&pdev->dev, "data");
  252. if (!data->dma_chan)
  253. return -EBUSY;
  254. ret = dmaengine_slave_config(data->dma_chan, &config);
  255. if (ret < 0) {
  256. dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
  257. return ret;
  258. }
  259. /*
  260. * Activate the ATA host
  261. */
  262. ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
  263. pdata->irq_flags, &pxa_ata_sht);
  264. if (ret)
  265. dma_release_channel(data->dma_chan);
  266. return ret;
  267. }
  268. static int pxa_ata_remove(struct platform_device *pdev)
  269. {
  270. struct ata_host *host = platform_get_drvdata(pdev);
  271. struct pata_pxa_data *data = host->ports[0]->private_data;
  272. dma_release_channel(data->dma_chan);
  273. ata_host_detach(host);
  274. return 0;
  275. }
  276. static struct platform_driver pxa_ata_driver = {
  277. .probe = pxa_ata_probe,
  278. .remove = pxa_ata_remove,
  279. .driver = {
  280. .name = DRV_NAME,
  281. },
  282. };
  283. module_platform_driver(pxa_ata_driver);
  284. MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
  285. MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
  286. MODULE_LICENSE("GPL");
  287. MODULE_VERSION(DRV_VERSION);
  288. MODULE_ALIAS("platform:" DRV_NAME);