clk.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __MACH_IMX_CLK_H
  3. #define __MACH_IMX_CLK_H
  4. #include <linux/spinlock.h>
  5. #include <linux/clk-provider.h>
  6. extern spinlock_t imx_ccm_lock;
  7. void imx_check_clocks(struct clk *clks[], unsigned int count);
  8. void imx_register_uart_clocks(struct clk ** const clks[]);
  9. extern void imx_cscmr1_fixup(u32 *val);
  10. enum imx_pllv1_type {
  11. IMX_PLLV1_IMX1,
  12. IMX_PLLV1_IMX21,
  13. IMX_PLLV1_IMX25,
  14. IMX_PLLV1_IMX27,
  15. IMX_PLLV1_IMX31,
  16. IMX_PLLV1_IMX35,
  17. };
  18. struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
  19. const char *parent, void __iomem *base);
  20. struct clk *imx_clk_pllv2(const char *name, const char *parent,
  21. void __iomem *base);
  22. enum imx_pllv3_type {
  23. IMX_PLLV3_GENERIC,
  24. IMX_PLLV3_SYS,
  25. IMX_PLLV3_USB,
  26. IMX_PLLV3_USB_VF610,
  27. IMX_PLLV3_AV,
  28. IMX_PLLV3_ENET,
  29. IMX_PLLV3_ENET_IMX7,
  30. IMX_PLLV3_SYS_VF610,
  31. IMX_PLLV3_DDR_IMX7,
  32. };
  33. struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  34. const char *parent_name, void __iomem *base, u32 div_mask);
  35. struct clk *clk_register_gate2(struct device *dev, const char *name,
  36. const char *parent_name, unsigned long flags,
  37. void __iomem *reg, u8 bit_idx, u8 cgr_val,
  38. u8 clk_gate_flags, spinlock_t *lock,
  39. unsigned int *share_count);
  40. struct clk * imx_obtain_fixed_clock(
  41. const char *name, unsigned long rate);
  42. struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
  43. void __iomem *reg, u8 shift, u32 exclusive_mask);
  44. struct clk *imx_clk_pfd(const char *name, const char *parent_name,
  45. void __iomem *reg, u8 idx);
  46. struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
  47. void __iomem *reg, u8 shift, u8 width,
  48. void __iomem *busy_reg, u8 busy_shift);
  49. struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
  50. u8 width, void __iomem *busy_reg, u8 busy_shift,
  51. const char * const *parent_names, int num_parents);
  52. struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
  53. void __iomem *reg, u8 shift, u8 width,
  54. void (*fixup)(u32 *val));
  55. struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
  56. u8 shift, u8 width, const char * const *parents,
  57. int num_parents, void (*fixup)(u32 *val));
  58. static inline struct clk *imx_clk_fixed(const char *name, int rate)
  59. {
  60. return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  61. }
  62. static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
  63. u8 shift, u8 width, const char * const *parents,
  64. int num_parents)
  65. {
  66. return clk_register_mux(NULL, name, parents, num_parents,
  67. CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
  68. shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
  69. }
  70. static inline struct clk *imx_clk_fixed_factor(const char *name,
  71. const char *parent, unsigned int mult, unsigned int div)
  72. {
  73. return clk_register_fixed_factor(NULL, name, parent,
  74. CLK_SET_RATE_PARENT, mult, div);
  75. }
  76. static inline struct clk *imx_clk_divider(const char *name, const char *parent,
  77. void __iomem *reg, u8 shift, u8 width)
  78. {
  79. return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
  80. reg, shift, width, 0, &imx_ccm_lock);
  81. }
  82. static inline struct clk *imx_clk_divider_flags(const char *name,
  83. const char *parent, void __iomem *reg, u8 shift, u8 width,
  84. unsigned long flags)
  85. {
  86. return clk_register_divider(NULL, name, parent, flags,
  87. reg, shift, width, 0, &imx_ccm_lock);
  88. }
  89. static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
  90. void __iomem *reg, u8 shift, u8 width)
  91. {
  92. return clk_register_divider(NULL, name, parent,
  93. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  94. reg, shift, width, 0, &imx_ccm_lock);
  95. }
  96. static inline struct clk *imx_clk_gate(const char *name, const char *parent,
  97. void __iomem *reg, u8 shift)
  98. {
  99. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  100. shift, 0, &imx_ccm_lock);
  101. }
  102. static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
  103. void __iomem *reg, u8 shift, unsigned long flags)
  104. {
  105. return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
  106. shift, 0, &imx_ccm_lock);
  107. }
  108. static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
  109. void __iomem *reg, u8 shift)
  110. {
  111. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  112. shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
  113. }
  114. static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
  115. void __iomem *reg, u8 shift)
  116. {
  117. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  118. shift, 0x3, 0, &imx_ccm_lock, NULL);
  119. }
  120. static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
  121. void __iomem *reg, u8 shift, unsigned long flags)
  122. {
  123. return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
  124. shift, 0x3, 0, &imx_ccm_lock, NULL);
  125. }
  126. static inline struct clk *imx_clk_gate2_shared(const char *name,
  127. const char *parent, void __iomem *reg, u8 shift,
  128. unsigned int *share_count)
  129. {
  130. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  131. shift, 0x3, 0, &imx_ccm_lock, share_count);
  132. }
  133. static inline struct clk *imx_clk_gate2_shared2(const char *name,
  134. const char *parent, void __iomem *reg, u8 shift,
  135. unsigned int *share_count)
  136. {
  137. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
  138. CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
  139. &imx_ccm_lock, share_count);
  140. }
  141. static inline struct clk *imx_clk_gate2_cgr(const char *name,
  142. const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
  143. {
  144. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  145. shift, cgr_val, 0, &imx_ccm_lock, NULL);
  146. }
  147. static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
  148. void __iomem *reg, u8 shift)
  149. {
  150. return clk_register_gate(NULL, name, parent,
  151. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  152. reg, shift, 0, &imx_ccm_lock);
  153. }
  154. static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
  155. void __iomem *reg, u8 shift)
  156. {
  157. return clk_register_gate2(NULL, name, parent,
  158. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  159. reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
  160. }
  161. static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
  162. u8 shift, u8 width, const char * const *parents,
  163. int num_parents)
  164. {
  165. return clk_register_mux(NULL, name, parents, num_parents,
  166. CLK_SET_RATE_NO_REPARENT, reg, shift,
  167. width, 0, &imx_ccm_lock);
  168. }
  169. static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
  170. u8 shift, u8 width, const char * const *parents,
  171. int num_parents)
  172. {
  173. return clk_register_mux(NULL, name, parents, num_parents,
  174. CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
  175. reg, shift, width, 0, &imx_ccm_lock);
  176. }
  177. static inline struct clk *imx_clk_mux_flags(const char *name,
  178. void __iomem *reg, u8 shift, u8 width,
  179. const char * const *parents, int num_parents,
  180. unsigned long flags)
  181. {
  182. return clk_register_mux(NULL, name, parents, num_parents,
  183. flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
  184. &imx_ccm_lock);
  185. }
  186. struct clk *imx_clk_cpu(const char *name, const char *parent_name,
  187. struct clk *div, struct clk *mux, struct clk *pll,
  188. struct clk *step);
  189. #endif