clk-mpll.c 3.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2. /*
  3. * Copyright (c) 2016 AmLogic, Inc.
  4. * Author: Michael Turquette <mturquette@baylibre.com>
  5. */
  6. /*
  7. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  8. * scaling capabilities. MPLL rates are calculated as:
  9. *
  10. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  11. */
  12. #include <linux/clk-provider.h>
  13. #include "clkc.h"
  14. #define SDM_DEN 16384
  15. #define N2_MIN 4
  16. #define N2_MAX 511
  17. static inline struct meson_clk_mpll_data *
  18. meson_clk_mpll_data(struct clk_regmap *clk)
  19. {
  20. return (struct meson_clk_mpll_data *)clk->data;
  21. }
  22. static long rate_from_params(unsigned long parent_rate,
  23. unsigned int sdm,
  24. unsigned int n2)
  25. {
  26. unsigned long divisor = (SDM_DEN * n2) + sdm;
  27. if (n2 < N2_MIN)
  28. return -EINVAL;
  29. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  30. }
  31. static void params_from_rate(unsigned long requested_rate,
  32. unsigned long parent_rate,
  33. unsigned int *sdm,
  34. unsigned int *n2,
  35. u8 flags)
  36. {
  37. uint64_t div = parent_rate;
  38. uint64_t frac = do_div(div, requested_rate);
  39. frac *= SDM_DEN;
  40. if (flags & CLK_MESON_MPLL_ROUND_CLOSEST)
  41. *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate);
  42. else
  43. *sdm = DIV_ROUND_UP_ULL(frac, requested_rate);
  44. if (*sdm == SDM_DEN) {
  45. *sdm = 0;
  46. div += 1;
  47. }
  48. if (div < N2_MIN) {
  49. *n2 = N2_MIN;
  50. *sdm = 0;
  51. } else if (div > N2_MAX) {
  52. *n2 = N2_MAX;
  53. *sdm = SDM_DEN - 1;
  54. } else {
  55. *n2 = div;
  56. }
  57. }
  58. static unsigned long mpll_recalc_rate(struct clk_hw *hw,
  59. unsigned long parent_rate)
  60. {
  61. struct clk_regmap *clk = to_clk_regmap(hw);
  62. struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
  63. unsigned int sdm, n2;
  64. long rate;
  65. sdm = meson_parm_read(clk->map, &mpll->sdm);
  66. n2 = meson_parm_read(clk->map, &mpll->n2);
  67. rate = rate_from_params(parent_rate, sdm, n2);
  68. return rate < 0 ? 0 : rate;
  69. }
  70. static long mpll_round_rate(struct clk_hw *hw,
  71. unsigned long rate,
  72. unsigned long *parent_rate)
  73. {
  74. struct clk_regmap *clk = to_clk_regmap(hw);
  75. struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
  76. unsigned int sdm, n2;
  77. params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
  78. return rate_from_params(*parent_rate, sdm, n2);
  79. }
  80. static int mpll_set_rate(struct clk_hw *hw,
  81. unsigned long rate,
  82. unsigned long parent_rate)
  83. {
  84. struct clk_regmap *clk = to_clk_regmap(hw);
  85. struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
  86. unsigned int sdm, n2;
  87. unsigned long flags = 0;
  88. params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
  89. if (mpll->lock)
  90. spin_lock_irqsave(mpll->lock, flags);
  91. else
  92. __acquire(mpll->lock);
  93. /* Enable and set the fractional part */
  94. meson_parm_write(clk->map, &mpll->sdm, sdm);
  95. meson_parm_write(clk->map, &mpll->sdm_en, 1);
  96. /* Set additional fractional part enable if required */
  97. if (MESON_PARM_APPLICABLE(&mpll->ssen))
  98. meson_parm_write(clk->map, &mpll->ssen, 1);
  99. /* Set the integer divider part */
  100. meson_parm_write(clk->map, &mpll->n2, n2);
  101. /* Set the magic misc bit if required */
  102. if (MESON_PARM_APPLICABLE(&mpll->misc))
  103. meson_parm_write(clk->map, &mpll->misc, 1);
  104. if (mpll->lock)
  105. spin_unlock_irqrestore(mpll->lock, flags);
  106. else
  107. __release(mpll->lock);
  108. return 0;
  109. }
  110. const struct clk_ops meson_clk_mpll_ro_ops = {
  111. .recalc_rate = mpll_recalc_rate,
  112. .round_rate = mpll_round_rate,
  113. };
  114. const struct clk_ops meson_clk_mpll_ops = {
  115. .recalc_rate = mpll_recalc_rate,
  116. .round_rate = mpll_round_rate,
  117. .set_rate = mpll_set_rate,
  118. };