meson8b.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015 Endless Mobile, Inc.
  4. * Author: Carlo Caione <carlo@endlessm.com>
  5. *
  6. * Copyright (c) 2016 BayLibre, Inc.
  7. * Michael Turquette <mturquette@baylibre.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/init.h>
  12. #include <linux/of_address.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/reset-controller.h>
  15. #include <linux/slab.h>
  16. #include <linux/regmap.h>
  17. #include "clkc.h"
  18. #include "meson8b.h"
  19. #include "clk-regmap.h"
  20. static DEFINE_SPINLOCK(meson_clk_lock);
  21. static void __iomem *clk_base;
  22. struct meson8b_clk_reset {
  23. struct reset_controller_dev reset;
  24. void __iomem *base;
  25. };
  26. static const struct pll_rate_table sys_pll_rate_table[] = {
  27. PLL_RATE(312000000, 52, 1, 2),
  28. PLL_RATE(336000000, 56, 1, 2),
  29. PLL_RATE(360000000, 60, 1, 2),
  30. PLL_RATE(384000000, 64, 1, 2),
  31. PLL_RATE(408000000, 68, 1, 2),
  32. PLL_RATE(432000000, 72, 1, 2),
  33. PLL_RATE(456000000, 76, 1, 2),
  34. PLL_RATE(480000000, 80, 1, 2),
  35. PLL_RATE(504000000, 84, 1, 2),
  36. PLL_RATE(528000000, 88, 1, 2),
  37. PLL_RATE(552000000, 92, 1, 2),
  38. PLL_RATE(576000000, 96, 1, 2),
  39. PLL_RATE(600000000, 50, 1, 1),
  40. PLL_RATE(624000000, 52, 1, 1),
  41. PLL_RATE(648000000, 54, 1, 1),
  42. PLL_RATE(672000000, 56, 1, 1),
  43. PLL_RATE(696000000, 58, 1, 1),
  44. PLL_RATE(720000000, 60, 1, 1),
  45. PLL_RATE(744000000, 62, 1, 1),
  46. PLL_RATE(768000000, 64, 1, 1),
  47. PLL_RATE(792000000, 66, 1, 1),
  48. PLL_RATE(816000000, 68, 1, 1),
  49. PLL_RATE(840000000, 70, 1, 1),
  50. PLL_RATE(864000000, 72, 1, 1),
  51. PLL_RATE(888000000, 74, 1, 1),
  52. PLL_RATE(912000000, 76, 1, 1),
  53. PLL_RATE(936000000, 78, 1, 1),
  54. PLL_RATE(960000000, 80, 1, 1),
  55. PLL_RATE(984000000, 82, 1, 1),
  56. PLL_RATE(1008000000, 84, 1, 1),
  57. PLL_RATE(1032000000, 86, 1, 1),
  58. PLL_RATE(1056000000, 88, 1, 1),
  59. PLL_RATE(1080000000, 90, 1, 1),
  60. PLL_RATE(1104000000, 92, 1, 1),
  61. PLL_RATE(1128000000, 94, 1, 1),
  62. PLL_RATE(1152000000, 96, 1, 1),
  63. PLL_RATE(1176000000, 98, 1, 1),
  64. PLL_RATE(1200000000, 50, 1, 0),
  65. PLL_RATE(1224000000, 51, 1, 0),
  66. PLL_RATE(1248000000, 52, 1, 0),
  67. PLL_RATE(1272000000, 53, 1, 0),
  68. PLL_RATE(1296000000, 54, 1, 0),
  69. PLL_RATE(1320000000, 55, 1, 0),
  70. PLL_RATE(1344000000, 56, 1, 0),
  71. PLL_RATE(1368000000, 57, 1, 0),
  72. PLL_RATE(1392000000, 58, 1, 0),
  73. PLL_RATE(1416000000, 59, 1, 0),
  74. PLL_RATE(1440000000, 60, 1, 0),
  75. PLL_RATE(1464000000, 61, 1, 0),
  76. PLL_RATE(1488000000, 62, 1, 0),
  77. PLL_RATE(1512000000, 63, 1, 0),
  78. PLL_RATE(1536000000, 64, 1, 0),
  79. { /* sentinel */ },
  80. };
  81. static struct clk_fixed_rate meson8b_xtal = {
  82. .fixed_rate = 24000000,
  83. .hw.init = &(struct clk_init_data){
  84. .name = "xtal",
  85. .num_parents = 0,
  86. .ops = &clk_fixed_rate_ops,
  87. },
  88. };
  89. static struct clk_regmap meson8b_fixed_pll = {
  90. .data = &(struct meson_clk_pll_data){
  91. .m = {
  92. .reg_off = HHI_MPLL_CNTL,
  93. .shift = 0,
  94. .width = 9,
  95. },
  96. .n = {
  97. .reg_off = HHI_MPLL_CNTL,
  98. .shift = 9,
  99. .width = 5,
  100. },
  101. .od = {
  102. .reg_off = HHI_MPLL_CNTL,
  103. .shift = 16,
  104. .width = 2,
  105. },
  106. .frac = {
  107. .reg_off = HHI_MPLL_CNTL2,
  108. .shift = 0,
  109. .width = 12,
  110. },
  111. .l = {
  112. .reg_off = HHI_MPLL_CNTL,
  113. .shift = 31,
  114. .width = 1,
  115. },
  116. .rst = {
  117. .reg_off = HHI_MPLL_CNTL,
  118. .shift = 29,
  119. .width = 1,
  120. },
  121. },
  122. .hw.init = &(struct clk_init_data){
  123. .name = "fixed_pll",
  124. .ops = &meson_clk_pll_ro_ops,
  125. .parent_names = (const char *[]){ "xtal" },
  126. .num_parents = 1,
  127. },
  128. };
  129. static struct clk_regmap meson8b_vid_pll = {
  130. .data = &(struct meson_clk_pll_data){
  131. .m = {
  132. .reg_off = HHI_VID_PLL_CNTL,
  133. .shift = 0,
  134. .width = 9,
  135. },
  136. .n = {
  137. .reg_off = HHI_VID_PLL_CNTL,
  138. .shift = 10,
  139. .width = 5,
  140. },
  141. .od = {
  142. .reg_off = HHI_VID_PLL_CNTL,
  143. .shift = 16,
  144. .width = 2,
  145. },
  146. .l = {
  147. .reg_off = HHI_VID_PLL_CNTL,
  148. .shift = 31,
  149. .width = 1,
  150. },
  151. .rst = {
  152. .reg_off = HHI_VID_PLL_CNTL,
  153. .shift = 29,
  154. .width = 1,
  155. },
  156. },
  157. .hw.init = &(struct clk_init_data){
  158. .name = "vid_pll",
  159. .ops = &meson_clk_pll_ro_ops,
  160. .parent_names = (const char *[]){ "xtal" },
  161. .num_parents = 1,
  162. },
  163. };
  164. static struct clk_regmap meson8b_sys_pll = {
  165. .data = &(struct meson_clk_pll_data){
  166. .m = {
  167. .reg_off = HHI_SYS_PLL_CNTL,
  168. .shift = 0,
  169. .width = 9,
  170. },
  171. .n = {
  172. .reg_off = HHI_SYS_PLL_CNTL,
  173. .shift = 9,
  174. .width = 5,
  175. },
  176. .od = {
  177. .reg_off = HHI_SYS_PLL_CNTL,
  178. .shift = 16,
  179. .width = 2,
  180. },
  181. .l = {
  182. .reg_off = HHI_SYS_PLL_CNTL,
  183. .shift = 31,
  184. .width = 1,
  185. },
  186. .rst = {
  187. .reg_off = HHI_SYS_PLL_CNTL,
  188. .shift = 29,
  189. .width = 1,
  190. },
  191. .table = sys_pll_rate_table,
  192. },
  193. .hw.init = &(struct clk_init_data){
  194. .name = "sys_pll",
  195. .ops = &meson_clk_pll_ro_ops,
  196. .parent_names = (const char *[]){ "xtal" },
  197. .num_parents = 1,
  198. },
  199. };
  200. static struct clk_fixed_factor meson8b_fclk_div2_div = {
  201. .mult = 1,
  202. .div = 2,
  203. .hw.init = &(struct clk_init_data){
  204. .name = "fclk_div2_div",
  205. .ops = &clk_fixed_factor_ops,
  206. .parent_names = (const char *[]){ "fixed_pll" },
  207. .num_parents = 1,
  208. },
  209. };
  210. static struct clk_regmap meson8b_fclk_div2 = {
  211. .data = &(struct clk_regmap_gate_data){
  212. .offset = HHI_MPLL_CNTL6,
  213. .bit_idx = 27,
  214. },
  215. .hw.init = &(struct clk_init_data){
  216. .name = "fclk_div2",
  217. .ops = &clk_regmap_gate_ops,
  218. .parent_names = (const char *[]){ "fclk_div2_div" },
  219. .num_parents = 1,
  220. /*
  221. * FIXME: Ethernet with a RGMII PHYs is not working if
  222. * fclk_div2 is disabled. it is currently unclear why this
  223. * is. keep it enabled until the Ethernet driver knows how
  224. * to manage this clock.
  225. */
  226. .flags = CLK_IS_CRITICAL,
  227. },
  228. };
  229. static struct clk_fixed_factor meson8b_fclk_div3_div = {
  230. .mult = 1,
  231. .div = 3,
  232. .hw.init = &(struct clk_init_data){
  233. .name = "fclk_div3_div",
  234. .ops = &clk_fixed_factor_ops,
  235. .parent_names = (const char *[]){ "fixed_pll" },
  236. .num_parents = 1,
  237. },
  238. };
  239. static struct clk_regmap meson8b_fclk_div3 = {
  240. .data = &(struct clk_regmap_gate_data){
  241. .offset = HHI_MPLL_CNTL6,
  242. .bit_idx = 28,
  243. },
  244. .hw.init = &(struct clk_init_data){
  245. .name = "fclk_div3",
  246. .ops = &clk_regmap_gate_ops,
  247. .parent_names = (const char *[]){ "fclk_div3_div" },
  248. .num_parents = 1,
  249. },
  250. };
  251. static struct clk_fixed_factor meson8b_fclk_div4_div = {
  252. .mult = 1,
  253. .div = 4,
  254. .hw.init = &(struct clk_init_data){
  255. .name = "fclk_div4_div",
  256. .ops = &clk_fixed_factor_ops,
  257. .parent_names = (const char *[]){ "fixed_pll" },
  258. .num_parents = 1,
  259. },
  260. };
  261. static struct clk_regmap meson8b_fclk_div4 = {
  262. .data = &(struct clk_regmap_gate_data){
  263. .offset = HHI_MPLL_CNTL6,
  264. .bit_idx = 29,
  265. },
  266. .hw.init = &(struct clk_init_data){
  267. .name = "fclk_div4",
  268. .ops = &clk_regmap_gate_ops,
  269. .parent_names = (const char *[]){ "fclk_div4_div" },
  270. .num_parents = 1,
  271. },
  272. };
  273. static struct clk_fixed_factor meson8b_fclk_div5_div = {
  274. .mult = 1,
  275. .div = 5,
  276. .hw.init = &(struct clk_init_data){
  277. .name = "fclk_div5_div",
  278. .ops = &clk_fixed_factor_ops,
  279. .parent_names = (const char *[]){ "fixed_pll" },
  280. .num_parents = 1,
  281. },
  282. };
  283. static struct clk_regmap meson8b_fclk_div5 = {
  284. .data = &(struct clk_regmap_gate_data){
  285. .offset = HHI_MPLL_CNTL6,
  286. .bit_idx = 30,
  287. },
  288. .hw.init = &(struct clk_init_data){
  289. .name = "fclk_div5",
  290. .ops = &clk_regmap_gate_ops,
  291. .parent_names = (const char *[]){ "fclk_div5_div" },
  292. .num_parents = 1,
  293. },
  294. };
  295. static struct clk_fixed_factor meson8b_fclk_div7_div = {
  296. .mult = 1,
  297. .div = 7,
  298. .hw.init = &(struct clk_init_data){
  299. .name = "fclk_div7_div",
  300. .ops = &clk_fixed_factor_ops,
  301. .parent_names = (const char *[]){ "fixed_pll" },
  302. .num_parents = 1,
  303. },
  304. };
  305. static struct clk_regmap meson8b_fclk_div7 = {
  306. .data = &(struct clk_regmap_gate_data){
  307. .offset = HHI_MPLL_CNTL6,
  308. .bit_idx = 31,
  309. },
  310. .hw.init = &(struct clk_init_data){
  311. .name = "fclk_div7",
  312. .ops = &clk_regmap_gate_ops,
  313. .parent_names = (const char *[]){ "fclk_div7_div" },
  314. .num_parents = 1,
  315. },
  316. };
  317. static struct clk_regmap meson8b_mpll_prediv = {
  318. .data = &(struct clk_regmap_div_data){
  319. .offset = HHI_MPLL_CNTL5,
  320. .shift = 12,
  321. .width = 1,
  322. },
  323. .hw.init = &(struct clk_init_data){
  324. .name = "mpll_prediv",
  325. .ops = &clk_regmap_divider_ro_ops,
  326. .parent_names = (const char *[]){ "fixed_pll" },
  327. .num_parents = 1,
  328. },
  329. };
  330. static struct clk_regmap meson8b_mpll0_div = {
  331. .data = &(struct meson_clk_mpll_data){
  332. .sdm = {
  333. .reg_off = HHI_MPLL_CNTL7,
  334. .shift = 0,
  335. .width = 14,
  336. },
  337. .sdm_en = {
  338. .reg_off = HHI_MPLL_CNTL7,
  339. .shift = 15,
  340. .width = 1,
  341. },
  342. .n2 = {
  343. .reg_off = HHI_MPLL_CNTL7,
  344. .shift = 16,
  345. .width = 9,
  346. },
  347. .ssen = {
  348. .reg_off = HHI_MPLL_CNTL,
  349. .shift = 25,
  350. .width = 1,
  351. },
  352. .lock = &meson_clk_lock,
  353. },
  354. .hw.init = &(struct clk_init_data){
  355. .name = "mpll0_div",
  356. .ops = &meson_clk_mpll_ops,
  357. .parent_names = (const char *[]){ "mpll_prediv" },
  358. .num_parents = 1,
  359. },
  360. };
  361. static struct clk_regmap meson8b_mpll0 = {
  362. .data = &(struct clk_regmap_gate_data){
  363. .offset = HHI_MPLL_CNTL7,
  364. .bit_idx = 14,
  365. },
  366. .hw.init = &(struct clk_init_data){
  367. .name = "mpll0",
  368. .ops = &clk_regmap_gate_ops,
  369. .parent_names = (const char *[]){ "mpll0_div" },
  370. .num_parents = 1,
  371. .flags = CLK_SET_RATE_PARENT,
  372. },
  373. };
  374. static struct clk_regmap meson8b_mpll1_div = {
  375. .data = &(struct meson_clk_mpll_data){
  376. .sdm = {
  377. .reg_off = HHI_MPLL_CNTL8,
  378. .shift = 0,
  379. .width = 14,
  380. },
  381. .sdm_en = {
  382. .reg_off = HHI_MPLL_CNTL8,
  383. .shift = 15,
  384. .width = 1,
  385. },
  386. .n2 = {
  387. .reg_off = HHI_MPLL_CNTL8,
  388. .shift = 16,
  389. .width = 9,
  390. },
  391. .lock = &meson_clk_lock,
  392. },
  393. .hw.init = &(struct clk_init_data){
  394. .name = "mpll1_div",
  395. .ops = &meson_clk_mpll_ops,
  396. .parent_names = (const char *[]){ "mpll_prediv" },
  397. .num_parents = 1,
  398. },
  399. };
  400. static struct clk_regmap meson8b_mpll1 = {
  401. .data = &(struct clk_regmap_gate_data){
  402. .offset = HHI_MPLL_CNTL8,
  403. .bit_idx = 14,
  404. },
  405. .hw.init = &(struct clk_init_data){
  406. .name = "mpll1",
  407. .ops = &clk_regmap_gate_ops,
  408. .parent_names = (const char *[]){ "mpll1_div" },
  409. .num_parents = 1,
  410. .flags = CLK_SET_RATE_PARENT,
  411. },
  412. };
  413. static struct clk_regmap meson8b_mpll2_div = {
  414. .data = &(struct meson_clk_mpll_data){
  415. .sdm = {
  416. .reg_off = HHI_MPLL_CNTL9,
  417. .shift = 0,
  418. .width = 14,
  419. },
  420. .sdm_en = {
  421. .reg_off = HHI_MPLL_CNTL9,
  422. .shift = 15,
  423. .width = 1,
  424. },
  425. .n2 = {
  426. .reg_off = HHI_MPLL_CNTL9,
  427. .shift = 16,
  428. .width = 9,
  429. },
  430. .lock = &meson_clk_lock,
  431. },
  432. .hw.init = &(struct clk_init_data){
  433. .name = "mpll2_div",
  434. .ops = &meson_clk_mpll_ops,
  435. .parent_names = (const char *[]){ "mpll_prediv" },
  436. .num_parents = 1,
  437. },
  438. };
  439. static struct clk_regmap meson8b_mpll2 = {
  440. .data = &(struct clk_regmap_gate_data){
  441. .offset = HHI_MPLL_CNTL9,
  442. .bit_idx = 14,
  443. },
  444. .hw.init = &(struct clk_init_data){
  445. .name = "mpll2",
  446. .ops = &clk_regmap_gate_ops,
  447. .parent_names = (const char *[]){ "mpll2_div" },
  448. .num_parents = 1,
  449. .flags = CLK_SET_RATE_PARENT,
  450. },
  451. };
  452. static u32 mux_table_clk81[] = { 6, 5, 7 };
  453. static struct clk_regmap meson8b_mpeg_clk_sel = {
  454. .data = &(struct clk_regmap_mux_data){
  455. .offset = HHI_MPEG_CLK_CNTL,
  456. .mask = 0x7,
  457. .shift = 12,
  458. .table = mux_table_clk81,
  459. },
  460. .hw.init = &(struct clk_init_data){
  461. .name = "mpeg_clk_sel",
  462. .ops = &clk_regmap_mux_ro_ops,
  463. /*
  464. * FIXME bits 14:12 selects from 8 possible parents:
  465. * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
  466. * fclk_div4, fclk_div3, fclk_div5
  467. */
  468. .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
  469. "fclk_div5" },
  470. .num_parents = 3,
  471. },
  472. };
  473. static struct clk_regmap meson8b_mpeg_clk_div = {
  474. .data = &(struct clk_regmap_div_data){
  475. .offset = HHI_MPEG_CLK_CNTL,
  476. .shift = 0,
  477. .width = 7,
  478. },
  479. .hw.init = &(struct clk_init_data){
  480. .name = "mpeg_clk_div",
  481. .ops = &clk_regmap_divider_ro_ops,
  482. .parent_names = (const char *[]){ "mpeg_clk_sel" },
  483. .num_parents = 1,
  484. },
  485. };
  486. static struct clk_regmap meson8b_clk81 = {
  487. .data = &(struct clk_regmap_gate_data){
  488. .offset = HHI_MPEG_CLK_CNTL,
  489. .bit_idx = 7,
  490. },
  491. .hw.init = &(struct clk_init_data){
  492. .name = "clk81",
  493. .ops = &clk_regmap_gate_ops,
  494. .parent_names = (const char *[]){ "mpeg_clk_div" },
  495. .num_parents = 1,
  496. .flags = CLK_IS_CRITICAL,
  497. },
  498. };
  499. static struct clk_regmap meson8b_cpu_in_sel = {
  500. .data = &(struct clk_regmap_mux_data){
  501. .offset = HHI_SYS_CPU_CLK_CNTL0,
  502. .mask = 0x1,
  503. .shift = 0,
  504. },
  505. .hw.init = &(struct clk_init_data){
  506. .name = "cpu_in_sel",
  507. .ops = &clk_regmap_mux_ro_ops,
  508. .parent_names = (const char *[]){ "xtal", "sys_pll" },
  509. .num_parents = 2,
  510. .flags = (CLK_SET_RATE_PARENT |
  511. CLK_SET_RATE_NO_REPARENT),
  512. },
  513. };
  514. static struct clk_fixed_factor meson8b_cpu_div2 = {
  515. .mult = 1,
  516. .div = 2,
  517. .hw.init = &(struct clk_init_data){
  518. .name = "cpu_div2",
  519. .ops = &clk_fixed_factor_ops,
  520. .parent_names = (const char *[]){ "cpu_in_sel" },
  521. .num_parents = 1,
  522. .flags = CLK_SET_RATE_PARENT,
  523. },
  524. };
  525. static struct clk_fixed_factor meson8b_cpu_div3 = {
  526. .mult = 1,
  527. .div = 3,
  528. .hw.init = &(struct clk_init_data){
  529. .name = "cpu_div3",
  530. .ops = &clk_fixed_factor_ops,
  531. .parent_names = (const char *[]){ "cpu_in_sel" },
  532. .num_parents = 1,
  533. .flags = CLK_SET_RATE_PARENT,
  534. },
  535. };
  536. static const struct clk_div_table cpu_scale_table[] = {
  537. { .val = 1, .div = 4 },
  538. { .val = 2, .div = 6 },
  539. { .val = 3, .div = 8 },
  540. { .val = 4, .div = 10 },
  541. { .val = 5, .div = 12 },
  542. { .val = 6, .div = 14 },
  543. { .val = 7, .div = 16 },
  544. { .val = 8, .div = 18 },
  545. { /* sentinel */ },
  546. };
  547. static struct clk_regmap meson8b_cpu_scale_div = {
  548. .data = &(struct clk_regmap_div_data){
  549. .offset = HHI_SYS_CPU_CLK_CNTL1,
  550. .shift = 20,
  551. .width = 10,
  552. .table = cpu_scale_table,
  553. .flags = CLK_DIVIDER_ALLOW_ZERO,
  554. },
  555. .hw.init = &(struct clk_init_data){
  556. .name = "cpu_scale_div",
  557. .ops = &clk_regmap_divider_ro_ops,
  558. .parent_names = (const char *[]){ "cpu_in_sel" },
  559. .num_parents = 1,
  560. .flags = CLK_SET_RATE_PARENT,
  561. },
  562. };
  563. static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
  564. static struct clk_regmap meson8b_cpu_scale_out_sel = {
  565. .data = &(struct clk_regmap_mux_data){
  566. .offset = HHI_SYS_CPU_CLK_CNTL0,
  567. .mask = 0x3,
  568. .shift = 2,
  569. .table = mux_table_cpu_scale_out_sel,
  570. },
  571. .hw.init = &(struct clk_init_data){
  572. .name = "cpu_scale_out_sel",
  573. .ops = &clk_regmap_mux_ro_ops,
  574. /*
  575. * NOTE: We are skipping the parent with value 0x2 (which is
  576. * "cpu_div3") because it results in a duty cycle of 33% which
  577. * makes the system unstable and can result in a lockup of the
  578. * whole system.
  579. */
  580. .parent_names = (const char *[]) { "cpu_in_sel",
  581. "cpu_div2",
  582. "cpu_scale_div" },
  583. .num_parents = 3,
  584. .flags = CLK_SET_RATE_PARENT,
  585. },
  586. };
  587. static struct clk_regmap meson8b_cpu_clk = {
  588. .data = &(struct clk_regmap_mux_data){
  589. .offset = HHI_SYS_CPU_CLK_CNTL0,
  590. .mask = 0x1,
  591. .shift = 7,
  592. },
  593. .hw.init = &(struct clk_init_data){
  594. .name = "cpu_clk",
  595. .ops = &clk_regmap_mux_ro_ops,
  596. .parent_names = (const char *[]){ "xtal",
  597. "cpu_scale_out_sel" },
  598. .num_parents = 2,
  599. .flags = (CLK_SET_RATE_PARENT |
  600. CLK_SET_RATE_NO_REPARENT |
  601. CLK_IS_CRITICAL),
  602. },
  603. };
  604. static struct clk_regmap meson8b_nand_clk_sel = {
  605. .data = &(struct clk_regmap_mux_data){
  606. .offset = HHI_NAND_CLK_CNTL,
  607. .mask = 0x7,
  608. .shift = 9,
  609. .flags = CLK_MUX_ROUND_CLOSEST,
  610. },
  611. .hw.init = &(struct clk_init_data){
  612. .name = "nand_clk_sel",
  613. .ops = &clk_regmap_mux_ops,
  614. /* FIXME all other parents are unknown: */
  615. .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
  616. "fclk_div5", "fclk_div7", "xtal" },
  617. .num_parents = 5,
  618. .flags = CLK_SET_RATE_PARENT,
  619. },
  620. };
  621. static struct clk_regmap meson8b_nand_clk_div = {
  622. .data = &(struct clk_regmap_div_data){
  623. .offset = HHI_NAND_CLK_CNTL,
  624. .shift = 0,
  625. .width = 7,
  626. .flags = CLK_DIVIDER_ROUND_CLOSEST,
  627. },
  628. .hw.init = &(struct clk_init_data){
  629. .name = "nand_clk_div",
  630. .ops = &clk_regmap_divider_ops,
  631. .parent_names = (const char *[]){ "nand_clk_sel" },
  632. .num_parents = 1,
  633. .flags = CLK_SET_RATE_PARENT,
  634. },
  635. };
  636. static struct clk_regmap meson8b_nand_clk_gate = {
  637. .data = &(struct clk_regmap_gate_data){
  638. .offset = HHI_NAND_CLK_CNTL,
  639. .bit_idx = 8,
  640. },
  641. .hw.init = &(struct clk_init_data){
  642. .name = "nand_clk_gate",
  643. .ops = &clk_regmap_gate_ops,
  644. .parent_names = (const char *[]){ "nand_clk_div" },
  645. .num_parents = 1,
  646. .flags = CLK_SET_RATE_PARENT,
  647. },
  648. };
  649. /* Everything Else (EE) domain gates */
  650. static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
  651. static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
  652. static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
  653. static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
  654. static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
  655. static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
  656. static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
  657. static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
  658. static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
  659. static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
  660. static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
  661. static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
  662. static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
  663. static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
  664. static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
  665. static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
  666. static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
  667. static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
  668. static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
  669. static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
  670. static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
  671. static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
  672. static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
  673. static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
  674. static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
  675. static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
  676. static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
  677. static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
  678. static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
  679. static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
  680. static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
  681. static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
  682. static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
  683. static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
  684. static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
  685. static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
  686. static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
  687. static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
  688. static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
  689. static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
  690. static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
  691. static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
  692. static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
  693. static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
  694. static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
  695. static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
  696. static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
  697. static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
  698. static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
  699. static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
  700. static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
  701. static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
  702. static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
  703. static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
  704. static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
  705. static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
  706. static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
  707. static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
  708. static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
  709. static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
  710. static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
  711. static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
  712. static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
  713. static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
  714. static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
  715. static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
  716. static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
  717. static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
  718. static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
  719. static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
  720. static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
  721. static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
  722. static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
  723. /* Always On (AO) domain gates */
  724. static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
  725. static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
  726. static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
  727. static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
  728. static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
  729. .hws = {
  730. [CLKID_XTAL] = &meson8b_xtal.hw,
  731. [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
  732. [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
  733. [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
  734. [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
  735. [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
  736. [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
  737. [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
  738. [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
  739. [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
  740. [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
  741. [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
  742. [CLKID_CLK81] = &meson8b_clk81.hw,
  743. [CLKID_DDR] = &meson8b_ddr.hw,
  744. [CLKID_DOS] = &meson8b_dos.hw,
  745. [CLKID_ISA] = &meson8b_isa.hw,
  746. [CLKID_PL301] = &meson8b_pl301.hw,
  747. [CLKID_PERIPHS] = &meson8b_periphs.hw,
  748. [CLKID_SPICC] = &meson8b_spicc.hw,
  749. [CLKID_I2C] = &meson8b_i2c.hw,
  750. [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
  751. [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
  752. [CLKID_RNG0] = &meson8b_rng0.hw,
  753. [CLKID_UART0] = &meson8b_uart0.hw,
  754. [CLKID_SDHC] = &meson8b_sdhc.hw,
  755. [CLKID_STREAM] = &meson8b_stream.hw,
  756. [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
  757. [CLKID_SDIO] = &meson8b_sdio.hw,
  758. [CLKID_ABUF] = &meson8b_abuf.hw,
  759. [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
  760. [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
  761. [CLKID_SPI] = &meson8b_spi.hw,
  762. [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
  763. [CLKID_ETH] = &meson8b_eth.hw,
  764. [CLKID_DEMUX] = &meson8b_demux.hw,
  765. [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
  766. [CLKID_IEC958] = &meson8b_iec958.hw,
  767. [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
  768. [CLKID_AMCLK] = &meson8b_amclk.hw,
  769. [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
  770. [CLKID_MIXER] = &meson8b_mixer.hw,
  771. [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
  772. [CLKID_ADC] = &meson8b_adc.hw,
  773. [CLKID_BLKMV] = &meson8b_blkmv.hw,
  774. [CLKID_AIU] = &meson8b_aiu.hw,
  775. [CLKID_UART1] = &meson8b_uart1.hw,
  776. [CLKID_G2D] = &meson8b_g2d.hw,
  777. [CLKID_USB0] = &meson8b_usb0.hw,
  778. [CLKID_USB1] = &meson8b_usb1.hw,
  779. [CLKID_RESET] = &meson8b_reset.hw,
  780. [CLKID_NAND] = &meson8b_nand.hw,
  781. [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
  782. [CLKID_USB] = &meson8b_usb.hw,
  783. [CLKID_VDIN1] = &meson8b_vdin1.hw,
  784. [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
  785. [CLKID_EFUSE] = &meson8b_efuse.hw,
  786. [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
  787. [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
  788. [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
  789. [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
  790. [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
  791. [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
  792. [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
  793. [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
  794. [CLKID_DVIN] = &meson8b_dvin.hw,
  795. [CLKID_UART2] = &meson8b_uart2.hw,
  796. [CLKID_SANA] = &meson8b_sana.hw,
  797. [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
  798. [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
  799. [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
  800. [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
  801. [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
  802. [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
  803. [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
  804. [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
  805. [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
  806. [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
  807. [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
  808. [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
  809. [CLKID_ENC480P] = &meson8b_enc480p.hw,
  810. [CLKID_RNG1] = &meson8b_rng1.hw,
  811. [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
  812. [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
  813. [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
  814. [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
  815. [CLKID_EDP] = &meson8b_edp.hw,
  816. [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
  817. [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
  818. [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
  819. [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
  820. [CLKID_MPLL0] = &meson8b_mpll0.hw,
  821. [CLKID_MPLL1] = &meson8b_mpll1.hw,
  822. [CLKID_MPLL2] = &meson8b_mpll2.hw,
  823. [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
  824. [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
  825. [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
  826. [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
  827. [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw,
  828. [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw,
  829. [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
  830. [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
  831. [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
  832. [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
  833. [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
  834. [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
  835. [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
  836. [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
  837. [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
  838. [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
  839. [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
  840. [CLK_NR_CLKS] = NULL,
  841. },
  842. .num = CLK_NR_CLKS,
  843. };
  844. static struct clk_regmap *const meson8b_clk_regmaps[] = {
  845. &meson8b_clk81,
  846. &meson8b_ddr,
  847. &meson8b_dos,
  848. &meson8b_isa,
  849. &meson8b_pl301,
  850. &meson8b_periphs,
  851. &meson8b_spicc,
  852. &meson8b_i2c,
  853. &meson8b_sar_adc,
  854. &meson8b_smart_card,
  855. &meson8b_rng0,
  856. &meson8b_uart0,
  857. &meson8b_sdhc,
  858. &meson8b_stream,
  859. &meson8b_async_fifo,
  860. &meson8b_sdio,
  861. &meson8b_abuf,
  862. &meson8b_hiu_iface,
  863. &meson8b_assist_misc,
  864. &meson8b_spi,
  865. &meson8b_i2s_spdif,
  866. &meson8b_eth,
  867. &meson8b_demux,
  868. &meson8b_aiu_glue,
  869. &meson8b_iec958,
  870. &meson8b_i2s_out,
  871. &meson8b_amclk,
  872. &meson8b_aififo2,
  873. &meson8b_mixer,
  874. &meson8b_mixer_iface,
  875. &meson8b_adc,
  876. &meson8b_blkmv,
  877. &meson8b_aiu,
  878. &meson8b_uart1,
  879. &meson8b_g2d,
  880. &meson8b_usb0,
  881. &meson8b_usb1,
  882. &meson8b_reset,
  883. &meson8b_nand,
  884. &meson8b_dos_parser,
  885. &meson8b_usb,
  886. &meson8b_vdin1,
  887. &meson8b_ahb_arb0,
  888. &meson8b_efuse,
  889. &meson8b_boot_rom,
  890. &meson8b_ahb_data_bus,
  891. &meson8b_ahb_ctrl_bus,
  892. &meson8b_hdmi_intr_sync,
  893. &meson8b_hdmi_pclk,
  894. &meson8b_usb1_ddr_bridge,
  895. &meson8b_usb0_ddr_bridge,
  896. &meson8b_mmc_pclk,
  897. &meson8b_dvin,
  898. &meson8b_uart2,
  899. &meson8b_sana,
  900. &meson8b_vpu_intr,
  901. &meson8b_sec_ahb_ahb3_bridge,
  902. &meson8b_clk81_a9,
  903. &meson8b_vclk2_venci0,
  904. &meson8b_vclk2_venci1,
  905. &meson8b_vclk2_vencp0,
  906. &meson8b_vclk2_vencp1,
  907. &meson8b_gclk_venci_int,
  908. &meson8b_gclk_vencp_int,
  909. &meson8b_dac_clk,
  910. &meson8b_aoclk_gate,
  911. &meson8b_iec958_gate,
  912. &meson8b_enc480p,
  913. &meson8b_rng1,
  914. &meson8b_gclk_vencl_int,
  915. &meson8b_vclk2_venclmcc,
  916. &meson8b_vclk2_vencl,
  917. &meson8b_vclk2_other,
  918. &meson8b_edp,
  919. &meson8b_ao_media_cpu,
  920. &meson8b_ao_ahb_sram,
  921. &meson8b_ao_ahb_bus,
  922. &meson8b_ao_iface,
  923. &meson8b_mpeg_clk_div,
  924. &meson8b_mpeg_clk_sel,
  925. &meson8b_mpll0,
  926. &meson8b_mpll1,
  927. &meson8b_mpll2,
  928. &meson8b_mpll0_div,
  929. &meson8b_mpll1_div,
  930. &meson8b_mpll2_div,
  931. &meson8b_fixed_pll,
  932. &meson8b_vid_pll,
  933. &meson8b_sys_pll,
  934. &meson8b_cpu_in_sel,
  935. &meson8b_cpu_scale_div,
  936. &meson8b_cpu_scale_out_sel,
  937. &meson8b_cpu_clk,
  938. &meson8b_mpll_prediv,
  939. &meson8b_fclk_div2,
  940. &meson8b_fclk_div3,
  941. &meson8b_fclk_div4,
  942. &meson8b_fclk_div5,
  943. &meson8b_fclk_div7,
  944. &meson8b_nand_clk_sel,
  945. &meson8b_nand_clk_div,
  946. &meson8b_nand_clk_gate,
  947. };
  948. static const struct meson8b_clk_reset_line {
  949. u32 reg;
  950. u8 bit_idx;
  951. } meson8b_clk_reset_bits[] = {
  952. [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
  953. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
  954. },
  955. [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
  956. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
  957. },
  958. [CLKC_RESET_SCU_SOFT_RESET] = {
  959. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
  960. },
  961. [CLKC_RESET_CPU3_SOFT_RESET] = {
  962. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
  963. },
  964. [CLKC_RESET_CPU2_SOFT_RESET] = {
  965. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
  966. },
  967. [CLKC_RESET_CPU1_SOFT_RESET] = {
  968. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
  969. },
  970. [CLKC_RESET_CPU0_SOFT_RESET] = {
  971. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
  972. },
  973. [CLKC_RESET_A5_GLOBAL_RESET] = {
  974. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
  975. },
  976. [CLKC_RESET_A5_AXI_SOFT_RESET] = {
  977. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
  978. },
  979. [CLKC_RESET_A5_ABP_SOFT_RESET] = {
  980. .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
  981. },
  982. [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
  983. .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
  984. },
  985. [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
  986. .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
  987. },
  988. [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
  989. .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
  990. },
  991. [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
  992. .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
  993. },
  994. [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
  995. .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
  996. },
  997. [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
  998. .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
  999. },
  1000. };
  1001. static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
  1002. unsigned long id, bool assert)
  1003. {
  1004. struct meson8b_clk_reset *meson8b_clk_reset =
  1005. container_of(rcdev, struct meson8b_clk_reset, reset);
  1006. unsigned long flags;
  1007. const struct meson8b_clk_reset_line *reset;
  1008. u32 val;
  1009. if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
  1010. return -EINVAL;
  1011. reset = &meson8b_clk_reset_bits[id];
  1012. spin_lock_irqsave(&meson_clk_lock, flags);
  1013. val = readl(meson8b_clk_reset->base + reset->reg);
  1014. if (assert)
  1015. val |= BIT(reset->bit_idx);
  1016. else
  1017. val &= ~BIT(reset->bit_idx);
  1018. writel(val, meson8b_clk_reset->base + reset->reg);
  1019. spin_unlock_irqrestore(&meson_clk_lock, flags);
  1020. return 0;
  1021. }
  1022. static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
  1023. unsigned long id)
  1024. {
  1025. return meson8b_clk_reset_update(rcdev, id, true);
  1026. }
  1027. static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
  1028. unsigned long id)
  1029. {
  1030. return meson8b_clk_reset_update(rcdev, id, false);
  1031. }
  1032. static const struct reset_control_ops meson8b_clk_reset_ops = {
  1033. .assert = meson8b_clk_reset_assert,
  1034. .deassert = meson8b_clk_reset_deassert,
  1035. };
  1036. static const struct regmap_config clkc_regmap_config = {
  1037. .reg_bits = 32,
  1038. .val_bits = 32,
  1039. .reg_stride = 4,
  1040. };
  1041. static int meson8b_clkc_probe(struct platform_device *pdev)
  1042. {
  1043. int ret, i;
  1044. struct device *dev = &pdev->dev;
  1045. struct regmap *map;
  1046. if (!clk_base)
  1047. return -ENXIO;
  1048. map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config);
  1049. if (IS_ERR(map))
  1050. return PTR_ERR(map);
  1051. /* Populate regmap for the regmap backed clocks */
  1052. for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
  1053. meson8b_clk_regmaps[i]->map = map;
  1054. /*
  1055. * register all clks
  1056. * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
  1057. */
  1058. for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
  1059. /* array might be sparse */
  1060. if (!meson8b_hw_onecell_data.hws[i])
  1061. continue;
  1062. ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]);
  1063. if (ret)
  1064. return ret;
  1065. }
  1066. return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
  1067. &meson8b_hw_onecell_data);
  1068. }
  1069. static const struct of_device_id meson8b_clkc_match_table[] = {
  1070. { .compatible = "amlogic,meson8-clkc" },
  1071. { .compatible = "amlogic,meson8b-clkc" },
  1072. { .compatible = "amlogic,meson8m2-clkc" },
  1073. { }
  1074. };
  1075. static struct platform_driver meson8b_driver = {
  1076. .probe = meson8b_clkc_probe,
  1077. .driver = {
  1078. .name = "meson8b-clkc",
  1079. .of_match_table = meson8b_clkc_match_table,
  1080. },
  1081. };
  1082. builtin_platform_driver(meson8b_driver);
  1083. static void __init meson8b_clkc_reset_init(struct device_node *np)
  1084. {
  1085. struct meson8b_clk_reset *rstc;
  1086. int ret;
  1087. /* Generic clocks, PLLs and some of the reset-bits */
  1088. clk_base = of_iomap(np, 1);
  1089. if (!clk_base) {
  1090. pr_err("%s: Unable to map clk base\n", __func__);
  1091. return;
  1092. }
  1093. rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
  1094. if (!rstc)
  1095. return;
  1096. /* Reset Controller */
  1097. rstc->base = clk_base;
  1098. rstc->reset.ops = &meson8b_clk_reset_ops;
  1099. rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
  1100. rstc->reset.of_node = np;
  1101. ret = reset_controller_register(&rstc->reset);
  1102. if (ret) {
  1103. pr_err("%s: Failed to register clkc reset controller: %d\n",
  1104. __func__, ret);
  1105. return;
  1106. }
  1107. }
  1108. CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
  1109. meson8b_clkc_reset_init);
  1110. CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
  1111. meson8b_clkc_reset_init);
  1112. CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
  1113. meson8b_clkc_reset_init);