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linux-arkmicro
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clk
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meson
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meson8b.h

meson8b.h 3.3 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2015 Endless Mobile, Inc.
    4. 

  4.  * Author: Carlo Caione <carlo@endlessm.com>
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2016 BayLibre, Inc.
    7. 

  7.  * Michael Turquette <mturquette@baylibre.com>
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __MESON8B_H
    11. 

  11. #define __MESON8B_H
    12. 

  12. 

  13. /*
    14. 

  14.  * Clock controller register offsets
    15. 

  15.  *
    16. 

  16.  * Register offsets from the HardKernel[0] data sheet are listed in comment
    17. 

  17.  * blocks below. Those offsets must be multiplied by 4 before adding them to
    18. 

  18.  * the base address to get the right value
    19. 

  19.  *
    20. 

  20.  * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
    21. 

  21.  */
    22. 

  22. #define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
    23. 

  23. #define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
    24. 

  24. #define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
    25. 

  25. #define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
    26. 

  26. #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
    27. 

  27. #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
    28. 

  28. #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
    29. 

  29. #define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
    30. 

  30. #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
    31. 

  31. #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
    32. 

  32. #define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
    33. 

  33. #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
    34. 

  34. #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
    35. 

  35. #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
    36. 

  36. 

  37. /*
    38. 

  38.  * MPLL register offeset taken from the S905 datasheet. Vendor kernel source
    39. 

  39.  * confirm these are the same for the S805.
    40. 

  40.  */
    41. 

  41. #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
    42. 

  42. #define HHI_MPLL_CNTL2			0x284 /* 0xa1 offset in data sheet */
    43. 

  43. #define HHI_MPLL_CNTL3			0x288 /* 0xa2 offset in data sheet */
    44. 

  44. #define HHI_MPLL_CNTL4			0x28C /* 0xa3 offset in data sheet */
    45. 

  45. #define HHI_MPLL_CNTL5			0x290 /* 0xa4 offset in data sheet */
    46. 

  46. #define HHI_MPLL_CNTL6			0x294 /* 0xa5 offset in data sheet */
    47. 

  47. #define HHI_MPLL_CNTL7			0x298 /* 0xa6 offset in data sheet */
    48. 

  48. #define HHI_MPLL_CNTL8			0x29C /* 0xa7 offset in data sheet */
    49. 

  49. #define HHI_MPLL_CNTL9			0x2A0 /* 0xa8 offset in data sheet */
    50. 

  50. #define HHI_MPLL_CNTL10			0x2A4 /* 0xa9 offset in data sheet */
    51. 

  51. 

  52. /*
    53. 

  53.  * CLKID index values
    54. 

  54.  *
    55. 

  55.  * These indices are entirely contrived and do not map onto the hardware.
    56. 

  56.  * It has now been decided to expose everything by default in the DT header:
    57. 

  57.  * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
    58. 

  58.  * to expose, such as the internal muxes and dividers of composite clocks,
    59. 

  59.  * will remain defined here.
    60. 

  60.  */
    61. 

  61. 

  62. #define CLKID_MPLL0_DIV		96
    63. 

  63. #define CLKID_MPLL1_DIV		97
    64. 

  64. #define CLKID_MPLL2_DIV		98
    65. 

  65. #define CLKID_CPU_IN_SEL	99
    66. 

  66. #define CLKID_CPU_DIV2		100
    67. 

  67. #define CLKID_CPU_DIV3		101
    68. 

  68. #define CLKID_CPU_SCALE_DIV	102
    69. 

  69. #define CLKID_CPU_SCALE_OUT_SEL	103
    70. 

  70. #define CLKID_MPLL_PREDIV	104
    71. 

  71. #define CLKID_FCLK_DIV2_DIV	105
    72. 

  72. #define CLKID_FCLK_DIV3_DIV	106
    73. 

  73. #define CLKID_FCLK_DIV4_DIV	107
    74. 

  74. #define CLKID_FCLK_DIV5_DIV	108
    75. 

  75. #define CLKID_FCLK_DIV7_DIV	109
    76. 

  76. #define CLKID_NAND_SEL		110
    77. 

  77. #define CLKID_NAND_DIV		111
    78. 

  78. 

  79. #define CLK_NR_CLKS		113
    80. 

  80. 

  81. /*
    82. 

  82.  * include the CLKID and RESETID that have
    83. 

  83.  * been made part of the stable DT binding
    84. 

  84.  */
    85. 

  85. #include <dt-bindings/clock/meson8b-clkc.h>
    86. 

  86. #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
    87. 

  87. 

  88. #endif /* __MESON8B_H */
    89.