sclk-div.c 5.7 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (c) 2018 BayLibre, SAS.
  4. * Author: Jerome Brunet <jbrunet@baylibre.com>
  5. *
  6. * Sample clock generator divider:
  7. * This HW divider gates with value 0 but is otherwise a zero based divider:
  8. *
  9. * val >= 1
  10. * divider = val + 1
  11. *
  12. * The duty cycle may also be set for the LR clock variant. The duty cycle
  13. * ratio is:
  14. *
  15. * hi = [0 - val]
  16. * duty_cycle = (1 + hi) / (1 + val)
  17. */
  18. #include "clkc-audio.h"
  19. static inline struct meson_sclk_div_data *
  20. meson_sclk_div_data(struct clk_regmap *clk)
  21. {
  22. return (struct meson_sclk_div_data *)clk->data;
  23. }
  24. static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
  25. {
  26. return (1 << sclk->div.width) - 1;
  27. }
  28. static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
  29. {
  30. return sclk_div_maxval(sclk) + 1;
  31. }
  32. static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
  33. unsigned long prate, int maxdiv)
  34. {
  35. int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
  36. return clamp(div, 2, maxdiv);
  37. }
  38. static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
  39. unsigned long *prate,
  40. struct meson_sclk_div_data *sclk)
  41. {
  42. struct clk_hw *parent = clk_hw_get_parent(hw);
  43. int bestdiv = 0, i;
  44. unsigned long maxdiv, now, parent_now;
  45. unsigned long best = 0, best_parent = 0;
  46. if (!rate)
  47. rate = 1;
  48. maxdiv = sclk_div_maxdiv(sclk);
  49. if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))
  50. return sclk_div_getdiv(hw, rate, *prate, maxdiv);
  51. /*
  52. * The maximum divider we can use without overflowing
  53. * unsigned long in rate * i below
  54. */
  55. maxdiv = min(ULONG_MAX / rate, maxdiv);
  56. for (i = 2; i <= maxdiv; i++) {
  57. /*
  58. * It's the most ideal case if the requested rate can be
  59. * divided from parent clock without needing to change
  60. * parent rate, so return the divider immediately.
  61. */
  62. if (rate * i == *prate)
  63. return i;
  64. parent_now = clk_hw_round_rate(parent, rate * i);
  65. now = DIV_ROUND_UP_ULL((u64)parent_now, i);
  66. if (abs(rate - now) < abs(rate - best)) {
  67. bestdiv = i;
  68. best = now;
  69. best_parent = parent_now;
  70. }
  71. }
  72. if (!bestdiv)
  73. bestdiv = sclk_div_maxdiv(sclk);
  74. else
  75. *prate = best_parent;
  76. return bestdiv;
  77. }
  78. static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate,
  79. unsigned long *prate)
  80. {
  81. struct clk_regmap *clk = to_clk_regmap(hw);
  82. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  83. int div;
  84. div = sclk_div_bestdiv(hw, rate, prate, sclk);
  85. return DIV_ROUND_UP_ULL((u64)*prate, div);
  86. }
  87. static void sclk_apply_ratio(struct clk_regmap *clk,
  88. struct meson_sclk_div_data *sclk)
  89. {
  90. unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div *
  91. sclk->cached_duty.num,
  92. sclk->cached_duty.den);
  93. if (hi)
  94. hi -= 1;
  95. meson_parm_write(clk->map, &sclk->hi, hi);
  96. }
  97. static int sclk_div_set_duty_cycle(struct clk_hw *hw,
  98. struct clk_duty *duty)
  99. {
  100. struct clk_regmap *clk = to_clk_regmap(hw);
  101. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  102. if (MESON_PARM_APPLICABLE(&sclk->hi)) {
  103. memcpy(&sclk->cached_duty, duty, sizeof(*duty));
  104. sclk_apply_ratio(clk, sclk);
  105. }
  106. return 0;
  107. }
  108. static int sclk_div_get_duty_cycle(struct clk_hw *hw,
  109. struct clk_duty *duty)
  110. {
  111. struct clk_regmap *clk = to_clk_regmap(hw);
  112. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  113. int hi;
  114. if (!MESON_PARM_APPLICABLE(&sclk->hi)) {
  115. duty->num = 1;
  116. duty->den = 2;
  117. return 0;
  118. }
  119. hi = meson_parm_read(clk->map, &sclk->hi);
  120. duty->num = hi + 1;
  121. duty->den = sclk->cached_div;
  122. return 0;
  123. }
  124. static void sclk_apply_divider(struct clk_regmap *clk,
  125. struct meson_sclk_div_data *sclk)
  126. {
  127. if (MESON_PARM_APPLICABLE(&sclk->hi))
  128. sclk_apply_ratio(clk, sclk);
  129. meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1);
  130. }
  131. static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
  132. unsigned long prate)
  133. {
  134. struct clk_regmap *clk = to_clk_regmap(hw);
  135. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  136. unsigned long maxdiv = sclk_div_maxdiv(sclk);
  137. sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
  138. if (clk_hw_is_enabled(hw))
  139. sclk_apply_divider(clk, sclk);
  140. return 0;
  141. }
  142. static unsigned long sclk_div_recalc_rate(struct clk_hw *hw,
  143. unsigned long prate)
  144. {
  145. struct clk_regmap *clk = to_clk_regmap(hw);
  146. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  147. return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div);
  148. }
  149. static int sclk_div_enable(struct clk_hw *hw)
  150. {
  151. struct clk_regmap *clk = to_clk_regmap(hw);
  152. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  153. sclk_apply_divider(clk, sclk);
  154. return 0;
  155. }
  156. static void sclk_div_disable(struct clk_hw *hw)
  157. {
  158. struct clk_regmap *clk = to_clk_regmap(hw);
  159. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  160. meson_parm_write(clk->map, &sclk->div, 0);
  161. }
  162. static int sclk_div_is_enabled(struct clk_hw *hw)
  163. {
  164. struct clk_regmap *clk = to_clk_regmap(hw);
  165. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  166. if (meson_parm_read(clk->map, &sclk->div))
  167. return 1;
  168. return 0;
  169. }
  170. static void sclk_div_init(struct clk_hw *hw)
  171. {
  172. struct clk_regmap *clk = to_clk_regmap(hw);
  173. struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
  174. unsigned int val;
  175. val = meson_parm_read(clk->map, &sclk->div);
  176. /* if the divider is initially disabled, assume max */
  177. if (!val)
  178. sclk->cached_div = sclk_div_maxdiv(sclk);
  179. else
  180. sclk->cached_div = val + 1;
  181. sclk_div_get_duty_cycle(hw, &sclk->cached_duty);
  182. }
  183. const struct clk_ops meson_sclk_div_ops = {
  184. .recalc_rate = sclk_div_recalc_rate,
  185. .round_rate = sclk_div_round_rate,
  186. .set_rate = sclk_div_set_rate,
  187. .enable = sclk_div_enable,
  188. .disable = sclk_div_disable,
  189. .is_enabled = sclk_div_is_enabled,
  190. .get_duty_cycle = sclk_div_get_duty_cycle,
  191. .set_duty_cycle = sclk_div_set_duty_cycle,
  192. .init = sclk_div_init,
  193. };
  194. EXPORT_SYMBOL_GPL(meson_sclk_div_ops);