gdsc.h 2.4 KB

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  1. /*
  2. * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef __QCOM_GDSC_H__
  14. #define __QCOM_GDSC_H__
  15. #include <linux/err.h>
  16. #include <linux/pm_domain.h>
  17. struct regmap;
  18. struct reset_controller_dev;
  19. /**
  20. * struct gdsc - Globally Distributed Switch Controller
  21. * @pd: generic power domain
  22. * @regmap: regmap for MMIO accesses
  23. * @gdscr: gsdc control register
  24. * @gds_hw_ctrl: gds_hw_ctrl register
  25. * @cxcs: offsets of branch registers to toggle mem/periph bits in
  26. * @cxc_count: number of @cxcs
  27. * @pwrsts: Possible powerdomain power states
  28. * @resets: ids of resets associated with this gdsc
  29. * @reset_count: number of @resets
  30. * @rcdev: reset controller
  31. */
  32. struct gdsc {
  33. struct generic_pm_domain pd;
  34. struct generic_pm_domain *parent;
  35. struct regmap *regmap;
  36. unsigned int gdscr;
  37. unsigned int gds_hw_ctrl;
  38. unsigned int clamp_io_ctrl;
  39. unsigned int *cxcs;
  40. unsigned int cxc_count;
  41. const u8 pwrsts;
  42. /* Powerdomain allowable state bitfields */
  43. #define PWRSTS_OFF BIT(0)
  44. #define PWRSTS_RET BIT(1)
  45. #define PWRSTS_ON BIT(2)
  46. #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
  47. #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
  48. const u8 flags;
  49. #define VOTABLE BIT(0)
  50. #define CLAMP_IO BIT(1)
  51. #define HW_CTRL BIT(2)
  52. #define SW_RESET BIT(3)
  53. #define AON_RESET BIT(4)
  54. #define POLL_CFG_GDSCR BIT(5)
  55. #define ALWAYS_ON BIT(6)
  56. struct reset_controller_dev *rcdev;
  57. unsigned int *resets;
  58. unsigned int reset_count;
  59. };
  60. struct gdsc_desc {
  61. struct device *dev;
  62. struct gdsc **scs;
  63. size_t num;
  64. };
  65. #ifdef CONFIG_QCOM_GDSC
  66. int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
  67. struct regmap *);
  68. void gdsc_unregister(struct gdsc_desc *desc);
  69. #else
  70. static inline int gdsc_register(struct gdsc_desc *desc,
  71. struct reset_controller_dev *rcdev,
  72. struct regmap *r)
  73. {
  74. return -ENOSYS;
  75. }
  76. static inline void gdsc_unregister(struct gdsc_desc *desc) {};
  77. #endif /* CONFIG_QCOM_GDSC */
  78. #endif /* __QCOM_GDSC_H__ */