clk-pmc-atom.c 9.2 KB

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  1. /*
  2. * Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
  3. *
  4. * Copyright (C) 2016, Intel Corporation
  5. * Author: Irina Tirdea <irina.tirdea@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. */
  16. #include <linux/clk-provider.h>
  17. #include <linux/clkdev.h>
  18. #include <linux/err.h>
  19. #include <linux/platform_data/x86/clk-pmc-atom.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #define PLT_CLK_NAME_BASE "pmc_plt_clk"
  23. #define PMC_CLK_CTL_OFFSET 0x60
  24. #define PMC_CLK_CTL_SIZE 4
  25. #define PMC_CLK_NUM 6
  26. #define PMC_CLK_CTL_GATED_ON_D3 0x0
  27. #define PMC_CLK_CTL_FORCE_ON 0x1
  28. #define PMC_CLK_CTL_FORCE_OFF 0x2
  29. #define PMC_CLK_CTL_RESERVED 0x3
  30. #define PMC_MASK_CLK_CTL GENMASK(1, 0)
  31. #define PMC_MASK_CLK_FREQ BIT(2)
  32. #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
  33. #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
  34. struct clk_plt_fixed {
  35. struct clk_hw *clk;
  36. struct clk_lookup *lookup;
  37. };
  38. struct clk_plt {
  39. struct clk_hw hw;
  40. void __iomem *reg;
  41. struct clk_lookup *lookup;
  42. /* protect access to PMC registers */
  43. spinlock_t lock;
  44. };
  45. #define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
  46. struct clk_plt_data {
  47. struct clk_plt_fixed **parents;
  48. u8 nparents;
  49. struct clk_plt *clks[PMC_CLK_NUM];
  50. struct clk_lookup *mclk_lookup;
  51. struct clk_lookup *ether_clk_lookup;
  52. };
  53. /* Return an index in parent table */
  54. static inline int plt_reg_to_parent(int reg)
  55. {
  56. switch (reg & PMC_MASK_CLK_FREQ) {
  57. default:
  58. case PMC_CLK_FREQ_XTAL:
  59. return 0;
  60. case PMC_CLK_FREQ_PLL:
  61. return 1;
  62. }
  63. }
  64. /* Return clk index of parent */
  65. static inline int plt_parent_to_reg(int index)
  66. {
  67. switch (index) {
  68. default:
  69. case 0:
  70. return PMC_CLK_FREQ_XTAL;
  71. case 1:
  72. return PMC_CLK_FREQ_PLL;
  73. }
  74. }
  75. /* Abstract status in simpler enabled/disabled value */
  76. static inline int plt_reg_to_enabled(int reg)
  77. {
  78. switch (reg & PMC_MASK_CLK_CTL) {
  79. case PMC_CLK_CTL_GATED_ON_D3:
  80. case PMC_CLK_CTL_FORCE_ON:
  81. return 1; /* enabled */
  82. case PMC_CLK_CTL_FORCE_OFF:
  83. case PMC_CLK_CTL_RESERVED:
  84. default:
  85. return 0; /* disabled */
  86. }
  87. }
  88. static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
  89. {
  90. u32 tmp;
  91. unsigned long flags;
  92. spin_lock_irqsave(&clk->lock, flags);
  93. tmp = readl(clk->reg);
  94. tmp = (tmp & ~mask) | (val & mask);
  95. writel(tmp, clk->reg);
  96. spin_unlock_irqrestore(&clk->lock, flags);
  97. }
  98. static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
  99. {
  100. struct clk_plt *clk = to_clk_plt(hw);
  101. plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
  102. return 0;
  103. }
  104. static u8 plt_clk_get_parent(struct clk_hw *hw)
  105. {
  106. struct clk_plt *clk = to_clk_plt(hw);
  107. u32 value;
  108. value = readl(clk->reg);
  109. return plt_reg_to_parent(value);
  110. }
  111. static int plt_clk_enable(struct clk_hw *hw)
  112. {
  113. struct clk_plt *clk = to_clk_plt(hw);
  114. plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
  115. return 0;
  116. }
  117. static void plt_clk_disable(struct clk_hw *hw)
  118. {
  119. struct clk_plt *clk = to_clk_plt(hw);
  120. plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
  121. }
  122. static int plt_clk_is_enabled(struct clk_hw *hw)
  123. {
  124. struct clk_plt *clk = to_clk_plt(hw);
  125. u32 value;
  126. value = readl(clk->reg);
  127. return plt_reg_to_enabled(value);
  128. }
  129. static const struct clk_ops plt_clk_ops = {
  130. .enable = plt_clk_enable,
  131. .disable = plt_clk_disable,
  132. .is_enabled = plt_clk_is_enabled,
  133. .get_parent = plt_clk_get_parent,
  134. .set_parent = plt_clk_set_parent,
  135. .determine_rate = __clk_mux_determine_rate,
  136. };
  137. static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
  138. const struct pmc_clk_data *pmc_data,
  139. const char **parent_names,
  140. int num_parents)
  141. {
  142. struct clk_plt *pclk;
  143. struct clk_init_data init;
  144. int ret;
  145. pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
  146. if (!pclk)
  147. return ERR_PTR(-ENOMEM);
  148. init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
  149. init.ops = &plt_clk_ops;
  150. init.flags = 0;
  151. init.parent_names = parent_names;
  152. init.num_parents = num_parents;
  153. pclk->hw.init = &init;
  154. pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
  155. spin_lock_init(&pclk->lock);
  156. /*
  157. * On some systems, the pmc_plt_clocks already enabled by the
  158. * firmware are being marked as critical to avoid them being
  159. * gated by the clock framework.
  160. */
  161. if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw))
  162. init.flags |= CLK_IS_CRITICAL;
  163. ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
  164. if (ret) {
  165. pclk = ERR_PTR(ret);
  166. goto err_free_init;
  167. }
  168. pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
  169. if (!pclk->lookup) {
  170. pclk = ERR_PTR(-ENOMEM);
  171. goto err_free_init;
  172. }
  173. err_free_init:
  174. kfree(init.name);
  175. return pclk;
  176. }
  177. static void plt_clk_unregister(struct clk_plt *pclk)
  178. {
  179. clkdev_drop(pclk->lookup);
  180. }
  181. static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
  182. const char *name,
  183. const char *parent_name,
  184. unsigned long fixed_rate)
  185. {
  186. struct clk_plt_fixed *pclk;
  187. pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
  188. if (!pclk)
  189. return ERR_PTR(-ENOMEM);
  190. pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
  191. 0, fixed_rate);
  192. if (IS_ERR(pclk->clk))
  193. return ERR_CAST(pclk->clk);
  194. pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
  195. if (!pclk->lookup) {
  196. clk_hw_unregister_fixed_rate(pclk->clk);
  197. return ERR_PTR(-ENOMEM);
  198. }
  199. return pclk;
  200. }
  201. static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
  202. {
  203. clkdev_drop(pclk->lookup);
  204. clk_hw_unregister_fixed_rate(pclk->clk);
  205. }
  206. static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
  207. unsigned int i)
  208. {
  209. while (i--)
  210. plt_clk_unregister_fixed_rate(data->parents[i]);
  211. }
  212. static void plt_clk_free_parent_names_loop(const char **parent_names,
  213. unsigned int i)
  214. {
  215. while (i--)
  216. kfree_const(parent_names[i]);
  217. kfree(parent_names);
  218. }
  219. static void plt_clk_unregister_loop(struct clk_plt_data *data,
  220. unsigned int i)
  221. {
  222. while (i--)
  223. plt_clk_unregister(data->clks[i]);
  224. }
  225. static const char **plt_clk_register_parents(struct platform_device *pdev,
  226. struct clk_plt_data *data,
  227. const struct pmc_clk *clks)
  228. {
  229. const char **parent_names;
  230. unsigned int i;
  231. int err;
  232. int nparents = 0;
  233. data->nparents = 0;
  234. while (clks[nparents].name)
  235. nparents++;
  236. data->parents = devm_kcalloc(&pdev->dev, nparents,
  237. sizeof(*data->parents), GFP_KERNEL);
  238. if (!data->parents)
  239. return ERR_PTR(-ENOMEM);
  240. parent_names = kcalloc(nparents, sizeof(*parent_names),
  241. GFP_KERNEL);
  242. if (!parent_names)
  243. return ERR_PTR(-ENOMEM);
  244. for (i = 0; i < nparents; i++) {
  245. data->parents[i] =
  246. plt_clk_register_fixed_rate(pdev, clks[i].name,
  247. clks[i].parent_name,
  248. clks[i].freq);
  249. if (IS_ERR(data->parents[i])) {
  250. err = PTR_ERR(data->parents[i]);
  251. goto err_unreg;
  252. }
  253. parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
  254. }
  255. data->nparents = nparents;
  256. return parent_names;
  257. err_unreg:
  258. plt_clk_unregister_fixed_rate_loop(data, i);
  259. plt_clk_free_parent_names_loop(parent_names, i);
  260. return ERR_PTR(err);
  261. }
  262. static void plt_clk_unregister_parents(struct clk_plt_data *data)
  263. {
  264. plt_clk_unregister_fixed_rate_loop(data, data->nparents);
  265. }
  266. static int plt_clk_probe(struct platform_device *pdev)
  267. {
  268. const struct pmc_clk_data *pmc_data;
  269. const char **parent_names;
  270. struct clk_plt_data *data;
  271. unsigned int i;
  272. int err;
  273. pmc_data = dev_get_platdata(&pdev->dev);
  274. if (!pmc_data || !pmc_data->clks)
  275. return -EINVAL;
  276. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  277. if (!data)
  278. return -ENOMEM;
  279. parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
  280. if (IS_ERR(parent_names))
  281. return PTR_ERR(parent_names);
  282. for (i = 0; i < PMC_CLK_NUM; i++) {
  283. data->clks[i] = plt_clk_register(pdev, i, pmc_data,
  284. parent_names, data->nparents);
  285. if (IS_ERR(data->clks[i])) {
  286. err = PTR_ERR(data->clks[i]);
  287. goto err_unreg_clk_plt;
  288. }
  289. }
  290. data->mclk_lookup = clkdev_hw_create(&data->clks[3]->hw, "mclk", NULL);
  291. if (!data->mclk_lookup) {
  292. err = -ENOMEM;
  293. goto err_unreg_clk_plt;
  294. }
  295. data->ether_clk_lookup = clkdev_hw_create(&data->clks[4]->hw,
  296. "ether_clk", NULL);
  297. if (!data->ether_clk_lookup) {
  298. err = -ENOMEM;
  299. goto err_drop_mclk;
  300. }
  301. plt_clk_free_parent_names_loop(parent_names, data->nparents);
  302. platform_set_drvdata(pdev, data);
  303. return 0;
  304. err_drop_mclk:
  305. clkdev_drop(data->mclk_lookup);
  306. err_unreg_clk_plt:
  307. plt_clk_unregister_loop(data, i);
  308. plt_clk_unregister_parents(data);
  309. plt_clk_free_parent_names_loop(parent_names, data->nparents);
  310. return err;
  311. }
  312. static int plt_clk_remove(struct platform_device *pdev)
  313. {
  314. struct clk_plt_data *data;
  315. data = platform_get_drvdata(pdev);
  316. clkdev_drop(data->ether_clk_lookup);
  317. clkdev_drop(data->mclk_lookup);
  318. plt_clk_unregister_loop(data, PMC_CLK_NUM);
  319. plt_clk_unregister_parents(data);
  320. return 0;
  321. }
  322. static struct platform_driver plt_clk_driver = {
  323. .driver = {
  324. .name = "clk-pmc-atom",
  325. },
  326. .probe = plt_clk_probe,
  327. .remove = plt_clk_remove,
  328. };
  329. builtin_platform_driver(plt_clk_driver);