altera_edac.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2017-2018, Intel Corporation
  4. * Copyright (C) 2015 Altera Corporation
  5. */
  6. #ifndef _ALTERA_EDAC_H
  7. #define _ALTERA_EDAC_H
  8. #include <linux/arm-smccc.h>
  9. #include <linux/edac.h>
  10. #include <linux/types.h>
  11. /* SDRAM Controller CtrlCfg Register */
  12. #define CV_CTLCFG_OFST 0x00
  13. /* SDRAM Controller CtrlCfg Register Bit Masks */
  14. #define CV_CTLCFG_ECC_EN 0x400
  15. #define CV_CTLCFG_ECC_CORR_EN 0x800
  16. #define CV_CTLCFG_GEN_SB_ERR 0x2000
  17. #define CV_CTLCFG_GEN_DB_ERR 0x4000
  18. #define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN)
  19. /* SDRAM Controller Address Width Register */
  20. #define CV_DRAMADDRW_OFST 0x2C
  21. /* SDRAM Controller Address Widths Field Register */
  22. #define DRAMADDRW_COLBIT_MASK 0x001F
  23. #define DRAMADDRW_COLBIT_SHIFT 0
  24. #define DRAMADDRW_ROWBIT_MASK 0x03E0
  25. #define DRAMADDRW_ROWBIT_SHIFT 5
  26. #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
  27. #define CV_DRAMADDRW_BANKBIT_SHIFT 10
  28. #define CV_DRAMADDRW_CSBIT_MASK 0xE000
  29. #define CV_DRAMADDRW_CSBIT_SHIFT 13
  30. /* SDRAM Controller Interface Data Width Register */
  31. #define CV_DRAMIFWIDTH_OFST 0x30
  32. /* SDRAM Controller Interface Data Width Defines */
  33. #define CV_DRAMIFWIDTH_16B_ECC 24
  34. #define CV_DRAMIFWIDTH_32B_ECC 40
  35. /* SDRAM Controller DRAM Status Register */
  36. #define CV_DRAMSTS_OFST 0x38
  37. /* SDRAM Controller DRAM Status Register Bit Masks */
  38. #define CV_DRAMSTS_SBEERR 0x04
  39. #define CV_DRAMSTS_DBEERR 0x08
  40. #define CV_DRAMSTS_CORR_DROP 0x10
  41. /* SDRAM Controller DRAM IRQ Register */
  42. #define CV_DRAMINTR_OFST 0x3C
  43. /* SDRAM Controller DRAM IRQ Register Bit Masks */
  44. #define CV_DRAMINTR_INTREN 0x01
  45. #define CV_DRAMINTR_SBEMASK 0x02
  46. #define CV_DRAMINTR_DBEMASK 0x04
  47. #define CV_DRAMINTR_CORRDROPMASK 0x08
  48. #define CV_DRAMINTR_INTRCLR 0x10
  49. /* SDRAM Controller Single Bit Error Count Register */
  50. #define CV_SBECOUNT_OFST 0x40
  51. /* SDRAM Controller Double Bit Error Count Register */
  52. #define CV_DBECOUNT_OFST 0x44
  53. /* SDRAM Controller ECC Error Address Register */
  54. #define CV_ERRADDR_OFST 0x48
  55. /*-----------------------------------------*/
  56. /* SDRAM Controller EccCtrl Register */
  57. #define A10_ECCCTRL1_OFST 0x00
  58. /* SDRAM Controller EccCtrl Register Bit Masks */
  59. #define A10_ECCCTRL1_ECC_EN 0x001
  60. #define A10_ECCCTRL1_CNT_RST 0x010
  61. #define A10_ECCCTRL1_AWB_CNT_RST 0x100
  62. #define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \
  63. A10_ECCCTRL1_AWB_CNT_RST)
  64. /* SDRAM Controller Address Width Register */
  65. #define CV_DRAMADDRW 0xFFC2502C
  66. #define A10_DRAMADDRW 0xFFCFA0A8
  67. #define S10_DRAMADDRW 0xF80110E0
  68. /* SDRAM Controller Address Widths Field Register */
  69. #define DRAMADDRW_COLBIT_MASK 0x001F
  70. #define DRAMADDRW_COLBIT_SHIFT 0
  71. #define DRAMADDRW_ROWBIT_MASK 0x03E0
  72. #define DRAMADDRW_ROWBIT_SHIFT 5
  73. #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
  74. #define CV_DRAMADDRW_BANKBIT_SHIFT 10
  75. #define CV_DRAMADDRW_CSBIT_MASK 0xE000
  76. #define CV_DRAMADDRW_CSBIT_SHIFT 13
  77. #define A10_DRAMADDRW_BANKBIT_MASK 0x3C00
  78. #define A10_DRAMADDRW_BANKBIT_SHIFT 10
  79. #define A10_DRAMADDRW_GRPBIT_MASK 0xC000
  80. #define A10_DRAMADDRW_GRPBIT_SHIFT 14
  81. #define A10_DRAMADDRW_CSBIT_MASK 0x70000
  82. #define A10_DRAMADDRW_CSBIT_SHIFT 16
  83. /* SDRAM Controller Interface Data Width Register */
  84. #define CV_DRAMIFWIDTH 0xFFC25030
  85. #define A10_DRAMIFWIDTH 0xFFCFB008
  86. #define S10_DRAMIFWIDTH 0xF8011008
  87. /* SDRAM Controller Interface Data Width Defines */
  88. #define CV_DRAMIFWIDTH_16B_ECC 24
  89. #define CV_DRAMIFWIDTH_32B_ECC 40
  90. #define A10_DRAMIFWIDTH_16B 0x0
  91. #define A10_DRAMIFWIDTH_32B 0x1
  92. #define A10_DRAMIFWIDTH_64B 0x2
  93. /* SDRAM Controller DRAM IRQ Register */
  94. #define A10_ERRINTEN_OFST 0x10
  95. /* SDRAM Controller DRAM IRQ Register Bit Masks */
  96. #define A10_ERRINTEN_SERRINTEN 0x01
  97. #define A10_ERRINTEN_DERRINTEN 0x02
  98. #define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \
  99. A10_ERRINTEN_DERRINTEN)
  100. /* SDRAM Interrupt Mode Register */
  101. #define A10_INTMODE_OFST 0x1C
  102. #define A10_INTMODE_SB_INT 1
  103. /* SDRAM Controller Error Status Register */
  104. #define A10_INTSTAT_OFST 0x20
  105. /* SDRAM Controller Error Status Register Bit Masks */
  106. #define A10_INTSTAT_SBEERR 0x01
  107. #define A10_INTSTAT_DBEERR 0x02
  108. /* SDRAM Controller ECC Error Address Register */
  109. #define A10_DERRADDR_OFST 0x2C
  110. #define A10_SERRADDR_OFST 0x30
  111. /* SDRAM Controller ECC Diagnostic Register */
  112. #define A10_DIAGINTTEST_OFST 0x24
  113. #define A10_DIAGINT_TSERRA_MASK 0x0001
  114. #define A10_DIAGINT_TDERRA_MASK 0x0100
  115. #define A10_SBERR_IRQ 34
  116. #define A10_DBERR_IRQ 32
  117. /* SDRAM Single Bit Error Count Compare Set Register */
  118. #define A10_SERRCNTREG_OFST 0x3C
  119. #define A10_SYMAN_INTMASK_CLR 0xFFD06098
  120. #define A10_INTMASK_CLR_OFST 0x10
  121. #define A10_DDR0_IRQ_MASK BIT(17)
  122. /************* Stratix10 Defines **************/
  123. /* SDRAM Controller EccCtrl Register */
  124. #define S10_ECCCTRL1_OFST 0xF8011100
  125. /* SDRAM Controller DRAM IRQ Register */
  126. #define S10_ERRINTEN_OFST 0xF8011110
  127. /* SDRAM Interrupt Mode Register */
  128. #define S10_INTMODE_OFST 0xF801111C
  129. /* SDRAM Controller Error Status Register */
  130. #define S10_INTSTAT_OFST 0xF8011120
  131. /* SDRAM Controller ECC Error Address Register */
  132. #define S10_DERRADDR_OFST 0xF801112C
  133. #define S10_SERRADDR_OFST 0xF8011130
  134. /* SDRAM Controller ECC Diagnostic Register */
  135. #define S10_DIAGINTTEST_OFST 0xF8011124
  136. /* SDRAM Single Bit Error Count Compare Set Register */
  137. #define S10_SERRCNTREG_OFST 0xF801113C
  138. /* Sticky registers for Uncorrected Errors */
  139. #define S10_SYSMGR_UE_VAL_OFST 0xFFD12220
  140. #define S10_SYSMGR_UE_ADDR_OFST 0xFFD12224
  141. struct altr_sdram_prv_data {
  142. int ecc_ctrl_offset;
  143. int ecc_ctl_en_mask;
  144. int ecc_cecnt_offset;
  145. int ecc_uecnt_offset;
  146. int ecc_stat_offset;
  147. int ecc_stat_ce_mask;
  148. int ecc_stat_ue_mask;
  149. int ecc_saddr_offset;
  150. int ecc_daddr_offset;
  151. int ecc_irq_en_offset;
  152. int ecc_irq_en_mask;
  153. int ecc_irq_clr_offset;
  154. int ecc_irq_clr_mask;
  155. int ecc_cnt_rst_offset;
  156. int ecc_cnt_rst_mask;
  157. struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
  158. int ecc_enable_mask;
  159. int ce_set_mask;
  160. int ue_set_mask;
  161. int ce_ue_trgr_offset;
  162. };
  163. /* Altera SDRAM Memory Controller data */
  164. struct altr_sdram_mc_data {
  165. struct regmap *mc_vbase;
  166. int sb_irq;
  167. int db_irq;
  168. const struct altr_sdram_prv_data *data;
  169. };
  170. /************************** EDAC Device Defines **************************/
  171. /***** General Device Trigger Defines *****/
  172. #define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */
  173. #define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */
  174. #define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */
  175. #define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */
  176. /******* Cyclone5 and Arria5 Defines *******/
  177. /* OCRAM ECC Management Group Defines */
  178. #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04
  179. #define ALTR_OCR_ECC_REG_OFFSET 0x00
  180. #define ALTR_OCR_ECC_EN BIT(0)
  181. #define ALTR_OCR_ECC_INJS BIT(1)
  182. #define ALTR_OCR_ECC_INJD BIT(2)
  183. #define ALTR_OCR_ECC_SERR BIT(3)
  184. #define ALTR_OCR_ECC_DERR BIT(4)
  185. /* L2 ECC Management Group Defines */
  186. #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00
  187. #define ALTR_L2_ECC_REG_OFFSET 0x00
  188. #define ALTR_L2_ECC_EN BIT(0)
  189. #define ALTR_L2_ECC_INJS BIT(1)
  190. #define ALTR_L2_ECC_INJD BIT(2)
  191. /* Arria10 General ECC Block Module Defines */
  192. #define ALTR_A10_ECC_CTRL_OFST 0x08
  193. #define ALTR_A10_ECC_EN BIT(0)
  194. #define ALTR_A10_ECC_INITA BIT(16)
  195. #define ALTR_A10_ECC_INITB BIT(24)
  196. #define ALTR_A10_ECC_INITSTAT_OFST 0x0C
  197. #define ALTR_A10_ECC_INITCOMPLETEA BIT(0)
  198. #define ALTR_A10_ECC_INITCOMPLETEB BIT(8)
  199. #define ALTR_A10_ECC_ERRINTEN_OFST 0x10
  200. #define ALTR_A10_ECC_ERRINTENS_OFST 0x14
  201. #define ALTR_A10_ECC_ERRINTENR_OFST 0x18
  202. #define ALTR_A10_ECC_SERRINTEN BIT(0)
  203. #define ALTR_A10_ECC_INTMODE_OFST 0x1C
  204. #define ALTR_A10_ECC_INTMODE BIT(0)
  205. #define ALTR_A10_ECC_INTSTAT_OFST 0x20
  206. #define ALTR_A10_ECC_SERRPENA BIT(0)
  207. #define ALTR_A10_ECC_DERRPENA BIT(8)
  208. #define ALTR_A10_ECC_ERRPENA_MASK (ALTR_A10_ECC_SERRPENA | \
  209. ALTR_A10_ECC_DERRPENA)
  210. #define ALTR_A10_ECC_SERRPENB BIT(16)
  211. #define ALTR_A10_ECC_DERRPENB BIT(24)
  212. #define ALTR_A10_ECC_ERRPENB_MASK (ALTR_A10_ECC_SERRPENB | \
  213. ALTR_A10_ECC_DERRPENB)
  214. #define ALTR_A10_ECC_INTTEST_OFST 0x24
  215. #define ALTR_A10_ECC_TSERRA BIT(0)
  216. #define ALTR_A10_ECC_TDERRA BIT(8)
  217. #define ALTR_A10_ECC_TSERRB BIT(16)
  218. #define ALTR_A10_ECC_TDERRB BIT(24)
  219. /* ECC Manager Defines */
  220. #define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
  221. #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
  222. #define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1)
  223. #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
  224. #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
  225. #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0)
  226. #define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1)
  227. #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8
  228. #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15)
  229. #define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31)
  230. /* Arria 10 L2 ECC Management Group Defines */
  231. #define ALTR_A10_L2_ECC_CTL_OFST 0x0
  232. #define ALTR_A10_L2_ECC_EN_CTL BIT(0)
  233. #define ALTR_A10_L2_ECC_STATUS 0xFFD060A4
  234. #define ALTR_A10_L2_ECC_STAT_OFST 0xA4
  235. #define ALTR_A10_L2_ECC_SERR_PEND BIT(0)
  236. #define ALTR_A10_L2_ECC_MERR_PEND BIT(0)
  237. #define ALTR_A10_L2_ECC_CLR_OFST 0x4
  238. #define ALTR_A10_L2_ECC_SERR_CLR BIT(15)
  239. #define ALTR_A10_L2_ECC_MERR_CLR BIT(31)
  240. #define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST
  241. #define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101
  242. #define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101
  243. /* Arria 10 OCRAM ECC Management Group Defines */
  244. #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
  245. /* Arria 10 Ethernet ECC Management Group Defines */
  246. #define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
  247. /* Arria 10 SDMMC ECC Management Group Defines */
  248. #define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15))
  249. /* A10 ECC Controller memory initialization timeout */
  250. #define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
  251. /************* Stratix10 Defines **************/
  252. /* Stratix10 ECC Manager Defines */
  253. #define S10_SYSMGR_ECC_INTMASK_VAL_OFST 0xFFD12090
  254. #define S10_SYSMGR_ECC_INTMASK_SET_OFST 0xFFD12094
  255. #define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0xFFD12098
  256. #define S10_SYSMGR_ECC_INTSTAT_SERR_OFST 0xFFD1209C
  257. #define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xFFD120A0
  258. #define S10_DDR0_IRQ_MASK BIT(16)
  259. struct altr_edac_device_dev;
  260. struct edac_device_prv_data {
  261. int (*setup)(struct altr_edac_device_dev *device);
  262. int ce_clear_mask;
  263. int ue_clear_mask;
  264. int irq_status_mask;
  265. void * (*alloc_mem)(size_t size, void **other);
  266. void (*free_mem)(void *p, size_t size, void *other);
  267. int ecc_enable_mask;
  268. int ecc_en_ofst;
  269. int ce_set_mask;
  270. int ue_set_mask;
  271. int set_err_ofst;
  272. irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
  273. int trig_alloc_sz;
  274. const struct file_operations *inject_fops;
  275. bool panic;
  276. };
  277. struct altr_edac_device_dev {
  278. struct list_head next;
  279. void __iomem *base;
  280. int sb_irq;
  281. int db_irq;
  282. const struct edac_device_prv_data *data;
  283. struct dentry *debugfs_dir;
  284. char *edac_dev_name;
  285. struct altr_arria10_edac *edac;
  286. struct edac_device_ctl_info *edac_dev;
  287. struct device ddev;
  288. int edac_idx;
  289. };
  290. struct altr_arria10_edac {
  291. struct device *dev;
  292. struct regmap *ecc_mgr_map;
  293. int sb_irq;
  294. int db_irq;
  295. struct irq_domain *domain;
  296. struct irq_chip irq_chip;
  297. struct list_head a10_ecc_devices;
  298. };
  299. /*
  300. * Functions specified by ARM SMC Calling convention:
  301. *
  302. * FAST call executes atomic operations, returns when the requested operation
  303. * has completed.
  304. * STD call starts a operation which can be preempted by a non-secure
  305. * interrupt. The call can return before the requested operation has
  306. * completed.
  307. *
  308. * a0..a7 is used as register names in the descriptions below, on arm32
  309. * that translates to r0..r7 and on arm64 to w0..w7.
  310. */
  311. #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
  312. ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
  313. ARM_SMCCC_OWNER_SIP, (func_num))
  314. #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
  315. ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
  316. ARM_SMCCC_OWNER_SIP, (func_num))
  317. #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
  318. #define INTEL_SIP_SMC_STATUS_OK 0x0
  319. #define INTEL_SIP_SMC_REG_ERROR 0x5
  320. /*
  321. * Request INTEL_SIP_SMC_REG_READ
  322. *
  323. * Read a protected register using SMCCC
  324. *
  325. * Call register usage:
  326. * a0: INTEL_SIP_SMC_REG_READ.
  327. * a1: register address.
  328. * a2-7: not used.
  329. *
  330. * Return status:
  331. * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
  332. * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
  333. * a1: Value in the register
  334. * a2-3: not used.
  335. */
  336. #define INTEL_SIP_SMC_FUNCID_REG_READ 7
  337. #define INTEL_SIP_SMC_REG_READ \
  338. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
  339. /*
  340. * Request INTEL_SIP_SMC_REG_WRITE
  341. *
  342. * Write a protected register using SMCCC
  343. *
  344. * Call register usage:
  345. * a0: INTEL_SIP_SMC_REG_WRITE.
  346. * a1: register address
  347. * a2: value to program into register.
  348. * a3-7: not used.
  349. *
  350. * Return status:
  351. * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
  352. * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
  353. * a1-3: not used.
  354. */
  355. #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
  356. #define INTEL_SIP_SMC_REG_WRITE \
  357. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
  358. struct altr_stratix10_edac {
  359. struct device *dev;
  360. int sb_irq;
  361. struct irq_domain *domain;
  362. struct irq_chip irq_chip;
  363. struct list_head s10_ecc_devices;
  364. struct notifier_block panic_notifier;
  365. };
  366. #endif /* #ifndef _ALTERA_EDAC_H */