exynos_drm_rotator.c 11 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3. * Authors:
  4. * YoungJun Cho <yj44.cho@samsung.com>
  5. * Eunchul Kim <chulspro.kim@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundationr
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/clk.h>
  18. #include <linux/of_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <drm/drmP.h>
  21. #include <drm/exynos_drm.h>
  22. #include "regs-rotator.h"
  23. #include "exynos_drm_drv.h"
  24. #include "exynos_drm_iommu.h"
  25. #include "exynos_drm_ipp.h"
  26. /*
  27. * Rotator supports image crop/rotator and input/output DMA operations.
  28. * input DMA reads image data from the memory.
  29. * output DMA writes image data to memory.
  30. */
  31. #define ROTATOR_AUTOSUSPEND_DELAY 2000
  32. #define rot_read(offset) readl(rot->regs + (offset))
  33. #define rot_write(cfg, offset) writel(cfg, rot->regs + (offset))
  34. enum rot_irq_status {
  35. ROT_IRQ_STATUS_COMPLETE = 8,
  36. ROT_IRQ_STATUS_ILLEGAL = 9,
  37. };
  38. struct rot_variant {
  39. const struct exynos_drm_ipp_formats *formats;
  40. unsigned int num_formats;
  41. };
  42. /*
  43. * A structure of rotator context.
  44. * @ippdrv: prepare initialization using ippdrv.
  45. * @regs: memory mapped io registers.
  46. * @clock: rotator gate clock.
  47. * @limit_tbl: limitation of rotator.
  48. * @irq: irq number.
  49. */
  50. struct rot_context {
  51. struct exynos_drm_ipp ipp;
  52. struct drm_device *drm_dev;
  53. struct device *dev;
  54. void __iomem *regs;
  55. struct clk *clock;
  56. const struct exynos_drm_ipp_formats *formats;
  57. unsigned int num_formats;
  58. struct exynos_drm_ipp_task *task;
  59. };
  60. static void rotator_reg_set_irq(struct rot_context *rot, bool enable)
  61. {
  62. u32 val = rot_read(ROT_CONFIG);
  63. if (enable == true)
  64. val |= ROT_CONFIG_IRQ;
  65. else
  66. val &= ~ROT_CONFIG_IRQ;
  67. rot_write(val, ROT_CONFIG);
  68. }
  69. static enum rot_irq_status rotator_reg_get_irq_status(struct rot_context *rot)
  70. {
  71. u32 val = rot_read(ROT_STATUS);
  72. val = ROT_STATUS_IRQ(val);
  73. if (val == ROT_STATUS_IRQ_VAL_COMPLETE)
  74. return ROT_IRQ_STATUS_COMPLETE;
  75. return ROT_IRQ_STATUS_ILLEGAL;
  76. }
  77. static irqreturn_t rotator_irq_handler(int irq, void *arg)
  78. {
  79. struct rot_context *rot = arg;
  80. enum rot_irq_status irq_status;
  81. u32 val;
  82. /* Get execution result */
  83. irq_status = rotator_reg_get_irq_status(rot);
  84. /* clear status */
  85. val = rot_read(ROT_STATUS);
  86. val |= ROT_STATUS_IRQ_PENDING((u32)irq_status);
  87. rot_write(val, ROT_STATUS);
  88. if (rot->task) {
  89. struct exynos_drm_ipp_task *task = rot->task;
  90. rot->task = NULL;
  91. pm_runtime_mark_last_busy(rot->dev);
  92. pm_runtime_put_autosuspend(rot->dev);
  93. exynos_drm_ipp_task_done(task,
  94. irq_status == ROT_IRQ_STATUS_COMPLETE ? 0 : -EINVAL);
  95. }
  96. return IRQ_HANDLED;
  97. }
  98. static void rotator_src_set_fmt(struct rot_context *rot, u32 fmt)
  99. {
  100. u32 val;
  101. val = rot_read(ROT_CONTROL);
  102. val &= ~ROT_CONTROL_FMT_MASK;
  103. switch (fmt) {
  104. case DRM_FORMAT_NV12:
  105. val |= ROT_CONTROL_FMT_YCBCR420_2P;
  106. break;
  107. case DRM_FORMAT_XRGB8888:
  108. val |= ROT_CONTROL_FMT_RGB888;
  109. break;
  110. }
  111. rot_write(val, ROT_CONTROL);
  112. }
  113. static void rotator_src_set_buf(struct rot_context *rot,
  114. struct exynos_drm_ipp_buffer *buf)
  115. {
  116. u32 val;
  117. /* Set buffer size configuration */
  118. val = ROT_SET_BUF_SIZE_H(buf->buf.height) |
  119. ROT_SET_BUF_SIZE_W(buf->buf.pitch[0] / buf->format->cpp[0]);
  120. rot_write(val, ROT_SRC_BUF_SIZE);
  121. /* Set crop image position configuration */
  122. val = ROT_CROP_POS_Y(buf->rect.y) | ROT_CROP_POS_X(buf->rect.x);
  123. rot_write(val, ROT_SRC_CROP_POS);
  124. val = ROT_SRC_CROP_SIZE_H(buf->rect.h) |
  125. ROT_SRC_CROP_SIZE_W(buf->rect.w);
  126. rot_write(val, ROT_SRC_CROP_SIZE);
  127. /* Set buffer DMA address */
  128. rot_write(buf->dma_addr[0], ROT_SRC_BUF_ADDR(0));
  129. rot_write(buf->dma_addr[1], ROT_SRC_BUF_ADDR(1));
  130. }
  131. static void rotator_dst_set_transf(struct rot_context *rot,
  132. unsigned int rotation)
  133. {
  134. u32 val;
  135. /* Set transform configuration */
  136. val = rot_read(ROT_CONTROL);
  137. val &= ~ROT_CONTROL_FLIP_MASK;
  138. if (rotation & DRM_MODE_REFLECT_X)
  139. val |= ROT_CONTROL_FLIP_VERTICAL;
  140. if (rotation & DRM_MODE_REFLECT_Y)
  141. val |= ROT_CONTROL_FLIP_HORIZONTAL;
  142. val &= ~ROT_CONTROL_ROT_MASK;
  143. if (rotation & DRM_MODE_ROTATE_90)
  144. val |= ROT_CONTROL_ROT_90;
  145. else if (rotation & DRM_MODE_ROTATE_180)
  146. val |= ROT_CONTROL_ROT_180;
  147. else if (rotation & DRM_MODE_ROTATE_270)
  148. val |= ROT_CONTROL_ROT_270;
  149. rot_write(val, ROT_CONTROL);
  150. }
  151. static void rotator_dst_set_buf(struct rot_context *rot,
  152. struct exynos_drm_ipp_buffer *buf)
  153. {
  154. u32 val;
  155. /* Set buffer size configuration */
  156. val = ROT_SET_BUF_SIZE_H(buf->buf.height) |
  157. ROT_SET_BUF_SIZE_W(buf->buf.pitch[0] / buf->format->cpp[0]);
  158. rot_write(val, ROT_DST_BUF_SIZE);
  159. /* Set crop image position configuration */
  160. val = ROT_CROP_POS_Y(buf->rect.y) | ROT_CROP_POS_X(buf->rect.x);
  161. rot_write(val, ROT_DST_CROP_POS);
  162. /* Set buffer DMA address */
  163. rot_write(buf->dma_addr[0], ROT_DST_BUF_ADDR(0));
  164. rot_write(buf->dma_addr[1], ROT_DST_BUF_ADDR(1));
  165. }
  166. static void rotator_start(struct rot_context *rot)
  167. {
  168. u32 val;
  169. /* Set interrupt enable */
  170. rotator_reg_set_irq(rot, true);
  171. val = rot_read(ROT_CONTROL);
  172. val |= ROT_CONTROL_START;
  173. rot_write(val, ROT_CONTROL);
  174. }
  175. static int rotator_commit(struct exynos_drm_ipp *ipp,
  176. struct exynos_drm_ipp_task *task)
  177. {
  178. struct rot_context *rot =
  179. container_of(ipp, struct rot_context, ipp);
  180. pm_runtime_get_sync(rot->dev);
  181. rot->task = task;
  182. rotator_src_set_fmt(rot, task->src.buf.fourcc);
  183. rotator_src_set_buf(rot, &task->src);
  184. rotator_dst_set_transf(rot, task->transform.rotation);
  185. rotator_dst_set_buf(rot, &task->dst);
  186. rotator_start(rot);
  187. return 0;
  188. }
  189. static const struct exynos_drm_ipp_funcs ipp_funcs = {
  190. .commit = rotator_commit,
  191. };
  192. static int rotator_bind(struct device *dev, struct device *master, void *data)
  193. {
  194. struct rot_context *rot = dev_get_drvdata(dev);
  195. struct drm_device *drm_dev = data;
  196. struct exynos_drm_ipp *ipp = &rot->ipp;
  197. rot->drm_dev = drm_dev;
  198. drm_iommu_attach_device(drm_dev, dev);
  199. exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs,
  200. DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE,
  201. rot->formats, rot->num_formats, "rotator");
  202. dev_info(dev, "The exynos rotator has been probed successfully\n");
  203. return 0;
  204. }
  205. static void rotator_unbind(struct device *dev, struct device *master,
  206. void *data)
  207. {
  208. struct rot_context *rot = dev_get_drvdata(dev);
  209. struct drm_device *drm_dev = data;
  210. struct exynos_drm_ipp *ipp = &rot->ipp;
  211. exynos_drm_ipp_unregister(drm_dev, ipp);
  212. drm_iommu_detach_device(rot->drm_dev, rot->dev);
  213. }
  214. static const struct component_ops rotator_component_ops = {
  215. .bind = rotator_bind,
  216. .unbind = rotator_unbind,
  217. };
  218. static int rotator_probe(struct platform_device *pdev)
  219. {
  220. struct device *dev = &pdev->dev;
  221. struct resource *regs_res;
  222. struct rot_context *rot;
  223. const struct rot_variant *variant;
  224. int irq;
  225. int ret;
  226. rot = devm_kzalloc(dev, sizeof(*rot), GFP_KERNEL);
  227. if (!rot)
  228. return -ENOMEM;
  229. variant = of_device_get_match_data(dev);
  230. rot->formats = variant->formats;
  231. rot->num_formats = variant->num_formats;
  232. rot->dev = dev;
  233. regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  234. rot->regs = devm_ioremap_resource(dev, regs_res);
  235. if (IS_ERR(rot->regs))
  236. return PTR_ERR(rot->regs);
  237. irq = platform_get_irq(pdev, 0);
  238. if (irq < 0) {
  239. dev_err(dev, "failed to get irq\n");
  240. return irq;
  241. }
  242. ret = devm_request_irq(dev, irq, rotator_irq_handler, 0, dev_name(dev),
  243. rot);
  244. if (ret < 0) {
  245. dev_err(dev, "failed to request irq\n");
  246. return ret;
  247. }
  248. rot->clock = devm_clk_get(dev, "rotator");
  249. if (IS_ERR(rot->clock)) {
  250. dev_err(dev, "failed to get clock\n");
  251. return PTR_ERR(rot->clock);
  252. }
  253. pm_runtime_use_autosuspend(dev);
  254. pm_runtime_set_autosuspend_delay(dev, ROTATOR_AUTOSUSPEND_DELAY);
  255. pm_runtime_enable(dev);
  256. platform_set_drvdata(pdev, rot);
  257. ret = component_add(dev, &rotator_component_ops);
  258. if (ret)
  259. goto err_component;
  260. return 0;
  261. err_component:
  262. pm_runtime_dont_use_autosuspend(dev);
  263. pm_runtime_disable(dev);
  264. return ret;
  265. }
  266. static int rotator_remove(struct platform_device *pdev)
  267. {
  268. struct device *dev = &pdev->dev;
  269. component_del(dev, &rotator_component_ops);
  270. pm_runtime_dont_use_autosuspend(dev);
  271. pm_runtime_disable(dev);
  272. return 0;
  273. }
  274. #ifdef CONFIG_PM
  275. static int rotator_runtime_suspend(struct device *dev)
  276. {
  277. struct rot_context *rot = dev_get_drvdata(dev);
  278. clk_disable_unprepare(rot->clock);
  279. return 0;
  280. }
  281. static int rotator_runtime_resume(struct device *dev)
  282. {
  283. struct rot_context *rot = dev_get_drvdata(dev);
  284. return clk_prepare_enable(rot->clock);
  285. }
  286. #endif
  287. static const struct drm_exynos_ipp_limit rotator_4210_rbg888_limits[] = {
  288. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_16K }, .v = { 8, SZ_16K }) },
  289. { IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
  290. };
  291. static const struct drm_exynos_ipp_limit rotator_4412_rbg888_limits[] = {
  292. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_8K }, .v = { 8, SZ_8K }) },
  293. { IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
  294. };
  295. static const struct drm_exynos_ipp_limit rotator_5250_rbg888_limits[] = {
  296. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_8K }, .v = { 8, SZ_8K }) },
  297. { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
  298. };
  299. static const struct drm_exynos_ipp_limit rotator_4210_yuv_limits[] = {
  300. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
  301. { IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
  302. };
  303. static const struct drm_exynos_ipp_limit rotator_4412_yuv_limits[] = {
  304. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_32K }, .v = { 32, SZ_32K }) },
  305. { IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
  306. };
  307. static const struct exynos_drm_ipp_formats rotator_4210_formats[] = {
  308. { IPP_SRCDST_FORMAT(XRGB8888, rotator_4210_rbg888_limits) },
  309. { IPP_SRCDST_FORMAT(NV12, rotator_4210_yuv_limits) },
  310. };
  311. static const struct exynos_drm_ipp_formats rotator_4412_formats[] = {
  312. { IPP_SRCDST_FORMAT(XRGB8888, rotator_4412_rbg888_limits) },
  313. { IPP_SRCDST_FORMAT(NV12, rotator_4412_yuv_limits) },
  314. };
  315. static const struct exynos_drm_ipp_formats rotator_5250_formats[] = {
  316. { IPP_SRCDST_FORMAT(XRGB8888, rotator_5250_rbg888_limits) },
  317. { IPP_SRCDST_FORMAT(NV12, rotator_4412_yuv_limits) },
  318. };
  319. static const struct rot_variant rotator_4210_data = {
  320. .formats = rotator_4210_formats,
  321. .num_formats = ARRAY_SIZE(rotator_4210_formats),
  322. };
  323. static const struct rot_variant rotator_4412_data = {
  324. .formats = rotator_4412_formats,
  325. .num_formats = ARRAY_SIZE(rotator_4412_formats),
  326. };
  327. static const struct rot_variant rotator_5250_data = {
  328. .formats = rotator_5250_formats,
  329. .num_formats = ARRAY_SIZE(rotator_5250_formats),
  330. };
  331. static const struct of_device_id exynos_rotator_match[] = {
  332. {
  333. .compatible = "samsung,exynos4210-rotator",
  334. .data = &rotator_4210_data,
  335. }, {
  336. .compatible = "samsung,exynos4212-rotator",
  337. .data = &rotator_4412_data,
  338. }, {
  339. .compatible = "samsung,exynos5250-rotator",
  340. .data = &rotator_5250_data,
  341. }, {
  342. },
  343. };
  344. MODULE_DEVICE_TABLE(of, exynos_rotator_match);
  345. static const struct dev_pm_ops rotator_pm_ops = {
  346. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  347. pm_runtime_force_resume)
  348. SET_RUNTIME_PM_OPS(rotator_runtime_suspend, rotator_runtime_resume,
  349. NULL)
  350. };
  351. struct platform_driver rotator_driver = {
  352. .probe = rotator_probe,
  353. .remove = rotator_remove,
  354. .driver = {
  355. .name = "exynos-rotator",
  356. .owner = THIS_MODULE,
  357. .pm = &rotator_pm_ops,
  358. .of_match_table = exynos_rotator_match,
  359. },
  360. };