irq-ativic32.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2005-2017 Andes Technology Corporation
  3. #include <linux/irq.h>
  4. #include <linux/of.h>
  5. #include <linux/of_irq.h>
  6. #include <linux/of_address.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irqdomain.h>
  9. #include <linux/irqchip.h>
  10. #include <nds32_intrinsic.h>
  11. static void ativic32_ack_irq(struct irq_data *data)
  12. {
  13. __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
  14. }
  15. static void ativic32_mask_irq(struct irq_data *data)
  16. {
  17. unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
  18. __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2);
  19. }
  20. static void ativic32_unmask_irq(struct irq_data *data)
  21. {
  22. unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
  23. __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
  24. }
  25. static struct irq_chip ativic32_chip = {
  26. .name = "ativic32",
  27. .irq_ack = ativic32_ack_irq,
  28. .irq_mask = ativic32_mask_irq,
  29. .irq_unmask = ativic32_unmask_irq,
  30. };
  31. static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
  32. static struct irq_domain *root_domain;
  33. static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
  34. irq_hw_number_t hw)
  35. {
  36. unsigned long int_trigger_type;
  37. u32 type;
  38. struct irq_data *irq_data;
  39. int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
  40. irq_data = irq_get_irq_data(virq);
  41. if (!irq_data)
  42. return -EINVAL;
  43. if (int_trigger_type & (BIT(hw))) {
  44. irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
  45. type = IRQ_TYPE_EDGE_RISING;
  46. } else {
  47. irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);
  48. type = IRQ_TYPE_LEVEL_HIGH;
  49. }
  50. irqd_set_trigger_type(irq_data, type);
  51. return 0;
  52. }
  53. static struct irq_domain_ops ativic32_ops = {
  54. .map = ativic32_irq_domain_map,
  55. .xlate = irq_domain_xlate_onecell
  56. };
  57. static irq_hw_number_t get_intr_src(void)
  58. {
  59. return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> ITYPE_offVECTOR)
  60. - NDS32_VECTOR_offINTERRUPT;
  61. }
  62. asmlinkage void asm_do_IRQ(struct pt_regs *regs)
  63. {
  64. irq_hw_number_t hwirq = get_intr_src();
  65. handle_domain_irq(root_domain, hwirq, regs);
  66. }
  67. int __init ativic32_init_irq(struct device_node *node, struct device_node *parent)
  68. {
  69. unsigned long int_vec_base, nivic, nr_ints;
  70. if (WARN(parent, "non-root ativic32 are not supported"))
  71. return -EINVAL;
  72. int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
  73. if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
  74. panic("Unable to use atcivic32 for this cpu.\n");
  75. nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
  76. if (nivic >= ARRAY_SIZE(nivic_map))
  77. panic("The number of input for ativic32 is not supported.\n");
  78. nr_ints = nivic_map[nivic];
  79. root_domain = irq_domain_add_linear(node, nr_ints,
  80. &ativic32_ops, NULL);
  81. if (!root_domain)
  82. panic("%s: unable to create IRQ domain\n", node->full_name);
  83. return 0;
  84. }
  85. IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);