rtsx_pcr.c 39 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. */
  21. #include <linux/pci.h>
  22. #include <linux/module.h>
  23. #include <linux/slab.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/highmem.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/delay.h>
  28. #include <linux/idr.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/mfd/core.h>
  31. #include <linux/rtsx_pci.h>
  32. #include <linux/mmc/card.h>
  33. #include <asm/unaligned.h>
  34. #include "rtsx_pcr.h"
  35. static bool msi_en = true;
  36. module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  37. MODULE_PARM_DESC(msi_en, "Enable MSI");
  38. static DEFINE_IDR(rtsx_pci_idr);
  39. static DEFINE_SPINLOCK(rtsx_pci_lock);
  40. static struct mfd_cell rtsx_pcr_cells[] = {
  41. [RTSX_SD_CARD] = {
  42. .name = DRV_NAME_RTSX_PCI_SDMMC,
  43. },
  44. [RTSX_MS_CARD] = {
  45. .name = DRV_NAME_RTSX_PCI_MS,
  46. },
  47. };
  48. static const struct pci_device_id rtsx_pci_ids[] = {
  49. { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  50. { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  51. { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  52. { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  53. { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  54. { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  55. { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56. { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57. { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58. { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  59. { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  60. { 0, }
  61. };
  62. MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  63. static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
  64. {
  65. rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
  66. 0xFC, pcr->aspm_en);
  67. }
  68. static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
  69. {
  70. rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
  71. 0xFC, 0);
  72. }
  73. static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
  74. {
  75. rtsx_pci_write_register(pcr, MSGTXDATA0,
  76. MASK_8_BIT_DEF, (u8) (latency & 0xFF));
  77. rtsx_pci_write_register(pcr, MSGTXDATA1,
  78. MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
  79. rtsx_pci_write_register(pcr, MSGTXDATA2,
  80. MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
  81. rtsx_pci_write_register(pcr, MSGTXDATA3,
  82. MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
  83. rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
  84. LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
  85. return 0;
  86. }
  87. int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
  88. {
  89. if (pcr->ops->set_ltr_latency)
  90. return pcr->ops->set_ltr_latency(pcr, latency);
  91. else
  92. return rtsx_comm_set_ltr_latency(pcr, latency);
  93. }
  94. static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
  95. {
  96. struct rtsx_cr_option *option = &pcr->option;
  97. if (pcr->aspm_enabled == enable)
  98. return;
  99. if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
  100. if (enable)
  101. rtsx_pci_enable_aspm(pcr);
  102. else
  103. rtsx_pci_disable_aspm(pcr);
  104. } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
  105. u8 mask = FORCE_ASPM_VAL_MASK;
  106. u8 val = 0;
  107. if (enable)
  108. val = pcr->aspm_en;
  109. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  110. }
  111. pcr->aspm_enabled = enable;
  112. }
  113. static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
  114. {
  115. if (pcr->ops->set_aspm)
  116. pcr->ops->set_aspm(pcr, false);
  117. else
  118. rtsx_comm_set_aspm(pcr, false);
  119. }
  120. int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
  121. {
  122. rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
  123. return 0;
  124. }
  125. static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
  126. {
  127. if (pcr->ops->set_l1off_cfg_sub_d0)
  128. pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
  129. }
  130. static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
  131. {
  132. struct rtsx_cr_option *option = &pcr->option;
  133. rtsx_disable_aspm(pcr);
  134. /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */
  135. msleep(1);
  136. if (option->ltr_enabled)
  137. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  138. if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
  139. rtsx_set_l1off_sub_cfg_d0(pcr, 1);
  140. }
  141. static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
  142. {
  143. if (pcr->ops->full_on)
  144. pcr->ops->full_on(pcr);
  145. else
  146. rtsx_comm_pm_full_on(pcr);
  147. }
  148. void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  149. {
  150. /* If pci device removed, don't queue idle work any more */
  151. if (pcr->remove_pci)
  152. return;
  153. if (pcr->state != PDEV_STAT_RUN) {
  154. pcr->state = PDEV_STAT_RUN;
  155. if (pcr->ops->enable_auto_blink)
  156. pcr->ops->enable_auto_blink(pcr);
  157. rtsx_pm_full_on(pcr);
  158. }
  159. mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  160. }
  161. EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  162. int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  163. {
  164. int i;
  165. u32 val = HAIMR_WRITE_START;
  166. val |= (u32)(addr & 0x3FFF) << 16;
  167. val |= (u32)mask << 8;
  168. val |= (u32)data;
  169. rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  170. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  171. val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  172. if ((val & HAIMR_TRANS_END) == 0) {
  173. if (data != (u8)val)
  174. return -EIO;
  175. return 0;
  176. }
  177. }
  178. return -ETIMEDOUT;
  179. }
  180. EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
  181. int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
  182. {
  183. u32 val = HAIMR_READ_START;
  184. int i;
  185. val |= (u32)(addr & 0x3FFF) << 16;
  186. rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  187. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  188. val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  189. if ((val & HAIMR_TRANS_END) == 0)
  190. break;
  191. }
  192. if (i >= MAX_RW_REG_CNT)
  193. return -ETIMEDOUT;
  194. if (data)
  195. *data = (u8)(val & 0xFF);
  196. return 0;
  197. }
  198. EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
  199. int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
  200. {
  201. int err, i, finished = 0;
  202. u8 tmp;
  203. rtsx_pci_init_cmd(pcr);
  204. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
  205. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
  206. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
  207. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
  208. err = rtsx_pci_send_cmd(pcr, 100);
  209. if (err < 0)
  210. return err;
  211. for (i = 0; i < 100000; i++) {
  212. err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
  213. if (err < 0)
  214. return err;
  215. if (!(tmp & 0x80)) {
  216. finished = 1;
  217. break;
  218. }
  219. }
  220. if (!finished)
  221. return -ETIMEDOUT;
  222. return 0;
  223. }
  224. int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
  225. {
  226. if (pcr->ops->write_phy)
  227. return pcr->ops->write_phy(pcr, addr, val);
  228. return __rtsx_pci_write_phy_register(pcr, addr, val);
  229. }
  230. EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
  231. int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  232. {
  233. int err, i, finished = 0;
  234. u16 data;
  235. u8 *ptr, tmp;
  236. rtsx_pci_init_cmd(pcr);
  237. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
  238. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
  239. err = rtsx_pci_send_cmd(pcr, 100);
  240. if (err < 0)
  241. return err;
  242. for (i = 0; i < 100000; i++) {
  243. err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
  244. if (err < 0)
  245. return err;
  246. if (!(tmp & 0x80)) {
  247. finished = 1;
  248. break;
  249. }
  250. }
  251. if (!finished)
  252. return -ETIMEDOUT;
  253. rtsx_pci_init_cmd(pcr);
  254. rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
  255. rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
  256. err = rtsx_pci_send_cmd(pcr, 100);
  257. if (err < 0)
  258. return err;
  259. ptr = rtsx_pci_get_cmd_data(pcr);
  260. data = ((u16)ptr[1] << 8) | ptr[0];
  261. if (val)
  262. *val = data;
  263. return 0;
  264. }
  265. int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  266. {
  267. if (pcr->ops->read_phy)
  268. return pcr->ops->read_phy(pcr, addr, val);
  269. return __rtsx_pci_read_phy_register(pcr, addr, val);
  270. }
  271. EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
  272. void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
  273. {
  274. if (pcr->ops->stop_cmd)
  275. return pcr->ops->stop_cmd(pcr);
  276. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  277. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  278. rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
  279. rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
  280. }
  281. EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
  282. void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
  283. u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
  284. {
  285. unsigned long flags;
  286. u32 val = 0;
  287. u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
  288. val |= (u32)(cmd_type & 0x03) << 30;
  289. val |= (u32)(reg_addr & 0x3FFF) << 16;
  290. val |= (u32)mask << 8;
  291. val |= (u32)data;
  292. spin_lock_irqsave(&pcr->lock, flags);
  293. ptr += pcr->ci;
  294. if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
  295. put_unaligned_le32(val, ptr);
  296. ptr++;
  297. pcr->ci++;
  298. }
  299. spin_unlock_irqrestore(&pcr->lock, flags);
  300. }
  301. EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
  302. void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
  303. {
  304. u32 val = 1 << 31;
  305. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  306. val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
  307. /* Hardware Auto Response */
  308. val |= 0x40000000;
  309. rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
  310. }
  311. EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
  312. int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
  313. {
  314. struct completion trans_done;
  315. u32 val = 1 << 31;
  316. long timeleft;
  317. unsigned long flags;
  318. int err = 0;
  319. spin_lock_irqsave(&pcr->lock, flags);
  320. /* set up data structures for the wakeup system */
  321. pcr->done = &trans_done;
  322. pcr->trans_result = TRANS_NOT_READY;
  323. init_completion(&trans_done);
  324. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  325. val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
  326. /* Hardware Auto Response */
  327. val |= 0x40000000;
  328. rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
  329. spin_unlock_irqrestore(&pcr->lock, flags);
  330. /* Wait for TRANS_OK_INT */
  331. timeleft = wait_for_completion_interruptible_timeout(
  332. &trans_done, msecs_to_jiffies(timeout));
  333. if (timeleft <= 0) {
  334. pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
  335. err = -ETIMEDOUT;
  336. goto finish_send_cmd;
  337. }
  338. spin_lock_irqsave(&pcr->lock, flags);
  339. if (pcr->trans_result == TRANS_RESULT_FAIL)
  340. err = -EINVAL;
  341. else if (pcr->trans_result == TRANS_RESULT_OK)
  342. err = 0;
  343. else if (pcr->trans_result == TRANS_NO_DEVICE)
  344. err = -ENODEV;
  345. spin_unlock_irqrestore(&pcr->lock, flags);
  346. finish_send_cmd:
  347. spin_lock_irqsave(&pcr->lock, flags);
  348. pcr->done = NULL;
  349. spin_unlock_irqrestore(&pcr->lock, flags);
  350. if ((err < 0) && (err != -ENODEV))
  351. rtsx_pci_stop_cmd(pcr);
  352. if (pcr->finish_me)
  353. complete(pcr->finish_me);
  354. return err;
  355. }
  356. EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
  357. static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
  358. dma_addr_t addr, unsigned int len, int end)
  359. {
  360. u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
  361. u64 val;
  362. u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
  363. pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
  364. if (end)
  365. option |= RTSX_SG_END;
  366. val = ((u64)addr << 32) | ((u64)len << 12) | option;
  367. put_unaligned_le64(val, ptr);
  368. pcr->sgi++;
  369. }
  370. int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  371. int num_sg, bool read, int timeout)
  372. {
  373. int err = 0, count;
  374. pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
  375. count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
  376. if (count < 1)
  377. return -EINVAL;
  378. pcr_dbg(pcr, "DMA mapping count: %d\n", count);
  379. err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
  380. rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
  381. return err;
  382. }
  383. EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
  384. int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  385. int num_sg, bool read)
  386. {
  387. enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  388. if (pcr->remove_pci)
  389. return -EINVAL;
  390. if ((sglist == NULL) || (num_sg <= 0))
  391. return -EINVAL;
  392. return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
  393. }
  394. EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
  395. void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  396. int num_sg, bool read)
  397. {
  398. enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  399. dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
  400. }
  401. EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
  402. int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  403. int count, bool read, int timeout)
  404. {
  405. struct completion trans_done;
  406. struct scatterlist *sg;
  407. dma_addr_t addr;
  408. long timeleft;
  409. unsigned long flags;
  410. unsigned int len;
  411. int i, err = 0;
  412. u32 val;
  413. u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
  414. if (pcr->remove_pci)
  415. return -ENODEV;
  416. if ((sglist == NULL) || (count < 1))
  417. return -EINVAL;
  418. val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
  419. pcr->sgi = 0;
  420. for_each_sg(sglist, sg, count, i) {
  421. addr = sg_dma_address(sg);
  422. len = sg_dma_len(sg);
  423. rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
  424. }
  425. spin_lock_irqsave(&pcr->lock, flags);
  426. pcr->done = &trans_done;
  427. pcr->trans_result = TRANS_NOT_READY;
  428. init_completion(&trans_done);
  429. rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
  430. rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
  431. spin_unlock_irqrestore(&pcr->lock, flags);
  432. timeleft = wait_for_completion_interruptible_timeout(
  433. &trans_done, msecs_to_jiffies(timeout));
  434. if (timeleft <= 0) {
  435. pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
  436. err = -ETIMEDOUT;
  437. goto out;
  438. }
  439. spin_lock_irqsave(&pcr->lock, flags);
  440. if (pcr->trans_result == TRANS_RESULT_FAIL) {
  441. err = -EILSEQ;
  442. if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
  443. pcr->dma_error_count++;
  444. }
  445. else if (pcr->trans_result == TRANS_NO_DEVICE)
  446. err = -ENODEV;
  447. spin_unlock_irqrestore(&pcr->lock, flags);
  448. out:
  449. spin_lock_irqsave(&pcr->lock, flags);
  450. pcr->done = NULL;
  451. spin_unlock_irqrestore(&pcr->lock, flags);
  452. if ((err < 0) && (err != -ENODEV))
  453. rtsx_pci_stop_cmd(pcr);
  454. if (pcr->finish_me)
  455. complete(pcr->finish_me);
  456. return err;
  457. }
  458. EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
  459. int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
  460. {
  461. int err;
  462. int i, j;
  463. u16 reg;
  464. u8 *ptr;
  465. if (buf_len > 512)
  466. buf_len = 512;
  467. ptr = buf;
  468. reg = PPBUF_BASE2;
  469. for (i = 0; i < buf_len / 256; i++) {
  470. rtsx_pci_init_cmd(pcr);
  471. for (j = 0; j < 256; j++)
  472. rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
  473. err = rtsx_pci_send_cmd(pcr, 250);
  474. if (err < 0)
  475. return err;
  476. memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
  477. ptr += 256;
  478. }
  479. if (buf_len % 256) {
  480. rtsx_pci_init_cmd(pcr);
  481. for (j = 0; j < buf_len % 256; j++)
  482. rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
  483. err = rtsx_pci_send_cmd(pcr, 250);
  484. if (err < 0)
  485. return err;
  486. }
  487. memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
  488. return 0;
  489. }
  490. EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
  491. int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
  492. {
  493. int err;
  494. int i, j;
  495. u16 reg;
  496. u8 *ptr;
  497. if (buf_len > 512)
  498. buf_len = 512;
  499. ptr = buf;
  500. reg = PPBUF_BASE2;
  501. for (i = 0; i < buf_len / 256; i++) {
  502. rtsx_pci_init_cmd(pcr);
  503. for (j = 0; j < 256; j++) {
  504. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  505. reg++, 0xFF, *ptr);
  506. ptr++;
  507. }
  508. err = rtsx_pci_send_cmd(pcr, 250);
  509. if (err < 0)
  510. return err;
  511. }
  512. if (buf_len % 256) {
  513. rtsx_pci_init_cmd(pcr);
  514. for (j = 0; j < buf_len % 256; j++) {
  515. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  516. reg++, 0xFF, *ptr);
  517. ptr++;
  518. }
  519. err = rtsx_pci_send_cmd(pcr, 250);
  520. if (err < 0)
  521. return err;
  522. }
  523. return 0;
  524. }
  525. EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
  526. static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
  527. {
  528. rtsx_pci_init_cmd(pcr);
  529. while (*tbl & 0xFFFF0000) {
  530. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  531. (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
  532. tbl++;
  533. }
  534. return rtsx_pci_send_cmd(pcr, 100);
  535. }
  536. int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
  537. {
  538. const u32 *tbl;
  539. if (card == RTSX_SD_CARD)
  540. tbl = pcr->sd_pull_ctl_enable_tbl;
  541. else if (card == RTSX_MS_CARD)
  542. tbl = pcr->ms_pull_ctl_enable_tbl;
  543. else
  544. return -EINVAL;
  545. return rtsx_pci_set_pull_ctl(pcr, tbl);
  546. }
  547. EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
  548. int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
  549. {
  550. const u32 *tbl;
  551. if (card == RTSX_SD_CARD)
  552. tbl = pcr->sd_pull_ctl_disable_tbl;
  553. else if (card == RTSX_MS_CARD)
  554. tbl = pcr->ms_pull_ctl_disable_tbl;
  555. else
  556. return -EINVAL;
  557. return rtsx_pci_set_pull_ctl(pcr, tbl);
  558. }
  559. EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
  560. static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
  561. {
  562. pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
  563. if (pcr->num_slots > 1)
  564. pcr->bier |= MS_INT_EN;
  565. /* Enable Bus Interrupt */
  566. rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
  567. pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
  568. }
  569. static inline u8 double_ssc_depth(u8 depth)
  570. {
  571. return ((depth > 1) ? (depth - 1) : depth);
  572. }
  573. static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
  574. {
  575. if (div > CLK_DIV_1) {
  576. if (ssc_depth > (div - 1))
  577. ssc_depth -= (div - 1);
  578. else
  579. ssc_depth = SSC_DEPTH_4M;
  580. }
  581. return ssc_depth;
  582. }
  583. int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  584. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  585. {
  586. int err, clk;
  587. u8 n, clk_divider, mcu_cnt, div;
  588. static const u8 depth[] = {
  589. [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
  590. [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
  591. [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
  592. [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
  593. [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
  594. };
  595. if (initial_mode) {
  596. /* We use 250k(around) here, in initial stage */
  597. clk_divider = SD_CLK_DIVIDE_128;
  598. card_clock = 30000000;
  599. } else {
  600. clk_divider = SD_CLK_DIVIDE_0;
  601. }
  602. err = rtsx_pci_write_register(pcr, SD_CFG1,
  603. SD_CLK_DIVIDE_MASK, clk_divider);
  604. if (err < 0)
  605. return err;
  606. /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
  607. if (card_clock == UHS_SDR104_MAX_DTR &&
  608. pcr->dma_error_count &&
  609. PCI_PID(pcr) == RTS5227_DEVICE_ID)
  610. card_clock = UHS_SDR104_MAX_DTR -
  611. (pcr->dma_error_count * 20000000);
  612. card_clock /= 1000000;
  613. pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
  614. clk = card_clock;
  615. if (!initial_mode && double_clk)
  616. clk = card_clock * 2;
  617. pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  618. clk, pcr->cur_clock);
  619. if (clk == pcr->cur_clock)
  620. return 0;
  621. if (pcr->ops->conv_clk_and_div_n)
  622. n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
  623. else
  624. n = (u8)(clk - 2);
  625. if ((clk <= 2) || (n > MAX_DIV_N_PCR))
  626. return -EINVAL;
  627. mcu_cnt = (u8)(125/clk + 3);
  628. if (mcu_cnt > 15)
  629. mcu_cnt = 15;
  630. /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
  631. div = CLK_DIV_1;
  632. while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
  633. if (pcr->ops->conv_clk_and_div_n) {
  634. int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
  635. DIV_N_TO_CLK) * 2;
  636. n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
  637. CLK_TO_DIV_N);
  638. } else {
  639. n = (n + 2) * 2 - 2;
  640. }
  641. div++;
  642. }
  643. pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
  644. ssc_depth = depth[ssc_depth];
  645. if (double_clk)
  646. ssc_depth = double_ssc_depth(ssc_depth);
  647. ssc_depth = revise_ssc_depth(ssc_depth, div);
  648. pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
  649. rtsx_pci_init_cmd(pcr);
  650. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  651. CLK_LOW_FREQ, CLK_LOW_FREQ);
  652. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  653. 0xFF, (div << 4) | mcu_cnt);
  654. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  655. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  656. SSC_DEPTH_MASK, ssc_depth);
  657. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
  658. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  659. if (vpclk) {
  660. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  661. PHASE_NOT_RESET, 0);
  662. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  663. PHASE_NOT_RESET, PHASE_NOT_RESET);
  664. }
  665. err = rtsx_pci_send_cmd(pcr, 2000);
  666. if (err < 0)
  667. return err;
  668. /* Wait SSC clock stable */
  669. udelay(SSC_CLOCK_STABLE_WAIT);
  670. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  671. if (err < 0)
  672. return err;
  673. pcr->cur_clock = clk;
  674. return 0;
  675. }
  676. EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
  677. int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
  678. {
  679. if (pcr->ops->card_power_on)
  680. return pcr->ops->card_power_on(pcr, card);
  681. return 0;
  682. }
  683. EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
  684. int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
  685. {
  686. if (pcr->ops->card_power_off)
  687. return pcr->ops->card_power_off(pcr, card);
  688. return 0;
  689. }
  690. EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
  691. int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
  692. {
  693. static const unsigned int cd_mask[] = {
  694. [RTSX_SD_CARD] = SD_EXIST,
  695. [RTSX_MS_CARD] = MS_EXIST
  696. };
  697. if (!(pcr->flags & PCR_MS_PMOS)) {
  698. /* When using single PMOS, accessing card is not permitted
  699. * if the existing card is not the designated one.
  700. */
  701. if (pcr->card_exist & (~cd_mask[card]))
  702. return -EIO;
  703. }
  704. return 0;
  705. }
  706. EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
  707. int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  708. {
  709. if (pcr->ops->switch_output_voltage)
  710. return pcr->ops->switch_output_voltage(pcr, voltage);
  711. return 0;
  712. }
  713. EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
  714. unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
  715. {
  716. unsigned int val;
  717. val = rtsx_pci_readl(pcr, RTSX_BIPR);
  718. if (pcr->ops->cd_deglitch)
  719. val = pcr->ops->cd_deglitch(pcr);
  720. return val;
  721. }
  722. EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
  723. void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
  724. {
  725. struct completion finish;
  726. pcr->finish_me = &finish;
  727. init_completion(&finish);
  728. if (pcr->done)
  729. complete(pcr->done);
  730. if (!pcr->remove_pci)
  731. rtsx_pci_stop_cmd(pcr);
  732. wait_for_completion_interruptible_timeout(&finish,
  733. msecs_to_jiffies(2));
  734. pcr->finish_me = NULL;
  735. }
  736. EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
  737. static void rtsx_pci_card_detect(struct work_struct *work)
  738. {
  739. struct delayed_work *dwork;
  740. struct rtsx_pcr *pcr;
  741. unsigned long flags;
  742. unsigned int card_detect = 0, card_inserted, card_removed;
  743. u32 irq_status;
  744. dwork = to_delayed_work(work);
  745. pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
  746. pcr_dbg(pcr, "--> %s\n", __func__);
  747. mutex_lock(&pcr->pcr_mutex);
  748. spin_lock_irqsave(&pcr->lock, flags);
  749. irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
  750. pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
  751. irq_status &= CARD_EXIST;
  752. card_inserted = pcr->card_inserted & irq_status;
  753. card_removed = pcr->card_removed;
  754. pcr->card_inserted = 0;
  755. pcr->card_removed = 0;
  756. spin_unlock_irqrestore(&pcr->lock, flags);
  757. if (card_inserted || card_removed) {
  758. pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
  759. card_inserted, card_removed);
  760. if (pcr->ops->cd_deglitch)
  761. card_inserted = pcr->ops->cd_deglitch(pcr);
  762. card_detect = card_inserted | card_removed;
  763. pcr->card_exist |= card_inserted;
  764. pcr->card_exist &= ~card_removed;
  765. }
  766. mutex_unlock(&pcr->pcr_mutex);
  767. if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
  768. pcr->slots[RTSX_SD_CARD].card_event(
  769. pcr->slots[RTSX_SD_CARD].p_dev);
  770. if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
  771. pcr->slots[RTSX_MS_CARD].card_event(
  772. pcr->slots[RTSX_MS_CARD].p_dev);
  773. }
  774. static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
  775. {
  776. if (pcr->ops->process_ocp)
  777. pcr->ops->process_ocp(pcr);
  778. }
  779. static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
  780. {
  781. if (pcr->option.ocp_en)
  782. rtsx_pci_process_ocp(pcr);
  783. return 0;
  784. }
  785. static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
  786. {
  787. struct rtsx_pcr *pcr = dev_id;
  788. u32 int_reg;
  789. if (!pcr)
  790. return IRQ_NONE;
  791. spin_lock(&pcr->lock);
  792. int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
  793. /* Clear interrupt flag */
  794. rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
  795. if ((int_reg & pcr->bier) == 0) {
  796. spin_unlock(&pcr->lock);
  797. return IRQ_NONE;
  798. }
  799. if (int_reg == 0xFFFFFFFF) {
  800. spin_unlock(&pcr->lock);
  801. return IRQ_HANDLED;
  802. }
  803. int_reg &= (pcr->bier | 0x7FFFFF);
  804. if (int_reg & SD_OC_INT)
  805. rtsx_pci_process_ocp_interrupt(pcr);
  806. if (int_reg & SD_INT) {
  807. if (int_reg & SD_EXIST) {
  808. pcr->card_inserted |= SD_EXIST;
  809. } else {
  810. pcr->card_removed |= SD_EXIST;
  811. pcr->card_inserted &= ~SD_EXIST;
  812. }
  813. pcr->dma_error_count = 0;
  814. }
  815. if (int_reg & MS_INT) {
  816. if (int_reg & MS_EXIST) {
  817. pcr->card_inserted |= MS_EXIST;
  818. } else {
  819. pcr->card_removed |= MS_EXIST;
  820. pcr->card_inserted &= ~MS_EXIST;
  821. }
  822. }
  823. if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
  824. if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
  825. pcr->trans_result = TRANS_RESULT_FAIL;
  826. if (pcr->done)
  827. complete(pcr->done);
  828. } else if (int_reg & TRANS_OK_INT) {
  829. pcr->trans_result = TRANS_RESULT_OK;
  830. if (pcr->done)
  831. complete(pcr->done);
  832. }
  833. }
  834. if (pcr->card_inserted || pcr->card_removed)
  835. schedule_delayed_work(&pcr->carddet_work,
  836. msecs_to_jiffies(200));
  837. spin_unlock(&pcr->lock);
  838. return IRQ_HANDLED;
  839. }
  840. static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
  841. {
  842. pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
  843. __func__, pcr->msi_en, pcr->pci->irq);
  844. if (request_irq(pcr->pci->irq, rtsx_pci_isr,
  845. pcr->msi_en ? 0 : IRQF_SHARED,
  846. DRV_NAME_RTSX_PCI, pcr)) {
  847. dev_err(&(pcr->pci->dev),
  848. "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
  849. pcr->pci->irq);
  850. return -1;
  851. }
  852. pcr->irq = pcr->pci->irq;
  853. pci_intx(pcr->pci, !pcr->msi_en);
  854. return 0;
  855. }
  856. static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
  857. {
  858. if (pcr->ops->set_aspm)
  859. pcr->ops->set_aspm(pcr, true);
  860. else
  861. rtsx_comm_set_aspm(pcr, true);
  862. }
  863. static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
  864. {
  865. struct rtsx_cr_option *option = &pcr->option;
  866. if (option->ltr_enabled) {
  867. u32 latency = option->ltr_l1off_latency;
  868. if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
  869. mdelay(option->l1_snooze_delay);
  870. rtsx_set_ltr_latency(pcr, latency);
  871. }
  872. if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
  873. rtsx_set_l1off_sub_cfg_d0(pcr, 0);
  874. rtsx_enable_aspm(pcr);
  875. }
  876. static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
  877. {
  878. if (pcr->ops->power_saving)
  879. pcr->ops->power_saving(pcr);
  880. else
  881. rtsx_comm_pm_power_saving(pcr);
  882. }
  883. static void rtsx_pci_idle_work(struct work_struct *work)
  884. {
  885. struct delayed_work *dwork = to_delayed_work(work);
  886. struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
  887. pcr_dbg(pcr, "--> %s\n", __func__);
  888. mutex_lock(&pcr->pcr_mutex);
  889. pcr->state = PDEV_STAT_IDLE;
  890. if (pcr->ops->disable_auto_blink)
  891. pcr->ops->disable_auto_blink(pcr);
  892. if (pcr->ops->turn_off_led)
  893. pcr->ops->turn_off_led(pcr);
  894. rtsx_pm_power_saving(pcr);
  895. mutex_unlock(&pcr->pcr_mutex);
  896. }
  897. #ifdef CONFIG_PM
  898. static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
  899. {
  900. if (pcr->ops->turn_off_led)
  901. pcr->ops->turn_off_led(pcr);
  902. rtsx_pci_writel(pcr, RTSX_BIER, 0);
  903. pcr->bier = 0;
  904. rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
  905. rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
  906. if (pcr->ops->force_power_down)
  907. pcr->ops->force_power_down(pcr, pm_state);
  908. }
  909. #endif
  910. void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
  911. {
  912. u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
  913. if (pcr->ops->enable_ocp)
  914. pcr->ops->enable_ocp(pcr);
  915. else
  916. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  917. }
  918. void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
  919. {
  920. u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
  921. if (pcr->ops->disable_ocp)
  922. pcr->ops->disable_ocp(pcr);
  923. else
  924. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  925. }
  926. void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
  927. {
  928. if (pcr->ops->init_ocp) {
  929. pcr->ops->init_ocp(pcr);
  930. } else {
  931. struct rtsx_cr_option *option = &(pcr->option);
  932. if (option->ocp_en) {
  933. u8 val = option->sd_400mA_ocp_thd;
  934. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
  935. rtsx_pci_write_register(pcr, REG_OCPPARA1,
  936. SD_OCP_TIME_MASK, SD_OCP_TIME_800);
  937. rtsx_pci_write_register(pcr, REG_OCPPARA2,
  938. SD_OCP_THD_MASK, val);
  939. rtsx_pci_write_register(pcr, REG_OCPGLITCH,
  940. SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
  941. rtsx_pci_enable_ocp(pcr);
  942. } else {
  943. /* OC power down */
  944. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
  945. OC_POWER_DOWN);
  946. }
  947. }
  948. }
  949. int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
  950. {
  951. if (pcr->ops->get_ocpstat)
  952. return pcr->ops->get_ocpstat(pcr, val);
  953. else
  954. return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
  955. }
  956. void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
  957. {
  958. if (pcr->ops->clear_ocpstat) {
  959. pcr->ops->clear_ocpstat(pcr);
  960. } else {
  961. u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
  962. u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
  963. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  964. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  965. }
  966. }
  967. int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
  968. {
  969. rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
  970. MS_CLK_EN | SD40_CLK_EN, 0);
  971. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  972. rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
  973. msleep(50);
  974. rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
  975. return 0;
  976. }
  977. int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
  978. {
  979. rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
  980. MS_CLK_EN | SD40_CLK_EN, 0);
  981. rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
  982. rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
  983. rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
  984. return 0;
  985. }
  986. static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
  987. {
  988. int err;
  989. pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
  990. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  991. rtsx_pci_enable_bus_int(pcr);
  992. /* Power on SSC */
  993. err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
  994. if (err < 0)
  995. return err;
  996. /* Wait SSC power stable */
  997. udelay(200);
  998. rtsx_pci_disable_aspm(pcr);
  999. if (pcr->ops->optimize_phy) {
  1000. err = pcr->ops->optimize_phy(pcr);
  1001. if (err < 0)
  1002. return err;
  1003. }
  1004. rtsx_pci_init_cmd(pcr);
  1005. /* Set mcu_cnt to 7 to ensure data can be sampled properly */
  1006. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
  1007. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
  1008. /* Disable card clock */
  1009. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
  1010. /* Reset delink mode */
  1011. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
  1012. /* Card driving select */
  1013. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
  1014. 0xFF, pcr->card_drive_sel);
  1015. /* Enable SSC Clock */
  1016. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
  1017. 0xFF, SSC_8X_EN | SSC_SEL_4M);
  1018. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
  1019. /* Disable cd_pwr_save */
  1020. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
  1021. /* Clear Link Ready Interrupt */
  1022. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
  1023. LINK_RDY_INT, LINK_RDY_INT);
  1024. /* Enlarge the estimation window of PERST# glitch
  1025. * to reduce the chance of invalid card interrupt
  1026. */
  1027. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
  1028. /* Update RC oscillator to 400k
  1029. * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
  1030. * 1: 2M 0: 400k
  1031. */
  1032. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
  1033. /* Set interrupt write clear
  1034. * bit 1: U_elbi_if_rd_clr_en
  1035. * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
  1036. * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
  1037. */
  1038. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
  1039. err = rtsx_pci_send_cmd(pcr, 100);
  1040. if (err < 0)
  1041. return err;
  1042. switch (PCI_PID(pcr)) {
  1043. case PID_5250:
  1044. case PID_524A:
  1045. case PID_525A:
  1046. case PID_5260:
  1047. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
  1048. break;
  1049. default:
  1050. break;
  1051. }
  1052. /* Enable clk_request_n to enable clock power management */
  1053. rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
  1054. /* Enter L1 when host tx idle */
  1055. rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
  1056. if (pcr->ops->extra_init_hw) {
  1057. err = pcr->ops->extra_init_hw(pcr);
  1058. if (err < 0)
  1059. return err;
  1060. }
  1061. /* No CD interrupt if probing driver with card inserted.
  1062. * So we need to initialize pcr->card_exist here.
  1063. */
  1064. if (pcr->ops->cd_deglitch)
  1065. pcr->card_exist = pcr->ops->cd_deglitch(pcr);
  1066. else
  1067. pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
  1068. return 0;
  1069. }
  1070. static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
  1071. {
  1072. int err;
  1073. spin_lock_init(&pcr->lock);
  1074. mutex_init(&pcr->pcr_mutex);
  1075. switch (PCI_PID(pcr)) {
  1076. default:
  1077. case 0x5209:
  1078. rts5209_init_params(pcr);
  1079. break;
  1080. case 0x5229:
  1081. rts5229_init_params(pcr);
  1082. break;
  1083. case 0x5289:
  1084. rtl8411_init_params(pcr);
  1085. break;
  1086. case 0x5227:
  1087. rts5227_init_params(pcr);
  1088. break;
  1089. case 0x522A:
  1090. rts522a_init_params(pcr);
  1091. break;
  1092. case 0x5249:
  1093. rts5249_init_params(pcr);
  1094. break;
  1095. case 0x524A:
  1096. rts524a_init_params(pcr);
  1097. break;
  1098. case 0x525A:
  1099. rts525a_init_params(pcr);
  1100. break;
  1101. case 0x5287:
  1102. rtl8411b_init_params(pcr);
  1103. break;
  1104. case 0x5286:
  1105. rtl8402_init_params(pcr);
  1106. break;
  1107. case 0x5260:
  1108. rts5260_init_params(pcr);
  1109. break;
  1110. }
  1111. pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
  1112. PCI_PID(pcr), pcr->ic_version);
  1113. pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
  1114. GFP_KERNEL);
  1115. if (!pcr->slots)
  1116. return -ENOMEM;
  1117. if (pcr->ops->fetch_vendor_settings)
  1118. pcr->ops->fetch_vendor_settings(pcr);
  1119. pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
  1120. pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
  1121. pcr->sd30_drive_sel_1v8);
  1122. pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
  1123. pcr->sd30_drive_sel_3v3);
  1124. pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
  1125. pcr->card_drive_sel);
  1126. pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
  1127. pcr->state = PDEV_STAT_IDLE;
  1128. err = rtsx_pci_init_hw(pcr);
  1129. if (err < 0) {
  1130. kfree(pcr->slots);
  1131. return err;
  1132. }
  1133. return 0;
  1134. }
  1135. static int rtsx_pci_probe(struct pci_dev *pcidev,
  1136. const struct pci_device_id *id)
  1137. {
  1138. struct rtsx_pcr *pcr;
  1139. struct pcr_handle *handle;
  1140. u32 base, len;
  1141. int ret, i, bar = 0;
  1142. dev_dbg(&(pcidev->dev),
  1143. ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
  1144. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
  1145. (int)pcidev->revision);
  1146. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
  1147. if (ret < 0)
  1148. return ret;
  1149. ret = pci_enable_device(pcidev);
  1150. if (ret)
  1151. return ret;
  1152. ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
  1153. if (ret)
  1154. goto disable;
  1155. pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
  1156. if (!pcr) {
  1157. ret = -ENOMEM;
  1158. goto release_pci;
  1159. }
  1160. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1161. if (!handle) {
  1162. ret = -ENOMEM;
  1163. goto free_pcr;
  1164. }
  1165. handle->pcr = pcr;
  1166. idr_preload(GFP_KERNEL);
  1167. spin_lock(&rtsx_pci_lock);
  1168. ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
  1169. if (ret >= 0)
  1170. pcr->id = ret;
  1171. spin_unlock(&rtsx_pci_lock);
  1172. idr_preload_end();
  1173. if (ret < 0)
  1174. goto free_handle;
  1175. pcr->pci = pcidev;
  1176. dev_set_drvdata(&pcidev->dev, handle);
  1177. if (CHK_PCI_PID(pcr, 0x525A))
  1178. bar = 1;
  1179. len = pci_resource_len(pcidev, bar);
  1180. base = pci_resource_start(pcidev, bar);
  1181. pcr->remap_addr = ioremap_nocache(base, len);
  1182. if (!pcr->remap_addr) {
  1183. ret = -ENOMEM;
  1184. goto free_handle;
  1185. }
  1186. pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
  1187. RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
  1188. GFP_KERNEL);
  1189. if (pcr->rtsx_resv_buf == NULL) {
  1190. ret = -ENXIO;
  1191. goto unmap;
  1192. }
  1193. pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
  1194. pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
  1195. pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
  1196. pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
  1197. pcr->card_inserted = 0;
  1198. pcr->card_removed = 0;
  1199. INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
  1200. INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
  1201. pcr->msi_en = msi_en;
  1202. if (pcr->msi_en) {
  1203. ret = pci_enable_msi(pcidev);
  1204. if (ret)
  1205. pcr->msi_en = false;
  1206. }
  1207. ret = rtsx_pci_acquire_irq(pcr);
  1208. if (ret < 0)
  1209. goto disable_msi;
  1210. pci_set_master(pcidev);
  1211. synchronize_irq(pcr->irq);
  1212. ret = rtsx_pci_init_chip(pcr);
  1213. if (ret < 0)
  1214. goto disable_irq;
  1215. for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
  1216. rtsx_pcr_cells[i].platform_data = handle;
  1217. rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
  1218. }
  1219. ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
  1220. ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
  1221. if (ret < 0)
  1222. goto free_slots;
  1223. schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
  1224. return 0;
  1225. free_slots:
  1226. kfree(pcr->slots);
  1227. disable_irq:
  1228. free_irq(pcr->irq, (void *)pcr);
  1229. disable_msi:
  1230. if (pcr->msi_en)
  1231. pci_disable_msi(pcr->pci);
  1232. dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
  1233. pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
  1234. unmap:
  1235. iounmap(pcr->remap_addr);
  1236. free_handle:
  1237. kfree(handle);
  1238. free_pcr:
  1239. kfree(pcr);
  1240. release_pci:
  1241. pci_release_regions(pcidev);
  1242. disable:
  1243. pci_disable_device(pcidev);
  1244. return ret;
  1245. }
  1246. static void rtsx_pci_remove(struct pci_dev *pcidev)
  1247. {
  1248. struct pcr_handle *handle = pci_get_drvdata(pcidev);
  1249. struct rtsx_pcr *pcr = handle->pcr;
  1250. pcr->remove_pci = true;
  1251. /* Disable interrupts at the pcr level */
  1252. spin_lock_irq(&pcr->lock);
  1253. rtsx_pci_writel(pcr, RTSX_BIER, 0);
  1254. pcr->bier = 0;
  1255. spin_unlock_irq(&pcr->lock);
  1256. cancel_delayed_work_sync(&pcr->carddet_work);
  1257. cancel_delayed_work_sync(&pcr->idle_work);
  1258. mfd_remove_devices(&pcidev->dev);
  1259. dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
  1260. pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
  1261. free_irq(pcr->irq, (void *)pcr);
  1262. if (pcr->msi_en)
  1263. pci_disable_msi(pcr->pci);
  1264. iounmap(pcr->remap_addr);
  1265. pci_release_regions(pcidev);
  1266. pci_disable_device(pcidev);
  1267. spin_lock(&rtsx_pci_lock);
  1268. idr_remove(&rtsx_pci_idr, pcr->id);
  1269. spin_unlock(&rtsx_pci_lock);
  1270. kfree(pcr->slots);
  1271. kfree(pcr);
  1272. kfree(handle);
  1273. dev_dbg(&(pcidev->dev),
  1274. ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
  1275. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
  1276. }
  1277. #ifdef CONFIG_PM
  1278. static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
  1279. {
  1280. struct pcr_handle *handle;
  1281. struct rtsx_pcr *pcr;
  1282. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  1283. handle = pci_get_drvdata(pcidev);
  1284. pcr = handle->pcr;
  1285. cancel_delayed_work(&pcr->carddet_work);
  1286. cancel_delayed_work(&pcr->idle_work);
  1287. mutex_lock(&pcr->pcr_mutex);
  1288. rtsx_pci_power_off(pcr, HOST_ENTER_S3);
  1289. pci_save_state(pcidev);
  1290. pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
  1291. pci_disable_device(pcidev);
  1292. pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
  1293. mutex_unlock(&pcr->pcr_mutex);
  1294. return 0;
  1295. }
  1296. static int rtsx_pci_resume(struct pci_dev *pcidev)
  1297. {
  1298. struct pcr_handle *handle;
  1299. struct rtsx_pcr *pcr;
  1300. int ret = 0;
  1301. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  1302. handle = pci_get_drvdata(pcidev);
  1303. pcr = handle->pcr;
  1304. mutex_lock(&pcr->pcr_mutex);
  1305. pci_set_power_state(pcidev, PCI_D0);
  1306. pci_restore_state(pcidev);
  1307. ret = pci_enable_device(pcidev);
  1308. if (ret)
  1309. goto out;
  1310. pci_set_master(pcidev);
  1311. ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
  1312. if (ret)
  1313. goto out;
  1314. ret = rtsx_pci_init_hw(pcr);
  1315. if (ret)
  1316. goto out;
  1317. schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
  1318. out:
  1319. mutex_unlock(&pcr->pcr_mutex);
  1320. return ret;
  1321. }
  1322. static void rtsx_pci_shutdown(struct pci_dev *pcidev)
  1323. {
  1324. struct pcr_handle *handle;
  1325. struct rtsx_pcr *pcr;
  1326. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  1327. handle = pci_get_drvdata(pcidev);
  1328. pcr = handle->pcr;
  1329. rtsx_pci_power_off(pcr, HOST_ENTER_S1);
  1330. pci_disable_device(pcidev);
  1331. free_irq(pcr->irq, (void *)pcr);
  1332. if (pcr->msi_en)
  1333. pci_disable_msi(pcr->pci);
  1334. }
  1335. #else /* CONFIG_PM */
  1336. #define rtsx_pci_suspend NULL
  1337. #define rtsx_pci_resume NULL
  1338. #define rtsx_pci_shutdown NULL
  1339. #endif /* CONFIG_PM */
  1340. static struct pci_driver rtsx_pci_driver = {
  1341. .name = DRV_NAME_RTSX_PCI,
  1342. .id_table = rtsx_pci_ids,
  1343. .probe = rtsx_pci_probe,
  1344. .remove = rtsx_pci_remove,
  1345. .suspend = rtsx_pci_suspend,
  1346. .resume = rtsx_pci_resume,
  1347. .shutdown = rtsx_pci_shutdown,
  1348. };
  1349. module_pci_driver(rtsx_pci_driver);
  1350. MODULE_LICENSE("GPL");
  1351. MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
  1352. MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");