eeprom_93xx46.c 12 KB

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  1. /*
  2. * Driver for 93xx46 EEPROMs
  3. *
  4. * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/mutex.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/slab.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/nvmem-provider.h>
  22. #include <linux/eeprom_93xx46.h>
  23. #define OP_START 0x4
  24. #define OP_WRITE (OP_START | 0x1)
  25. #define OP_READ (OP_START | 0x2)
  26. #define ADDR_EWDS 0x00
  27. #define ADDR_ERAL 0x20
  28. #define ADDR_EWEN 0x30
  29. struct eeprom_93xx46_devtype_data {
  30. unsigned int quirks;
  31. };
  32. static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
  33. .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
  34. EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
  35. };
  36. static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = {
  37. .quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE,
  38. };
  39. struct eeprom_93xx46_dev {
  40. struct spi_device *spi;
  41. struct eeprom_93xx46_platform_data *pdata;
  42. struct mutex lock;
  43. struct nvmem_config nvmem_config;
  44. struct nvmem_device *nvmem;
  45. int addrlen;
  46. int size;
  47. };
  48. static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
  49. {
  50. return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
  51. }
  52. static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
  53. {
  54. return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
  55. }
  56. static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
  57. {
  58. return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
  59. }
  60. static int eeprom_93xx46_read(void *priv, unsigned int off,
  61. void *val, size_t count)
  62. {
  63. struct eeprom_93xx46_dev *edev = priv;
  64. char *buf = val;
  65. int err = 0;
  66. if (unlikely(off >= edev->size))
  67. return 0;
  68. if ((off + count) > edev->size)
  69. count = edev->size - off;
  70. if (unlikely(!count))
  71. return count;
  72. mutex_lock(&edev->lock);
  73. if (edev->pdata->prepare)
  74. edev->pdata->prepare(edev);
  75. while (count) {
  76. struct spi_message m;
  77. struct spi_transfer t[2] = { { 0 } };
  78. u16 cmd_addr = OP_READ << edev->addrlen;
  79. size_t nbytes = count;
  80. int bits;
  81. if (edev->addrlen == 7) {
  82. cmd_addr |= off & 0x7f;
  83. bits = 10;
  84. if (has_quirk_single_word_read(edev))
  85. nbytes = 1;
  86. } else {
  87. cmd_addr |= (off >> 1) & 0x3f;
  88. bits = 9;
  89. if (has_quirk_single_word_read(edev))
  90. nbytes = 2;
  91. }
  92. dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
  93. cmd_addr, edev->spi->max_speed_hz);
  94. if (has_quirk_extra_read_cycle(edev)) {
  95. cmd_addr <<= 1;
  96. bits += 1;
  97. }
  98. spi_message_init(&m);
  99. t[0].tx_buf = (char *)&cmd_addr;
  100. t[0].len = 2;
  101. t[0].bits_per_word = bits;
  102. spi_message_add_tail(&t[0], &m);
  103. t[1].rx_buf = buf;
  104. t[1].len = count;
  105. t[1].bits_per_word = 8;
  106. spi_message_add_tail(&t[1], &m);
  107. err = spi_sync(edev->spi, &m);
  108. /* have to wait at least Tcsl ns */
  109. ndelay(250);
  110. if (err) {
  111. dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
  112. nbytes, (int)off, err);
  113. break;
  114. }
  115. buf += nbytes;
  116. off += nbytes;
  117. count -= nbytes;
  118. }
  119. if (edev->pdata->finish)
  120. edev->pdata->finish(edev);
  121. mutex_unlock(&edev->lock);
  122. return err;
  123. }
  124. static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
  125. {
  126. struct spi_message m;
  127. struct spi_transfer t;
  128. int bits, ret;
  129. u16 cmd_addr;
  130. cmd_addr = OP_START << edev->addrlen;
  131. if (edev->addrlen == 7) {
  132. cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
  133. bits = 10;
  134. } else {
  135. cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS);
  136. bits = 9;
  137. }
  138. if (has_quirk_instruction_length(edev)) {
  139. cmd_addr <<= 2;
  140. bits += 2;
  141. }
  142. dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
  143. is_on ? "en" : "ds", cmd_addr, bits);
  144. spi_message_init(&m);
  145. memset(&t, 0, sizeof(t));
  146. t.tx_buf = &cmd_addr;
  147. t.len = 2;
  148. t.bits_per_word = bits;
  149. spi_message_add_tail(&t, &m);
  150. mutex_lock(&edev->lock);
  151. if (edev->pdata->prepare)
  152. edev->pdata->prepare(edev);
  153. ret = spi_sync(edev->spi, &m);
  154. /* have to wait at least Tcsl ns */
  155. ndelay(250);
  156. if (ret)
  157. dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
  158. is_on ? "en" : "dis", ret);
  159. if (edev->pdata->finish)
  160. edev->pdata->finish(edev);
  161. mutex_unlock(&edev->lock);
  162. return ret;
  163. }
  164. static ssize_t
  165. eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
  166. const char *buf, unsigned off)
  167. {
  168. struct spi_message m;
  169. struct spi_transfer t[2];
  170. int bits, data_len, ret;
  171. u16 cmd_addr;
  172. cmd_addr = OP_WRITE << edev->addrlen;
  173. if (edev->addrlen == 7) {
  174. cmd_addr |= off & 0x7f;
  175. bits = 10;
  176. data_len = 1;
  177. } else {
  178. cmd_addr |= (off >> 1) & 0x3f;
  179. bits = 9;
  180. data_len = 2;
  181. }
  182. dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
  183. spi_message_init(&m);
  184. memset(t, 0, sizeof(t));
  185. t[0].tx_buf = (char *)&cmd_addr;
  186. t[0].len = 2;
  187. t[0].bits_per_word = bits;
  188. spi_message_add_tail(&t[0], &m);
  189. t[1].tx_buf = buf;
  190. t[1].len = data_len;
  191. t[1].bits_per_word = 8;
  192. spi_message_add_tail(&t[1], &m);
  193. ret = spi_sync(edev->spi, &m);
  194. /* have to wait program cycle time Twc ms */
  195. mdelay(6);
  196. return ret;
  197. }
  198. static int eeprom_93xx46_write(void *priv, unsigned int off,
  199. void *val, size_t count)
  200. {
  201. struct eeprom_93xx46_dev *edev = priv;
  202. char *buf = val;
  203. int i, ret, step = 1;
  204. if (unlikely(off >= edev->size))
  205. return -EFBIG;
  206. if ((off + count) > edev->size)
  207. count = edev->size - off;
  208. if (unlikely(!count))
  209. return count;
  210. /* only write even number of bytes on 16-bit devices */
  211. if (edev->addrlen == 6) {
  212. step = 2;
  213. count &= ~1;
  214. }
  215. /* erase/write enable */
  216. ret = eeprom_93xx46_ew(edev, 1);
  217. if (ret)
  218. return ret;
  219. mutex_lock(&edev->lock);
  220. if (edev->pdata->prepare)
  221. edev->pdata->prepare(edev);
  222. for (i = 0; i < count; i += step) {
  223. ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
  224. if (ret) {
  225. dev_err(&edev->spi->dev, "write failed at %d: %d\n",
  226. (int)off + i, ret);
  227. break;
  228. }
  229. }
  230. if (edev->pdata->finish)
  231. edev->pdata->finish(edev);
  232. mutex_unlock(&edev->lock);
  233. /* erase/write disable */
  234. eeprom_93xx46_ew(edev, 0);
  235. return ret;
  236. }
  237. static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
  238. {
  239. struct eeprom_93xx46_platform_data *pd = edev->pdata;
  240. struct spi_message m;
  241. struct spi_transfer t;
  242. int bits, ret;
  243. u16 cmd_addr;
  244. cmd_addr = OP_START << edev->addrlen;
  245. if (edev->addrlen == 7) {
  246. cmd_addr |= ADDR_ERAL << 1;
  247. bits = 10;
  248. } else {
  249. cmd_addr |= ADDR_ERAL;
  250. bits = 9;
  251. }
  252. if (has_quirk_instruction_length(edev)) {
  253. cmd_addr <<= 2;
  254. bits += 2;
  255. }
  256. dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
  257. spi_message_init(&m);
  258. memset(&t, 0, sizeof(t));
  259. t.tx_buf = &cmd_addr;
  260. t.len = 2;
  261. t.bits_per_word = bits;
  262. spi_message_add_tail(&t, &m);
  263. mutex_lock(&edev->lock);
  264. if (edev->pdata->prepare)
  265. edev->pdata->prepare(edev);
  266. ret = spi_sync(edev->spi, &m);
  267. if (ret)
  268. dev_err(&edev->spi->dev, "erase error %d\n", ret);
  269. /* have to wait erase cycle time Tec ms */
  270. mdelay(6);
  271. if (pd->finish)
  272. pd->finish(edev);
  273. mutex_unlock(&edev->lock);
  274. return ret;
  275. }
  276. static ssize_t eeprom_93xx46_store_erase(struct device *dev,
  277. struct device_attribute *attr,
  278. const char *buf, size_t count)
  279. {
  280. struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
  281. int erase = 0, ret;
  282. sscanf(buf, "%d", &erase);
  283. if (erase) {
  284. ret = eeprom_93xx46_ew(edev, 1);
  285. if (ret)
  286. return ret;
  287. ret = eeprom_93xx46_eral(edev);
  288. if (ret)
  289. return ret;
  290. ret = eeprom_93xx46_ew(edev, 0);
  291. if (ret)
  292. return ret;
  293. }
  294. return count;
  295. }
  296. static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
  297. static void select_assert(void *context)
  298. {
  299. struct eeprom_93xx46_dev *edev = context;
  300. gpiod_set_value_cansleep(edev->pdata->select, 1);
  301. }
  302. static void select_deassert(void *context)
  303. {
  304. struct eeprom_93xx46_dev *edev = context;
  305. gpiod_set_value_cansleep(edev->pdata->select, 0);
  306. }
  307. static const struct of_device_id eeprom_93xx46_of_table[] = {
  308. { .compatible = "eeprom-93xx46", },
  309. { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
  310. { .compatible = "microchip,93lc46b", .data = &microchip_93lc46b_data, },
  311. {}
  312. };
  313. MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
  314. static int eeprom_93xx46_probe_dt(struct spi_device *spi)
  315. {
  316. const struct of_device_id *of_id =
  317. of_match_device(eeprom_93xx46_of_table, &spi->dev);
  318. struct device_node *np = spi->dev.of_node;
  319. struct eeprom_93xx46_platform_data *pd;
  320. u32 tmp;
  321. int ret;
  322. pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
  323. if (!pd)
  324. return -ENOMEM;
  325. ret = of_property_read_u32(np, "data-size", &tmp);
  326. if (ret < 0) {
  327. dev_err(&spi->dev, "data-size property not found\n");
  328. return ret;
  329. }
  330. if (tmp == 8) {
  331. pd->flags |= EE_ADDR8;
  332. } else if (tmp == 16) {
  333. pd->flags |= EE_ADDR16;
  334. } else {
  335. dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
  336. return -EINVAL;
  337. }
  338. if (of_property_read_bool(np, "read-only"))
  339. pd->flags |= EE_READONLY;
  340. pd->select = devm_gpiod_get_optional(&spi->dev, "select",
  341. GPIOD_OUT_LOW);
  342. if (IS_ERR(pd->select))
  343. return PTR_ERR(pd->select);
  344. pd->prepare = select_assert;
  345. pd->finish = select_deassert;
  346. gpiod_direction_output(pd->select, 0);
  347. if (of_id->data) {
  348. const struct eeprom_93xx46_devtype_data *data = of_id->data;
  349. pd->quirks = data->quirks;
  350. }
  351. spi->dev.platform_data = pd;
  352. return 0;
  353. }
  354. static int eeprom_93xx46_probe(struct spi_device *spi)
  355. {
  356. struct eeprom_93xx46_platform_data *pd;
  357. struct eeprom_93xx46_dev *edev;
  358. int err;
  359. if (spi->dev.of_node) {
  360. err = eeprom_93xx46_probe_dt(spi);
  361. if (err < 0)
  362. return err;
  363. }
  364. pd = spi->dev.platform_data;
  365. if (!pd) {
  366. dev_err(&spi->dev, "missing platform data\n");
  367. return -ENODEV;
  368. }
  369. edev = kzalloc(sizeof(*edev), GFP_KERNEL);
  370. if (!edev)
  371. return -ENOMEM;
  372. if (pd->flags & EE_ADDR8)
  373. edev->addrlen = 7;
  374. else if (pd->flags & EE_ADDR16)
  375. edev->addrlen = 6;
  376. else {
  377. dev_err(&spi->dev, "unspecified address type\n");
  378. err = -EINVAL;
  379. goto fail;
  380. }
  381. mutex_init(&edev->lock);
  382. edev->spi = spi;
  383. edev->pdata = pd;
  384. edev->size = 128;
  385. edev->nvmem_config.name = dev_name(&spi->dev);
  386. edev->nvmem_config.dev = &spi->dev;
  387. edev->nvmem_config.read_only = pd->flags & EE_READONLY;
  388. edev->nvmem_config.root_only = true;
  389. edev->nvmem_config.owner = THIS_MODULE;
  390. edev->nvmem_config.compat = true;
  391. edev->nvmem_config.base_dev = &spi->dev;
  392. edev->nvmem_config.reg_read = eeprom_93xx46_read;
  393. edev->nvmem_config.reg_write = eeprom_93xx46_write;
  394. edev->nvmem_config.priv = edev;
  395. edev->nvmem_config.stride = 4;
  396. edev->nvmem_config.word_size = 1;
  397. edev->nvmem_config.size = edev->size;
  398. edev->nvmem = nvmem_register(&edev->nvmem_config);
  399. if (IS_ERR(edev->nvmem)) {
  400. err = PTR_ERR(edev->nvmem);
  401. goto fail;
  402. }
  403. dev_info(&spi->dev, "%d-bit eeprom %s\n",
  404. (pd->flags & EE_ADDR8) ? 8 : 16,
  405. (pd->flags & EE_READONLY) ? "(readonly)" : "");
  406. if (!(pd->flags & EE_READONLY)) {
  407. if (device_create_file(&spi->dev, &dev_attr_erase))
  408. dev_err(&spi->dev, "can't create erase interface\n");
  409. }
  410. spi_set_drvdata(spi, edev);
  411. return 0;
  412. fail:
  413. kfree(edev);
  414. return err;
  415. }
  416. static int eeprom_93xx46_remove(struct spi_device *spi)
  417. {
  418. struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
  419. nvmem_unregister(edev->nvmem);
  420. if (!(edev->pdata->flags & EE_READONLY))
  421. device_remove_file(&spi->dev, &dev_attr_erase);
  422. kfree(edev);
  423. return 0;
  424. }
  425. static struct spi_driver eeprom_93xx46_driver = {
  426. .driver = {
  427. .name = "93xx46",
  428. .of_match_table = of_match_ptr(eeprom_93xx46_of_table),
  429. },
  430. .probe = eeprom_93xx46_probe,
  431. .remove = eeprom_93xx46_remove,
  432. };
  433. module_spi_driver(eeprom_93xx46_driver);
  434. MODULE_LICENSE("GPL");
  435. MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
  436. MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
  437. MODULE_ALIAS("spi:93xx46");
  438. MODULE_ALIAS("spi:eeprom-93xx46");