ksz_9477_reg.h 42 KB

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  1. /*
  2. * Microchip KSZ9477 register definitions
  3. *
  4. * Copyright (C) 2017
  5. *
  6. * Permission to use, copy, modify, and/or distribute this software for any
  7. * purpose with or without fee is hereby granted, provided that the above
  8. * copyright notice and this permission notice appear in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef __KSZ9477_REGS_H
  19. #define __KSZ9477_REGS_H
  20. #define KS_PRIO_M 0x7
  21. #define KS_PRIO_S 4
  22. /* 0 - Operation */
  23. #define REG_CHIP_ID0__1 0x0000
  24. #define REG_CHIP_ID1__1 0x0001
  25. #define FAMILY_ID 0x95
  26. #define FAMILY_ID_94 0x94
  27. #define FAMILY_ID_95 0x95
  28. #define FAMILY_ID_85 0x85
  29. #define FAMILY_ID_98 0x98
  30. #define FAMILY_ID_88 0x88
  31. #define REG_CHIP_ID2__1 0x0002
  32. #define CHIP_ID_63 0x63
  33. #define CHIP_ID_66 0x66
  34. #define CHIP_ID_67 0x67
  35. #define CHIP_ID_77 0x77
  36. #define CHIP_ID_93 0x93
  37. #define CHIP_ID_96 0x96
  38. #define CHIP_ID_97 0x97
  39. #define REG_CHIP_ID3__1 0x0003
  40. #define SWITCH_REVISION_M 0x0F
  41. #define SWITCH_REVISION_S 4
  42. #define SWITCH_RESET 0x01
  43. #define REG_SW_PME_CTRL 0x0006
  44. #define PME_ENABLE BIT(1)
  45. #define PME_POLARITY BIT(0)
  46. #define REG_GLOBAL_OPTIONS 0x000F
  47. #define SW_GIGABIT_ABLE BIT(6)
  48. #define SW_REDUNDANCY_ABLE BIT(5)
  49. #define SW_AVB_ABLE BIT(4)
  50. #define SW_9567_RL_5_2 0xC
  51. #define SW_9477_SL_5_2 0xD
  52. #define SW_9896_GL_5_1 0xB
  53. #define SW_9896_RL_5_1 0x8
  54. #define SW_9896_SL_5_1 0x9
  55. #define SW_9895_GL_4_1 0x7
  56. #define SW_9895_RL_4_1 0x4
  57. #define SW_9895_SL_4_1 0x5
  58. #define SW_9896_RL_4_2 0x6
  59. #define SW_9893_RL_2_1 0x0
  60. #define SW_9893_SL_2_1 0x1
  61. #define SW_9893_GL_2_1 0x3
  62. #define SW_QW_ABLE BIT(5)
  63. #define SW_9893_RN_2_1 0xC
  64. #define REG_SW_INT_STATUS__4 0x0010
  65. #define REG_SW_INT_MASK__4 0x0014
  66. #define LUE_INT BIT(31)
  67. #define TRIG_TS_INT BIT(30)
  68. #define APB_TIMEOUT_INT BIT(29)
  69. #define SWITCH_INT_MASK (TRIG_TS_INT | APB_TIMEOUT_INT)
  70. #define REG_SW_PORT_INT_STATUS__4 0x0018
  71. #define REG_SW_PORT_INT_MASK__4 0x001C
  72. #define REG_SW_PHY_INT_STATUS 0x0020
  73. #define REG_SW_PHY_INT_ENABLE 0x0024
  74. /* 1 - Global */
  75. #define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100
  76. #define SW_SPARE_REG_2 BIT(7)
  77. #define SW_SPARE_REG_1 BIT(6)
  78. #define SW_SPARE_REG_0 BIT(5)
  79. #define SW_BIG_ENDIAN BIT(4)
  80. #define SPI_AUTO_EDGE_DETECTION BIT(1)
  81. #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
  82. #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
  83. #define SW_ENABLE_REFCLKO BIT(1)
  84. #define SW_REFCLKO_IS_125MHZ BIT(0)
  85. #define REG_SW_IBA__4 0x0104
  86. #define SW_IBA_ENABLE BIT(31)
  87. #define SW_IBA_DA_MATCH BIT(30)
  88. #define SW_IBA_INIT BIT(29)
  89. #define SW_IBA_QID_M 0xF
  90. #define SW_IBA_QID_S 22
  91. #define SW_IBA_PORT_M 0x2F
  92. #define SW_IBA_PORT_S 16
  93. #define SW_IBA_FRAME_TPID_M 0xFFFF
  94. #define REG_SW_APB_TIMEOUT_ADDR__4 0x0108
  95. #define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
  96. #define REG_SW_IBA_SYNC__1 0x010C
  97. #define REG_SW_IO_STRENGTH__1 0x010D
  98. #define SW_DRIVE_STRENGTH_M 0x7
  99. #define SW_DRIVE_STRENGTH_2MA 0
  100. #define SW_DRIVE_STRENGTH_4MA 1
  101. #define SW_DRIVE_STRENGTH_8MA 2
  102. #define SW_DRIVE_STRENGTH_12MA 3
  103. #define SW_DRIVE_STRENGTH_16MA 4
  104. #define SW_DRIVE_STRENGTH_20MA 5
  105. #define SW_DRIVE_STRENGTH_24MA 6
  106. #define SW_DRIVE_STRENGTH_28MA 7
  107. #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
  108. #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
  109. #define REG_SW_IBA_STATUS__4 0x0110
  110. #define SW_IBA_REQ BIT(31)
  111. #define SW_IBA_RESP BIT(30)
  112. #define SW_IBA_DA_MISMATCH BIT(14)
  113. #define SW_IBA_FMT_MISMATCH BIT(13)
  114. #define SW_IBA_CODE_ERROR BIT(12)
  115. #define SW_IBA_CMD_ERROR BIT(11)
  116. #define SW_IBA_CMD_LOC_M (BIT(6) - 1)
  117. #define REG_SW_IBA_STATES__4 0x0114
  118. #define SW_IBA_BUF_STATE_S 30
  119. #define SW_IBA_CMD_STATE_S 28
  120. #define SW_IBA_RESP_STATE_S 26
  121. #define SW_IBA_STATE_M 0x3
  122. #define SW_IBA_PACKET_SIZE_M 0x7F
  123. #define SW_IBA_PACKET_SIZE_S 16
  124. #define SW_IBA_FMT_ID_M 0xFFFF
  125. #define REG_SW_IBA_RESULT__4 0x0118
  126. #define SW_IBA_SIZE_S 24
  127. #define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
  128. /* 2 - PHY */
  129. #define REG_SW_POWER_MANAGEMENT_CTRL 0x0201
  130. #define SW_PLL_POWER_DOWN BIT(5)
  131. #define SW_POWER_DOWN_MODE 0x3
  132. #define SW_ENERGY_DETECTION 1
  133. #define SW_SOFT_POWER_DOWN 2
  134. #define SW_POWER_SAVING 3
  135. /* 3 - Operation Control */
  136. #define REG_SW_OPERATION 0x0300
  137. #define SW_DOUBLE_TAG BIT(7)
  138. #define SW_RESET BIT(1)
  139. #define SW_START BIT(0)
  140. #define REG_SW_MAC_ADDR_0 0x0302
  141. #define REG_SW_MAC_ADDR_1 0x0303
  142. #define REG_SW_MAC_ADDR_2 0x0304
  143. #define REG_SW_MAC_ADDR_3 0x0305
  144. #define REG_SW_MAC_ADDR_4 0x0306
  145. #define REG_SW_MAC_ADDR_5 0x0307
  146. #define REG_SW_MTU__2 0x0308
  147. #define REG_SW_ISP_TPID__2 0x030A
  148. #define REG_SW_HSR_TPID__2 0x030C
  149. #define REG_AVB_STRATEGY__2 0x030E
  150. #define SW_SHAPING_CREDIT_ACCT BIT(1)
  151. #define SW_POLICING_CREDIT_ACCT BIT(0)
  152. #define REG_SW_LUE_CTRL_0 0x0310
  153. #define SW_VLAN_ENABLE BIT(7)
  154. #define SW_DROP_INVALID_VID BIT(6)
  155. #define SW_AGE_CNT_M 0x7
  156. #define SW_AGE_CNT_S 3
  157. #define SW_RESV_MCAST_ENABLE BIT(2)
  158. #define SW_HASH_OPTION_M 0x03
  159. #define SW_HASH_OPTION_CRC 1
  160. #define SW_HASH_OPTION_XOR 2
  161. #define SW_HASH_OPTION_DIRECT 3
  162. #define REG_SW_LUE_CTRL_1 0x0311
  163. #define UNICAST_LEARN_DISABLE BIT(7)
  164. #define SW_SRC_ADDR_FILTER BIT(6)
  165. #define SW_FLUSH_STP_TABLE BIT(5)
  166. #define SW_FLUSH_MSTP_TABLE BIT(4)
  167. #define SW_FWD_MCAST_SRC_ADDR BIT(3)
  168. #define SW_AGING_ENABLE BIT(2)
  169. #define SW_FAST_AGING BIT(1)
  170. #define SW_LINK_AUTO_AGING BIT(0)
  171. #define REG_SW_LUE_CTRL_2 0x0312
  172. #define SW_TRAP_DOUBLE_TAG BIT(6)
  173. #define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
  174. #define SW_EGRESS_VLAN_FILTER_STA BIT(4)
  175. #define SW_FLUSH_OPTION_M 0x3
  176. #define SW_FLUSH_OPTION_S 2
  177. #define SW_FLUSH_OPTION_DYN_MAC 1
  178. #define SW_FLUSH_OPTION_STA_MAC 2
  179. #define SW_FLUSH_OPTION_BOTH 3
  180. #define SW_PRIO_M 0x3
  181. #define SW_PRIO_DA 0
  182. #define SW_PRIO_SA 1
  183. #define SW_PRIO_HIGHEST_DA_SA 2
  184. #define SW_PRIO_LOWEST_DA_SA 3
  185. #define REG_SW_LUE_CTRL_3 0x0313
  186. #define REG_SW_LUE_INT_STATUS 0x0314
  187. #define REG_SW_LUE_INT_ENABLE 0x0315
  188. #define LEARN_FAIL_INT BIT(2)
  189. #define ALMOST_FULL_INT BIT(1)
  190. #define WRITE_FAIL_INT BIT(0)
  191. #define REG_SW_LUE_INDEX_0__2 0x0316
  192. #define ENTRY_INDEX_M 0x0FFF
  193. #define REG_SW_LUE_INDEX_1__2 0x0318
  194. #define FAIL_INDEX_M 0x03FF
  195. #define REG_SW_LUE_INDEX_2__2 0x031A
  196. #define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320
  197. #define SW_UNK_UCAST_ENABLE BIT(31)
  198. #define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324
  199. #define SW_UNK_MCAST_ENABLE BIT(31)
  200. #define REG_SW_LUE_UNK_VID_CTRL__4 0x0328
  201. #define SW_UNK_VID_ENABLE BIT(31)
  202. #define REG_SW_MAC_CTRL_0 0x0330
  203. #define SW_NEW_BACKOFF BIT(7)
  204. #define SW_CHECK_LENGTH BIT(3)
  205. #define SW_PAUSE_UNH_MODE BIT(1)
  206. #define SW_AGGR_BACKOFF BIT(0)
  207. #define REG_SW_MAC_CTRL_1 0x0331
  208. #define MULTICAST_STORM_DISABLE BIT(6)
  209. #define SW_BACK_PRESSURE BIT(5)
  210. #define FAIR_FLOW_CTRL BIT(4)
  211. #define NO_EXC_COLLISION_DROP BIT(3)
  212. #define SW_JUMBO_PACKET BIT(2)
  213. #define SW_LEGAL_PACKET_DISABLE BIT(1)
  214. #define SW_PASS_SHORT_FRAME BIT(0)
  215. #define REG_SW_MAC_CTRL_2 0x0332
  216. #define SW_REPLACE_VID BIT(3)
  217. #define BROADCAST_STORM_RATE_HI 0x07
  218. #define REG_SW_MAC_CTRL_3 0x0333
  219. #define BROADCAST_STORM_RATE_LO 0xFF
  220. #define BROADCAST_STORM_RATE 0x07FF
  221. #define REG_SW_MAC_CTRL_4 0x0334
  222. #define SW_PASS_PAUSE BIT(3)
  223. #define REG_SW_MAC_CTRL_5 0x0335
  224. #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
  225. #define REG_SW_MAC_CTRL_6 0x0336
  226. #define SW_MIB_COUNTER_FLUSH BIT(7)
  227. #define SW_MIB_COUNTER_FREEZE BIT(6)
  228. #define REG_SW_MAC_802_1P_MAP_0 0x0338
  229. #define REG_SW_MAC_802_1P_MAP_1 0x0339
  230. #define REG_SW_MAC_802_1P_MAP_2 0x033A
  231. #define REG_SW_MAC_802_1P_MAP_3 0x033B
  232. #define SW_802_1P_MAP_M KS_PRIO_M
  233. #define SW_802_1P_MAP_S KS_PRIO_S
  234. #define REG_SW_MAC_ISP_CTRL 0x033C
  235. #define REG_SW_MAC_TOS_CTRL 0x033E
  236. #define SW_TOS_DSCP_REMARK BIT(1)
  237. #define SW_TOS_DSCP_REMAP BIT(0)
  238. #define REG_SW_MAC_TOS_PRIO_0 0x0340
  239. #define REG_SW_MAC_TOS_PRIO_1 0x0341
  240. #define REG_SW_MAC_TOS_PRIO_2 0x0342
  241. #define REG_SW_MAC_TOS_PRIO_3 0x0343
  242. #define REG_SW_MAC_TOS_PRIO_4 0x0344
  243. #define REG_SW_MAC_TOS_PRIO_5 0x0345
  244. #define REG_SW_MAC_TOS_PRIO_6 0x0346
  245. #define REG_SW_MAC_TOS_PRIO_7 0x0347
  246. #define REG_SW_MAC_TOS_PRIO_8 0x0348
  247. #define REG_SW_MAC_TOS_PRIO_9 0x0349
  248. #define REG_SW_MAC_TOS_PRIO_10 0x034A
  249. #define REG_SW_MAC_TOS_PRIO_11 0x034B
  250. #define REG_SW_MAC_TOS_PRIO_12 0x034C
  251. #define REG_SW_MAC_TOS_PRIO_13 0x034D
  252. #define REG_SW_MAC_TOS_PRIO_14 0x034E
  253. #define REG_SW_MAC_TOS_PRIO_15 0x034F
  254. #define REG_SW_MAC_TOS_PRIO_16 0x0350
  255. #define REG_SW_MAC_TOS_PRIO_17 0x0351
  256. #define REG_SW_MAC_TOS_PRIO_18 0x0352
  257. #define REG_SW_MAC_TOS_PRIO_19 0x0353
  258. #define REG_SW_MAC_TOS_PRIO_20 0x0354
  259. #define REG_SW_MAC_TOS_PRIO_21 0x0355
  260. #define REG_SW_MAC_TOS_PRIO_22 0x0356
  261. #define REG_SW_MAC_TOS_PRIO_23 0x0357
  262. #define REG_SW_MAC_TOS_PRIO_24 0x0358
  263. #define REG_SW_MAC_TOS_PRIO_25 0x0359
  264. #define REG_SW_MAC_TOS_PRIO_26 0x035A
  265. #define REG_SW_MAC_TOS_PRIO_27 0x035B
  266. #define REG_SW_MAC_TOS_PRIO_28 0x035C
  267. #define REG_SW_MAC_TOS_PRIO_29 0x035D
  268. #define REG_SW_MAC_TOS_PRIO_30 0x035E
  269. #define REG_SW_MAC_TOS_PRIO_31 0x035F
  270. #define REG_SW_MRI_CTRL_0 0x0370
  271. #define SW_IGMP_SNOOP BIT(6)
  272. #define SW_IPV6_MLD_OPTION BIT(3)
  273. #define SW_IPV6_MLD_SNOOP BIT(2)
  274. #define SW_MIRROR_RX_TX BIT(0)
  275. #define REG_SW_CLASS_D_IP_CTRL__4 0x0374
  276. #define SW_CLASS_D_IP_ENABLE BIT(31)
  277. #define REG_SW_MRI_CTRL_8 0x0378
  278. #define SW_NO_COLOR_S 6
  279. #define SW_RED_COLOR_S 4
  280. #define SW_YELLOW_COLOR_S 2
  281. #define SW_GREEN_COLOR_S 0
  282. #define SW_COLOR_M 0x3
  283. #define REG_SW_QM_CTRL__4 0x0390
  284. #define PRIO_SCHEME_SELECT_M KS_PRIO_M
  285. #define PRIO_SCHEME_SELECT_S 6
  286. #define PRIO_MAP_3_HI 0
  287. #define PRIO_MAP_2_HI 2
  288. #define PRIO_MAP_0_LO 3
  289. #define UNICAST_VLAN_BOUNDARY BIT(1)
  290. #define REG_SW_EEE_QM_CTRL__2 0x03C0
  291. #define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2
  292. /* 4 - */
  293. #define REG_SW_VLAN_ENTRY__4 0x0400
  294. #define VLAN_VALID BIT(31)
  295. #define VLAN_FORWARD_OPTION BIT(27)
  296. #define VLAN_PRIO_M KS_PRIO_M
  297. #define VLAN_PRIO_S 24
  298. #define VLAN_MSTP_M 0x7
  299. #define VLAN_MSTP_S 12
  300. #define VLAN_FID_M 0x7F
  301. #define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404
  302. #define REG_SW_VLAN_ENTRY_PORTS__4 0x0408
  303. #define REG_SW_VLAN_ENTRY_INDEX__2 0x040C
  304. #define VLAN_INDEX_M 0x0FFF
  305. #define REG_SW_VLAN_CTRL 0x040E
  306. #define VLAN_START BIT(7)
  307. #define VLAN_ACTION 0x3
  308. #define VLAN_WRITE 1
  309. #define VLAN_READ 2
  310. #define VLAN_CLEAR 3
  311. #define REG_SW_ALU_INDEX_0 0x0410
  312. #define ALU_FID_INDEX_S 16
  313. #define ALU_MAC_ADDR_HI 0xFFFF
  314. #define REG_SW_ALU_INDEX_1 0x0414
  315. #define ALU_DIRECT_INDEX_M (BIT(12) - 1)
  316. #define REG_SW_ALU_CTRL__4 0x0418
  317. #define ALU_VALID_CNT_M (BIT(14) - 1)
  318. #define ALU_VALID_CNT_S 16
  319. #define ALU_START BIT(7)
  320. #define ALU_VALID BIT(6)
  321. #define ALU_DIRECT BIT(2)
  322. #define ALU_ACTION 0x3
  323. #define ALU_WRITE 1
  324. #define ALU_READ 2
  325. #define ALU_SEARCH 3
  326. #define REG_SW_ALU_STAT_CTRL__4 0x041C
  327. #define ALU_STAT_INDEX_M (BIT(4) - 1)
  328. #define ALU_STAT_INDEX_S 16
  329. #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
  330. #define ALU_STAT_START BIT(7)
  331. #define ALU_RESV_MCAST_ADDR BIT(1)
  332. #define ALU_STAT_READ BIT(0)
  333. #define REG_SW_ALU_VAL_A 0x0420
  334. #define ALU_V_STATIC_VALID BIT(31)
  335. #define ALU_V_SRC_FILTER BIT(30)
  336. #define ALU_V_DST_FILTER BIT(29)
  337. #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
  338. #define ALU_V_PRIO_AGE_CNT_S 26
  339. #define ALU_V_MSTP_M 0x7
  340. #define REG_SW_ALU_VAL_B 0x0424
  341. #define ALU_V_OVERRIDE BIT(31)
  342. #define ALU_V_USE_FID BIT(30)
  343. #define ALU_V_PORT_MAP (BIT(24) - 1)
  344. #define REG_SW_ALU_VAL_C 0x0428
  345. #define ALU_V_FID_M (BIT(16) - 1)
  346. #define ALU_V_FID_S 16
  347. #define ALU_V_MAC_ADDR_HI 0xFFFF
  348. #define REG_SW_ALU_VAL_D 0x042C
  349. #define REG_HSR_ALU_INDEX_0 0x0440
  350. #define REG_HSR_ALU_INDEX_1 0x0444
  351. #define HSR_DST_MAC_INDEX_LO_S 16
  352. #define HSR_SRC_MAC_INDEX_HI 0xFFFF
  353. #define REG_HSR_ALU_INDEX_2 0x0448
  354. #define HSR_INDEX_MAX BIT(9)
  355. #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)
  356. #define REG_HSR_ALU_INDEX_3 0x044C
  357. #define HSR_PATH_INDEX_M (BIT(4) - 1)
  358. #define REG_HSR_ALU_CTRL__4 0x0450
  359. #define HSR_VALID_CNT_M (BIT(14) - 1)
  360. #define HSR_VALID_CNT_S 16
  361. #define HSR_START BIT(7)
  362. #define HSR_VALID BIT(6)
  363. #define HSR_SEARCH_END BIT(5)
  364. #define HSR_DIRECT BIT(2)
  365. #define HSR_ACTION 0x3
  366. #define HSR_WRITE 1
  367. #define HSR_READ 2
  368. #define HSR_SEARCH 3
  369. #define REG_HSR_ALU_VAL_A 0x0454
  370. #define HSR_V_STATIC_VALID BIT(31)
  371. #define HSR_V_AGE_CNT_M (BIT(3) - 1)
  372. #define HSR_V_AGE_CNT_S 26
  373. #define HSR_V_PATH_ID_M (BIT(4) - 1)
  374. #define REG_HSR_ALU_VAL_B 0x0458
  375. #define REG_HSR_ALU_VAL_C 0x045C
  376. #define HSR_V_DST_MAC_ADDR_LO_S 16
  377. #define HSR_V_SRC_MAC_ADDR_HI 0xFFFF
  378. #define REG_HSR_ALU_VAL_D 0x0460
  379. #define REG_HSR_ALU_VAL_E 0x0464
  380. #define HSR_V_START_SEQ_1_S 16
  381. #define HSR_V_START_SEQ_2_S 0
  382. #define REG_HSR_ALU_VAL_F 0x0468
  383. #define HSR_V_EXP_SEQ_1_S 16
  384. #define HSR_V_EXP_SEQ_2_S 0
  385. #define REG_HSR_ALU_VAL_G 0x046C
  386. #define HSR_V_SEQ_CNT_1_S 16
  387. #define HSR_V_SEQ_CNT_2_S 0
  388. #define HSR_V_SEQ_M (BIT(16) - 1)
  389. /* 5 - PTP Clock */
  390. #define REG_PTP_CLK_CTRL 0x0500
  391. #define PTP_STEP_ADJ BIT(6)
  392. #define PTP_STEP_DIR BIT(5)
  393. #define PTP_READ_TIME BIT(4)
  394. #define PTP_LOAD_TIME BIT(3)
  395. #define PTP_CLK_ADJ_ENABLE BIT(2)
  396. #define PTP_CLK_ENABLE BIT(1)
  397. #define PTP_CLK_RESET BIT(0)
  398. #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
  399. #define PTP_RTC_SUB_NANOSEC_M 0x0007
  400. #define REG_PTP_RTC_NANOSEC 0x0504
  401. #define REG_PTP_RTC_NANOSEC_H 0x0504
  402. #define REG_PTP_RTC_NANOSEC_L 0x0506
  403. #define REG_PTP_RTC_SEC 0x0508
  404. #define REG_PTP_RTC_SEC_H 0x0508
  405. #define REG_PTP_RTC_SEC_L 0x050A
  406. #define REG_PTP_SUBNANOSEC_RATE 0x050C
  407. #define REG_PTP_SUBNANOSEC_RATE_H 0x050C
  408. #define PTP_RATE_DIR BIT(31)
  409. #define PTP_TMP_RATE_ENABLE BIT(30)
  410. #define REG_PTP_SUBNANOSEC_RATE_L 0x050E
  411. #define REG_PTP_RATE_DURATION 0x0510
  412. #define REG_PTP_RATE_DURATION_H 0x0510
  413. #define REG_PTP_RATE_DURATION_L 0x0512
  414. #define REG_PTP_MSG_CONF1 0x0514
  415. #define PTP_802_1AS BIT(7)
  416. #define PTP_ENABLE BIT(6)
  417. #define PTP_ETH_ENABLE BIT(5)
  418. #define PTP_IPV4_UDP_ENABLE BIT(4)
  419. #define PTP_IPV6_UDP_ENABLE BIT(3)
  420. #define PTP_TC_P2P BIT(2)
  421. #define PTP_MASTER BIT(1)
  422. #define PTP_1STEP BIT(0)
  423. #define REG_PTP_MSG_CONF2 0x0516
  424. #define PTP_UNICAST_ENABLE BIT(12)
  425. #define PTP_ALTERNATE_MASTER BIT(11)
  426. #define PTP_ALL_HIGH_PRIO BIT(10)
  427. #define PTP_SYNC_CHECK BIT(9)
  428. #define PTP_DELAY_CHECK BIT(8)
  429. #define PTP_PDELAY_CHECK BIT(7)
  430. #define PTP_DROP_SYNC_DELAY_REQ BIT(5)
  431. #define PTP_DOMAIN_CHECK BIT(4)
  432. #define PTP_UDP_CHECKSUM BIT(2)
  433. #define REG_PTP_DOMAIN_VERSION 0x0518
  434. #define PTP_VERSION_M 0xFF00
  435. #define PTP_DOMAIN_M 0x00FF
  436. #define REG_PTP_UNIT_INDEX__4 0x0520
  437. #define PTP_UNIT_M 0xF
  438. #define PTP_GPIO_INDEX_S 16
  439. #define PTP_TSI_INDEX_S 8
  440. #define PTP_TOU_INDEX_S 0
  441. #define REG_PTP_TRIG_STATUS__4 0x0524
  442. #define TRIG_ERROR_S 16
  443. #define TRIG_DONE_S 0
  444. #define REG_PTP_INT_STATUS__4 0x0528
  445. #define TRIG_INT_S 16
  446. #define TS_INT_S 0
  447. #define TRIG_UNIT_M 0x7
  448. #define TS_UNIT_M 0x3
  449. #define REG_PTP_CTRL_STAT__4 0x052C
  450. #define GPIO_IN BIT(7)
  451. #define GPIO_OUT BIT(6)
  452. #define TS_INT_ENABLE BIT(5)
  453. #define TRIG_ACTIVE BIT(4)
  454. #define TRIG_ENABLE BIT(3)
  455. #define TRIG_RESET BIT(2)
  456. #define TS_ENABLE BIT(1)
  457. #define TS_RESET BIT(0)
  458. #define GPIO_CTRL_M (GPIO_IN | GPIO_OUT)
  459. #define TRIG_CTRL_M \
  460. (TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET)
  461. #define TS_CTRL_M \
  462. (TS_INT_ENABLE | TS_ENABLE | TS_RESET)
  463. #define REG_TRIG_TARGET_NANOSEC 0x0530
  464. #define REG_TRIG_TARGET_SEC 0x0534
  465. #define REG_TRIG_CTRL__4 0x0538
  466. #define TRIG_CASCADE_ENABLE BIT(31)
  467. #define TRIG_CASCADE_TAIL BIT(30)
  468. #define TRIG_CASCADE_UPS_M 0xF
  469. #define TRIG_CASCADE_UPS_S 26
  470. #define TRIG_NOW BIT(25)
  471. #define TRIG_NOTIFY BIT(24)
  472. #define TRIG_EDGE BIT(23)
  473. #define TRIG_PATTERN_S 20
  474. #define TRIG_PATTERN_M 0x7
  475. #define TRIG_NEG_EDGE 0
  476. #define TRIG_POS_EDGE 1
  477. #define TRIG_NEG_PULSE 2
  478. #define TRIG_POS_PULSE 3
  479. #define TRIG_NEG_PERIOD 4
  480. #define TRIG_POS_PERIOD 5
  481. #define TRIG_REG_OUTPUT 6
  482. #define TRIG_GPO_S 16
  483. #define TRIG_GPO_M 0xF
  484. #define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF
  485. #define REG_TRIG_CYCLE_WIDTH 0x053C
  486. #define REG_TRIG_CYCLE_CNT 0x0540
  487. #define TRIG_CYCLE_CNT_M 0xFFFF
  488. #define TRIG_CYCLE_CNT_S 16
  489. #define TRIG_BIT_PATTERN_M 0xFFFF
  490. #define REG_TRIG_ITERATE_TIME 0x0544
  491. #define REG_TRIG_PULSE_WIDTH__4 0x0548
  492. #define TRIG_PULSE_WIDTH_M 0x00FFFFFF
  493. #define REG_TS_CTRL_STAT__4 0x0550
  494. #define TS_EVENT_DETECT_M 0xF
  495. #define TS_EVENT_DETECT_S 17
  496. #define TS_EVENT_OVERFLOW BIT(16)
  497. #define TS_GPI_M 0xF
  498. #define TS_GPI_S 8
  499. #define TS_DETECT_RISE BIT(7)
  500. #define TS_DETECT_FALL BIT(6)
  501. #define TS_DETECT_S 6
  502. #define TS_CASCADE_TAIL BIT(5)
  503. #define TS_CASCADE_UPS_M 0xF
  504. #define TS_CASCADE_UPS_S 1
  505. #define TS_CASCADE_ENABLE BIT(0)
  506. #define DETECT_RISE (TS_DETECT_RISE >> TS_DETECT_S)
  507. #define DETECT_FALL (TS_DETECT_FALL >> TS_DETECT_S)
  508. #define REG_TS_EVENT_0_NANOSEC 0x0554
  509. #define REG_TS_EVENT_0_SEC 0x0558
  510. #define REG_TS_EVENT_0_SUB_NANOSEC 0x055C
  511. #define REG_TS_EVENT_1_NANOSEC 0x0560
  512. #define REG_TS_EVENT_1_SEC 0x0564
  513. #define REG_TS_EVENT_1_SUB_NANOSEC 0x0568
  514. #define REG_TS_EVENT_2_NANOSEC 0x056C
  515. #define REG_TS_EVENT_2_SEC 0x0570
  516. #define REG_TS_EVENT_2_SUB_NANOSEC 0x0574
  517. #define REG_TS_EVENT_3_NANOSEC 0x0578
  518. #define REG_TS_EVENT_3_SEC 0x057C
  519. #define REG_TS_EVENT_3_SUB_NANOSEC 0x0580
  520. #define REG_TS_EVENT_4_NANOSEC 0x0584
  521. #define REG_TS_EVENT_4_SEC 0x0588
  522. #define REG_TS_EVENT_4_SUB_NANOSEC 0x058C
  523. #define REG_TS_EVENT_5_NANOSEC 0x0590
  524. #define REG_TS_EVENT_5_SEC 0x0594
  525. #define REG_TS_EVENT_5_SUB_NANOSEC 0x0598
  526. #define REG_TS_EVENT_6_NANOSEC 0x059C
  527. #define REG_TS_EVENT_6_SEC 0x05A0
  528. #define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4
  529. #define REG_TS_EVENT_7_NANOSEC 0x05A8
  530. #define REG_TS_EVENT_7_SEC 0x05AC
  531. #define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0
  532. #define TS_EVENT_EDGE_M 0x1
  533. #define TS_EVENT_EDGE_S 30
  534. #define TS_EVENT_NANOSEC_M (BIT(30) - 1)
  535. #define TS_EVENT_SUB_NANOSEC_M 0x7
  536. #define TS_EVENT_SAMPLE \
  537. (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
  538. #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
  539. #define REG_GLOBAL_RR_INDEX__1 0x0600
  540. /* DLR */
  541. #define REG_DLR_SRC_PORT__4 0x0604
  542. #define DLR_SRC_PORT_UNICAST BIT(31)
  543. #define DLR_SRC_PORT_M 0x3
  544. #define DLR_SRC_PORT_BOTH 0
  545. #define DLR_SRC_PORT_EACH 1
  546. #define REG_DLR_IP_ADDR__4 0x0608
  547. #define REG_DLR_CTRL__1 0x0610
  548. #define DLR_RESET_SEQ_ID BIT(3)
  549. #define DLR_BACKUP_AUTO_ON BIT(2)
  550. #define DLR_BEACON_TX_ENABLE BIT(1)
  551. #define DLR_ASSIST_ENABLE BIT(0)
  552. #define REG_DLR_STATE__1 0x0611
  553. #define DLR_NODE_STATE_M 0x3
  554. #define DLR_NODE_STATE_S 1
  555. #define DLR_NODE_STATE_IDLE 0
  556. #define DLR_NODE_STATE_FAULT 1
  557. #define DLR_NODE_STATE_NORMAL 2
  558. #define DLR_RING_STATE_FAULT 0
  559. #define DLR_RING_STATE_NORMAL 1
  560. #define REG_DLR_PRECEDENCE__1 0x0612
  561. #define REG_DLR_BEACON_INTERVAL__4 0x0614
  562. #define REG_DLR_BEACON_TIMEOUT__4 0x0618
  563. #define REG_DLR_TIMEOUT_WINDOW__4 0x061C
  564. #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
  565. #define REG_DLR_VLAN_ID__2 0x0620
  566. #define DLR_VLAN_ID_M (BIT(12) - 1)
  567. #define REG_DLR_DEST_ADDR_0 0x0622
  568. #define REG_DLR_DEST_ADDR_1 0x0623
  569. #define REG_DLR_DEST_ADDR_2 0x0624
  570. #define REG_DLR_DEST_ADDR_3 0x0625
  571. #define REG_DLR_DEST_ADDR_4 0x0626
  572. #define REG_DLR_DEST_ADDR_5 0x0627
  573. #define REG_DLR_PORT_MAP__4 0x0628
  574. #define REG_DLR_CLASS__1 0x062C
  575. #define DLR_FRAME_QID_M 0x3
  576. /* HSR */
  577. #define REG_HSR_PORT_MAP__4 0x0640
  578. #define REG_HSR_ALU_CTRL_0__1 0x0644
  579. #define HSR_DUPLICATE_DISCARD BIT(7)
  580. #define HSR_NODE_UNICAST BIT(6)
  581. #define HSR_AGE_CNT_DEFAULT_M 0x7
  582. #define HSR_AGE_CNT_DEFAULT_S 3
  583. #define HSR_LEARN_MCAST_DISABLE BIT(2)
  584. #define HSR_HASH_OPTION_M 0x3
  585. #define HSR_HASH_DISABLE 0
  586. #define HSR_HASH_UPPER_BITS 1
  587. #define HSR_HASH_LOWER_BITS 2
  588. #define HSR_HASH_XOR_BOTH_BITS 3
  589. #define REG_HSR_ALU_CTRL_1__1 0x0645
  590. #define HSR_LEARN_UCAST_DISABLE BIT(7)
  591. #define HSR_FLUSH_TABLE BIT(5)
  592. #define HSR_PROC_MCAST_SRC BIT(3)
  593. #define HSR_AGING_ENABLE BIT(2)
  594. #define REG_HSR_ALU_CTRL_2__2 0x0646
  595. #define REG_HSR_ALU_AGE_PERIOD__4 0x0648
  596. #define REG_HSR_ALU_INT_STATUS__1 0x064C
  597. #define REG_HSR_ALU_INT_MASK__1 0x064D
  598. #define HSR_WINDOW_OVERFLOW_INT BIT(3)
  599. #define HSR_LEARN_FAIL_INT BIT(2)
  600. #define HSR_ALMOST_FULL_INT BIT(1)
  601. #define HSR_WRITE_FAIL_INT BIT(0)
  602. #define REG_HSR_ALU_ENTRY_0__2 0x0650
  603. #define HSR_ENTRY_INDEX_M (BIT(10) - 1)
  604. #define HSR_FAIL_INDEX_M (BIT(8) - 1)
  605. #define REG_HSR_ALU_ENTRY_1__2 0x0652
  606. #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
  607. #define REG_HSR_ALU_ENTRY_3__2 0x0654
  608. #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
  609. /* 0 - Operation */
  610. #define REG_PORT_DEFAULT_VID 0x0000
  611. #define REG_PORT_CUSTOM_VID 0x0002
  612. #define REG_PORT_AVB_SR_1_VID 0x0004
  613. #define REG_PORT_AVB_SR_2_VID 0x0006
  614. #define REG_PORT_AVB_SR_1_TYPE 0x0008
  615. #define REG_PORT_AVB_SR_2_TYPE 0x000A
  616. #define REG_PORT_PME_STATUS 0x0013
  617. #define REG_PORT_PME_CTRL 0x0017
  618. #define PME_WOL_MAGICPKT BIT(2)
  619. #define PME_WOL_LINKUP BIT(1)
  620. #define PME_WOL_ENERGY BIT(0)
  621. #define REG_PORT_INT_STATUS 0x001B
  622. #define REG_PORT_INT_MASK 0x001F
  623. #define PORT_SGMII_INT BIT(3)
  624. #define PORT_PTP_INT BIT(2)
  625. #define PORT_PHY_INT BIT(1)
  626. #define PORT_ACL_INT BIT(0)
  627. #define PORT_INT_MASK \
  628. (PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT)
  629. #define REG_PORT_CTRL_0 0x0020
  630. #define PORT_MAC_LOOPBACK BIT(7)
  631. #define PORT_FORCE_TX_FLOW_CTRL BIT(4)
  632. #define PORT_FORCE_RX_FLOW_CTRL BIT(3)
  633. #define PORT_TAIL_TAG_ENABLE BIT(2)
  634. #define PORT_QUEUE_SPLIT_ENABLE 0x3
  635. #define REG_PORT_CTRL_1 0x0021
  636. #define PORT_SRP_ENABLE 0x3
  637. #define REG_PORT_STATUS_0 0x0030
  638. #define PORT_INTF_SPEED_M 0x3
  639. #define PORT_INTF_SPEED_S 3
  640. #define PORT_INTF_FULL_DUPLEX BIT(2)
  641. #define PORT_TX_FLOW_CTRL BIT(1)
  642. #define PORT_RX_FLOW_CTRL BIT(0)
  643. #define REG_PORT_STATUS_1 0x0034
  644. /* 1 - PHY */
  645. #define REG_PORT_PHY_CTRL 0x0100
  646. #define PORT_PHY_RESET BIT(15)
  647. #define PORT_PHY_LOOPBACK BIT(14)
  648. #define PORT_SPEED_100MBIT BIT(13)
  649. #define PORT_AUTO_NEG_ENABLE BIT(12)
  650. #define PORT_POWER_DOWN BIT(11)
  651. #define PORT_ISOLATE BIT(10)
  652. #define PORT_AUTO_NEG_RESTART BIT(9)
  653. #define PORT_FULL_DUPLEX BIT(8)
  654. #define PORT_COLLISION_TEST BIT(7)
  655. #define PORT_SPEED_1000MBIT BIT(6)
  656. #define REG_PORT_PHY_STATUS 0x0102
  657. #define PORT_100BT4_CAPABLE BIT(15)
  658. #define PORT_100BTX_FD_CAPABLE BIT(14)
  659. #define PORT_100BTX_CAPABLE BIT(13)
  660. #define PORT_10BT_FD_CAPABLE BIT(12)
  661. #define PORT_10BT_CAPABLE BIT(11)
  662. #define PORT_EXTENDED_STATUS BIT(8)
  663. #define PORT_MII_SUPPRESS_CAPABLE BIT(6)
  664. #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
  665. #define PORT_REMOTE_FAULT BIT(4)
  666. #define PORT_AUTO_NEG_CAPABLE BIT(3)
  667. #define PORT_LINK_STATUS BIT(2)
  668. #define PORT_JABBER_DETECT BIT(1)
  669. #define PORT_EXTENDED_CAPABILITY BIT(0)
  670. #define REG_PORT_PHY_ID_HI 0x0104
  671. #define REG_PORT_PHY_ID_LO 0x0106
  672. #define KSZ9477_ID_HI 0x0022
  673. #define KSZ9477_ID_LO 0x1622
  674. #define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108
  675. #define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
  676. #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
  677. #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
  678. #define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
  679. #define PORT_AUTO_NEG_100BT4 BIT(9)
  680. #define PORT_AUTO_NEG_100BTX_FD BIT(8)
  681. #define PORT_AUTO_NEG_100BTX BIT(7)
  682. #define PORT_AUTO_NEG_10BT_FD BIT(6)
  683. #define PORT_AUTO_NEG_10BT BIT(5)
  684. #define PORT_AUTO_NEG_SELECTOR 0x001F
  685. #define PORT_AUTO_NEG_802_3 0x0001
  686. #define PORT_AUTO_NEG_PAUSE \
  687. (PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE)
  688. #define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A
  689. #define PORT_REMOTE_NEXT_PAGE BIT(15)
  690. #define PORT_REMOTE_ACKNOWLEDGE BIT(14)
  691. #define PORT_REMOTE_REMOTE_FAULT BIT(13)
  692. #define PORT_REMOTE_ASYM_PAUSE BIT(11)
  693. #define PORT_REMOTE_SYM_PAUSE BIT(10)
  694. #define PORT_REMOTE_100BTX_FD BIT(8)
  695. #define PORT_REMOTE_100BTX BIT(7)
  696. #define PORT_REMOTE_10BT_FD BIT(6)
  697. #define PORT_REMOTE_10BT BIT(5)
  698. #define REG_PORT_PHY_1000_CTRL 0x0112
  699. #define PORT_AUTO_NEG_MANUAL BIT(12)
  700. #define PORT_AUTO_NEG_MASTER BIT(11)
  701. #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
  702. #define PORT_AUTO_NEG_1000BT_FD BIT(9)
  703. #define PORT_AUTO_NEG_1000BT BIT(8)
  704. #define REG_PORT_PHY_1000_STATUS 0x0114
  705. #define PORT_MASTER_FAULT BIT(15)
  706. #define PORT_LOCAL_MASTER BIT(14)
  707. #define PORT_LOCAL_RX_OK BIT(13)
  708. #define PORT_REMOTE_RX_OK BIT(12)
  709. #define PORT_REMOTE_1000BT_FD BIT(11)
  710. #define PORT_REMOTE_1000BT BIT(10)
  711. #define PORT_REMOTE_IDLE_CNT_M 0x0F
  712. #define PORT_PHY_1000_STATIC_STATUS \
  713. (PORT_LOCAL_RX_OK | \
  714. PORT_REMOTE_RX_OK | \
  715. PORT_REMOTE_1000BT_FD | \
  716. PORT_REMOTE_1000BT)
  717. #define REG_PORT_PHY_MMD_SETUP 0x011A
  718. #define PORT_MMD_OP_MODE_M 0x3
  719. #define PORT_MMD_OP_MODE_S 14
  720. #define PORT_MMD_OP_INDEX 0
  721. #define PORT_MMD_OP_DATA_NO_INCR 1
  722. #define PORT_MMD_OP_DATA_INCR_RW 2
  723. #define PORT_MMD_OP_DATA_INCR_W 3
  724. #define PORT_MMD_DEVICE_ID_M 0x1F
  725. #define MMD_SETUP(mode, dev) \
  726. (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
  727. #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
  728. #define MMD_DEVICE_ID_DSP 1
  729. #define MMD_DSP_SQI_CHAN_A 0xAC
  730. #define MMD_DSP_SQI_CHAN_B 0xAD
  731. #define MMD_DSP_SQI_CHAN_C 0xAE
  732. #define MMD_DSP_SQI_CHAN_D 0xAF
  733. #define DSP_SQI_ERR_DETECTED BIT(15)
  734. #define DSP_SQI_AVG_ERR 0x7FFF
  735. #define MMD_DEVICE_ID_COMMON 2
  736. #define MMD_DEVICE_ID_EEE_ADV 7
  737. #define MMD_EEE_ADV 0x3C
  738. #define EEE_ADV_100MBIT BIT(1)
  739. #define EEE_ADV_1GBIT BIT(2)
  740. #define MMD_EEE_LP_ADV 0x3D
  741. #define MMD_EEE_MSG_CODE 0x3F
  742. #define MMD_DEVICE_ID_AFED 0x1C
  743. #define REG_PORT_PHY_EXTENDED_STATUS 0x011E
  744. #define PORT_100BTX_FD_ABLE BIT(15)
  745. #define PORT_100BTX_ABLE BIT(14)
  746. #define PORT_10BT_FD_ABLE BIT(13)
  747. #define PORT_10BT_ABLE BIT(12)
  748. #define REG_PORT_SGMII_ADDR__4 0x0200
  749. #define PORT_SGMII_AUTO_INCR BIT(23)
  750. #define PORT_SGMII_DEVICE_ID_M 0x1F
  751. #define PORT_SGMII_DEVICE_ID_S 16
  752. #define PORT_SGMII_ADDR_M (BIT(21) - 1)
  753. #define REG_PORT_SGMII_DATA__4 0x0204
  754. #define PORT_SGMII_DATA_M (BIT(16) - 1)
  755. #define MMD_DEVICE_ID_PMA 0x01
  756. #define MMD_DEVICE_ID_PCS 0x03
  757. #define MMD_DEVICE_ID_PHY_XS 0x04
  758. #define MMD_DEVICE_ID_DTE_XS 0x05
  759. #define MMD_DEVICE_ID_AN 0x07
  760. #define MMD_DEVICE_ID_VENDOR_CTRL 0x1E
  761. #define MMD_DEVICE_ID_VENDOR_MII 0x1F
  762. #define SR_MII MMD_DEVICE_ID_VENDOR_MII
  763. #define MMD_SR_MII_CTRL 0x0000
  764. #define SR_MII_RESET BIT(15)
  765. #define SR_MII_LOOPBACK BIT(14)
  766. #define SR_MII_SPEED_100MBIT BIT(13)
  767. #define SR_MII_AUTO_NEG_ENABLE BIT(12)
  768. #define SR_MII_POWER_DOWN BIT(11)
  769. #define SR_MII_AUTO_NEG_RESTART BIT(9)
  770. #define SR_MII_FULL_DUPLEX BIT(8)
  771. #define SR_MII_SPEED_1000MBIT BIT(6)
  772. #define MMD_SR_MII_STATUS 0x0001
  773. #define MMD_SR_MII_ID_1 0x0002
  774. #define MMD_SR_MII_ID_2 0x0003
  775. #define MMD_SR_MII_AUTO_NEGOTIATION 0x0004
  776. #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
  777. #define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3
  778. #define SR_MII_AUTO_NEG_REMOTE_FAULT_S 12
  779. #define SR_MII_AUTO_NEG_NO_ERROR 0
  780. #define SR_MII_AUTO_NEG_OFFLINE 1
  781. #define SR_MII_AUTO_NEG_LINK_FAILURE 2
  782. #define SR_MII_AUTO_NEG_ERROR 3
  783. #define SR_MII_AUTO_NEG_PAUSE_M 0x3
  784. #define SR_MII_AUTO_NEG_PAUSE_S 7
  785. #define SR_MII_AUTO_NEG_NO_PAUSE 0
  786. #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 1
  787. #define SR_MII_AUTO_NEG_SYM_PAUSE 2
  788. #define SR_MII_AUTO_NEG_ASYM_PAUSE_RX 3
  789. #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
  790. #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
  791. #define MMD_SR_MII_REMOTE_CAPABILITY 0x0005
  792. #define MMD_SR_MII_AUTO_NEG_EXP 0x0006
  793. #define MMD_SR_MII_AUTO_NEG_EXT 0x000F
  794. #define MMD_SR_MII_DIGITAL_CTRL_1 0x8000
  795. #define MMD_SR_MII_AUTO_NEG_CTRL 0x8001
  796. #define SR_MII_8_BIT BIT(8)
  797. #define SR_MII_SGMII_LINK_UP BIT(4)
  798. #define SR_MII_TX_CFG_PHY_MASTER BIT(3)
  799. #define SR_MII_PCS_MODE_M 0x3
  800. #define SR_MII_PCS_MODE_S 1
  801. #define SR_MII_PCS_SGMII 2
  802. #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
  803. #define MMD_SR_MII_AUTO_NEG_STATUS 0x8002
  804. #define SR_MII_STAT_LINK_UP BIT(4)
  805. #define SR_MII_STAT_M 0x3
  806. #define SR_MII_STAT_S 2
  807. #define SR_MII_STAT_10_MBPS 0
  808. #define SR_MII_STAT_100_MBPS 1
  809. #define SR_MII_STAT_1000_MBPS 2
  810. #define SR_MII_STAT_FULL_DUPLEX BIT(1)
  811. #define MMD_SR_MII_PHY_CTRL 0x80A0
  812. #define SR_MII_PHY_LANE_SEL_M 0xF
  813. #define SR_MII_PHY_LANE_SEL_S 8
  814. #define SR_MII_PHY_WRITE BIT(1)
  815. #define SR_MII_PHY_START_BUSY BIT(0)
  816. #define MMD_SR_MII_PHY_ADDR 0x80A1
  817. #define SR_MII_PHY_ADDR_M (BIT(16) - 1)
  818. #define MMD_SR_MII_PHY_DATA 0x80A2
  819. #define SR_MII_PHY_DATA_M (BIT(16) - 1)
  820. #define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C
  821. #define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D
  822. #define REG_PORT_PHY_REMOTE_LB_LED 0x0122
  823. #define PORT_REMOTE_LOOPBACK BIT(8)
  824. #define PORT_LED_SELECT (3 << 6)
  825. #define PORT_LED_CTRL (3 << 4)
  826. #define PORT_LED_CTRL_TEST BIT(3)
  827. #define PORT_10BT_PREAMBLE BIT(2)
  828. #define PORT_LINK_MD_10BT_ENABLE BIT(1)
  829. #define PORT_LINK_MD_PASS BIT(0)
  830. #define REG_PORT_PHY_LINK_MD 0x0124
  831. #define PORT_START_CABLE_DIAG BIT(15)
  832. #define PORT_TX_DISABLE BIT(14)
  833. #define PORT_CABLE_DIAG_PAIR_M 0x3
  834. #define PORT_CABLE_DIAG_PAIR_S 12
  835. #define PORT_CABLE_DIAG_SELECT_M 0x3
  836. #define PORT_CABLE_DIAG_SELECT_S 10
  837. #define PORT_CABLE_DIAG_RESULT_M 0x3
  838. #define PORT_CABLE_DIAG_RESULT_S 8
  839. #define PORT_CABLE_STAT_NORMAL 0
  840. #define PORT_CABLE_STAT_OPEN 1
  841. #define PORT_CABLE_STAT_SHORT 2
  842. #define PORT_CABLE_STAT_FAILED 3
  843. #define PORT_CABLE_FAULT_COUNTER 0x00FF
  844. #define REG_PORT_PHY_PMA_STATUS 0x0126
  845. #define PORT_1000_LINK_GOOD BIT(1)
  846. #define PORT_100_LINK_GOOD BIT(0)
  847. #define REG_PORT_PHY_DIGITAL_STATUS 0x0128
  848. #define PORT_LINK_DETECT BIT(14)
  849. #define PORT_SIGNAL_DETECT BIT(13)
  850. #define PORT_PHY_STAT_MDI BIT(12)
  851. #define PORT_PHY_STAT_MASTER BIT(11)
  852. #define REG_PORT_PHY_RXER_COUNTER 0x012A
  853. #define REG_PORT_PHY_INT_ENABLE 0x0136
  854. #define REG_PORT_PHY_INT_STATUS 0x0137
  855. #define JABBER_INT BIT(7)
  856. #define RX_ERR_INT BIT(6)
  857. #define PAGE_RX_INT BIT(5)
  858. #define PARALLEL_DETECT_FAULT_INT BIT(4)
  859. #define LINK_PARTNER_ACK_INT BIT(3)
  860. #define LINK_DOWN_INT BIT(2)
  861. #define REMOTE_FAULT_INT BIT(1)
  862. #define LINK_UP_INT BIT(0)
  863. #define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138
  864. #define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
  865. #define PORT_PHY_FORCE_MDI BIT(7)
  866. #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
  867. /* Same as PORT_PHY_LOOPBACK */
  868. #define PORT_PHY_PCS_LOOPBACK BIT(0)
  869. #define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A
  870. #define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C
  871. #define PORT_100BT_FIXED_LATENCY BIT(15)
  872. #define REG_PORT_PHY_PHY_CTRL 0x013E
  873. #define PORT_INT_PIN_HIGH BIT(14)
  874. #define PORT_ENABLE_JABBER BIT(9)
  875. #define PORT_STAT_SPEED_1000MBIT BIT(6)
  876. #define PORT_STAT_SPEED_100MBIT BIT(5)
  877. #define PORT_STAT_SPEED_10MBIT BIT(4)
  878. #define PORT_STAT_FULL_DUPLEX BIT(3)
  879. /* Same as PORT_PHY_STAT_MASTER */
  880. #define PORT_STAT_MASTER BIT(2)
  881. #define PORT_RESET BIT(1)
  882. #define PORT_LINK_STATUS_FAIL BIT(0)
  883. /* 3 - xMII */
  884. #define REG_PORT_XMII_CTRL_0 0x0300
  885. #define PORT_SGMII_SEL BIT(7)
  886. #define PORT_MII_FULL_DUPLEX BIT(6)
  887. #define PORT_MII_100MBIT BIT(4)
  888. #define PORT_GRXC_ENABLE BIT(0)
  889. #define REG_PORT_XMII_CTRL_1 0x0301
  890. #define PORT_RMII_CLK_SEL BIT(7)
  891. /* S1 */
  892. #define PORT_MII_1000MBIT_S1 BIT(6)
  893. /* S2 */
  894. #define PORT_MII_NOT_1GBIT BIT(6)
  895. #define PORT_MII_SEL_EDGE BIT(5)
  896. #define PORT_RGMII_ID_IG_ENABLE BIT(4)
  897. #define PORT_RGMII_ID_EG_ENABLE BIT(3)
  898. #define PORT_MII_MAC_MODE BIT(2)
  899. #define PORT_MII_SEL_M 0x3
  900. /* S1 */
  901. #define PORT_MII_SEL_S1 0x0
  902. #define PORT_RMII_SEL_S1 0x1
  903. #define PORT_GMII_SEL_S1 0x2
  904. #define PORT_RGMII_SEL_S1 0x3
  905. /* S2 */
  906. #define PORT_RGMII_SEL 0x0
  907. #define PORT_RMII_SEL 0x1
  908. #define PORT_GMII_SEL 0x2
  909. #define PORT_MII_SEL 0x3
  910. /* 4 - MAC */
  911. #define REG_PORT_MAC_CTRL_0 0x0400
  912. #define PORT_BROADCAST_STORM BIT(1)
  913. #define PORT_JUMBO_FRAME BIT(0)
  914. #define REG_PORT_MAC_CTRL_1 0x0401
  915. #define PORT_BACK_PRESSURE BIT(3)
  916. #define PORT_PASS_ALL BIT(0)
  917. #define REG_PORT_MAC_CTRL_2 0x0402
  918. #define PORT_100BT_EEE_DISABLE BIT(7)
  919. #define PORT_1000BT_EEE_DISABLE BIT(6)
  920. #define REG_PORT_MAC_IN_RATE_LIMIT 0x0403
  921. #define PORT_IN_PORT_BASED_S 6
  922. #define PORT_RATE_PACKET_BASED_S 5
  923. #define PORT_IN_FLOW_CTRL_S 4
  924. #define PORT_COUNT_IFG_S 1
  925. #define PORT_COUNT_PREAMBLE_S 0
  926. #define PORT_IN_PORT_BASED BIT(6)
  927. #define PORT_IN_PACKET_BASED BIT(5)
  928. #define PORT_IN_FLOW_CTRL BIT(4)
  929. #define PORT_IN_LIMIT_MODE_M 0x3
  930. #define PORT_IN_LIMIT_MODE_S 2
  931. #define PORT_IN_ALL 0
  932. #define PORT_IN_UNICAST 1
  933. #define PORT_IN_MULTICAST 2
  934. #define PORT_IN_BROADCAST 3
  935. #define PORT_COUNT_IFG BIT(1)
  936. #define PORT_COUNT_PREAMBLE BIT(0)
  937. #define REG_PORT_IN_RATE_0 0x0410
  938. #define REG_PORT_IN_RATE_1 0x0411
  939. #define REG_PORT_IN_RATE_2 0x0412
  940. #define REG_PORT_IN_RATE_3 0x0413
  941. #define REG_PORT_IN_RATE_4 0x0414
  942. #define REG_PORT_IN_RATE_5 0x0415
  943. #define REG_PORT_IN_RATE_6 0x0416
  944. #define REG_PORT_IN_RATE_7 0x0417
  945. #define REG_PORT_OUT_RATE_0 0x0420
  946. #define REG_PORT_OUT_RATE_1 0x0421
  947. #define REG_PORT_OUT_RATE_2 0x0422
  948. #define REG_PORT_OUT_RATE_3 0x0423
  949. #define PORT_RATE_LIMIT_M (BIT(7) - 1)
  950. /* 5 - MIB Counters */
  951. #define REG_PORT_MIB_CTRL_STAT__4 0x0500
  952. #define MIB_COUNTER_OVERFLOW BIT(31)
  953. #define MIB_COUNTER_VALID BIT(30)
  954. #define MIB_COUNTER_READ BIT(25)
  955. #define MIB_COUNTER_FLUSH_FREEZE BIT(24)
  956. #define MIB_COUNTER_INDEX_M (BIT(8) - 1)
  957. #define MIB_COUNTER_INDEX_S 16
  958. #define MIB_COUNTER_DATA_HI_M 0xF
  959. #define REG_PORT_MIB_DATA 0x0504
  960. /* 6 - ACL */
  961. #define REG_PORT_ACL_0 0x0600
  962. #define ACL_FIRST_RULE_M 0xF
  963. #define REG_PORT_ACL_1 0x0601
  964. #define ACL_MODE_M 0x3
  965. #define ACL_MODE_S 4
  966. #define ACL_MODE_DISABLE 0
  967. #define ACL_MODE_LAYER_2 1
  968. #define ACL_MODE_LAYER_3 2
  969. #define ACL_MODE_LAYER_4 3
  970. #define ACL_ENABLE_M 0x3
  971. #define ACL_ENABLE_S 2
  972. #define ACL_ENABLE_2_COUNT 0
  973. #define ACL_ENABLE_2_TYPE 1
  974. #define ACL_ENABLE_2_MAC 2
  975. #define ACL_ENABLE_2_BOTH 3
  976. #define ACL_ENABLE_3_IP 1
  977. #define ACL_ENABLE_3_SRC_DST_COMP 2
  978. #define ACL_ENABLE_4_PROTOCOL 0
  979. #define ACL_ENABLE_4_TCP_PORT_COMP 1
  980. #define ACL_ENABLE_4_UDP_PORT_COMP 2
  981. #define ACL_ENABLE_4_TCP_SEQN_COMP 3
  982. #define ACL_SRC BIT(1)
  983. #define ACL_EQUAL BIT(0)
  984. #define REG_PORT_ACL_2 0x0602
  985. #define REG_PORT_ACL_3 0x0603
  986. #define ACL_MAX_PORT 0xFFFF
  987. #define REG_PORT_ACL_4 0x0604
  988. #define REG_PORT_ACL_5 0x0605
  989. #define ACL_MIN_PORT 0xFFFF
  990. #define ACL_IP_ADDR 0xFFFFFFFF
  991. #define ACL_TCP_SEQNUM 0xFFFFFFFF
  992. #define REG_PORT_ACL_6 0x0606
  993. #define ACL_RESERVED 0xF8
  994. #define ACL_PORT_MODE_M 0x3
  995. #define ACL_PORT_MODE_S 1
  996. #define ACL_PORT_MODE_DISABLE 0
  997. #define ACL_PORT_MODE_EITHER 1
  998. #define ACL_PORT_MODE_IN_RANGE 2
  999. #define ACL_PORT_MODE_OUT_OF_RANGE 3
  1000. #define REG_PORT_ACL_7 0x0607
  1001. #define ACL_TCP_FLAG_ENABLE BIT(0)
  1002. #define REG_PORT_ACL_8 0x0608
  1003. #define ACL_TCP_FLAG_M 0xFF
  1004. #define REG_PORT_ACL_9 0x0609
  1005. #define ACL_TCP_FLAG 0xFF
  1006. #define ACL_ETH_TYPE 0xFFFF
  1007. #define ACL_IP_M 0xFFFFFFFF
  1008. #define REG_PORT_ACL_A 0x060A
  1009. #define ACL_PRIO_MODE_M 0x3
  1010. #define ACL_PRIO_MODE_S 6
  1011. #define ACL_PRIO_MODE_DISABLE 0
  1012. #define ACL_PRIO_MODE_HIGHER 1
  1013. #define ACL_PRIO_MODE_LOWER 2
  1014. #define ACL_PRIO_MODE_REPLACE 3
  1015. #define ACL_PRIO_M KS_PRIO_M
  1016. #define ACL_PRIO_S 3
  1017. #define ACL_VLAN_PRIO_REPLACE BIT(2)
  1018. #define ACL_VLAN_PRIO_M KS_PRIO_M
  1019. #define ACL_VLAN_PRIO_HI_M 0x3
  1020. #define REG_PORT_ACL_B 0x060B
  1021. #define ACL_VLAN_PRIO_LO_M 0x8
  1022. #define ACL_VLAN_PRIO_S 7
  1023. #define ACL_MAP_MODE_M 0x3
  1024. #define ACL_MAP_MODE_S 5
  1025. #define ACL_MAP_MODE_DISABLE 0
  1026. #define ACL_MAP_MODE_OR 1
  1027. #define ACL_MAP_MODE_AND 2
  1028. #define ACL_MAP_MODE_REPLACE 3
  1029. #define ACL_CNT_M (BIT(11) - 1)
  1030. #define ACL_CNT_S 5
  1031. #define REG_PORT_ACL_C 0x060C
  1032. #define REG_PORT_ACL_D 0x060D
  1033. #define ACL_MSEC_UNIT BIT(6)
  1034. #define ACL_INTR_MODE BIT(5)
  1035. #define ACL_PORT_MAP 0x7F
  1036. #define REG_PORT_ACL_E 0x060E
  1037. #define REG_PORT_ACL_F 0x060F
  1038. #define REG_PORT_ACL_BYTE_EN_MSB 0x0610
  1039. #define REG_PORT_ACL_BYTE_EN_LSB 0x0611
  1040. #define ACL_ACTION_START 0xA
  1041. #define ACL_ACTION_LEN 4
  1042. #define ACL_INTR_CNT_START 0xD
  1043. #define ACL_RULESET_START 0xE
  1044. #define ACL_RULESET_LEN 2
  1045. #define ACL_TABLE_LEN 16
  1046. #define ACL_ACTION_ENABLE 0x003C
  1047. #define ACL_MATCH_ENABLE 0x7FC3
  1048. #define ACL_RULESET_ENABLE 0x8003
  1049. #define ACL_BYTE_ENABLE 0xFFFF
  1050. #define REG_PORT_ACL_CTRL_0 0x0612
  1051. #define PORT_ACL_WRITE_DONE BIT(6)
  1052. #define PORT_ACL_READ_DONE BIT(5)
  1053. #define PORT_ACL_WRITE BIT(4)
  1054. #define PORT_ACL_INDEX_M 0xF
  1055. #define REG_PORT_ACL_CTRL_1 0x0613
  1056. /* 8 - Classification and Policing */
  1057. #define REG_PORT_MRI_MIRROR_CTRL 0x0800
  1058. #define PORT_MIRROR_RX BIT(6)
  1059. #define PORT_MIRROR_TX BIT(5)
  1060. #define PORT_MIRROR_SNIFFER BIT(1)
  1061. #define REG_PORT_MRI_PRIO_CTRL 0x0801
  1062. #define PORT_HIGHEST_PRIO BIT(7)
  1063. #define PORT_OR_PRIO BIT(6)
  1064. #define PORT_MAC_PRIO_ENABLE BIT(4)
  1065. #define PORT_VLAN_PRIO_ENABLE BIT(3)
  1066. #define PORT_802_1P_PRIO_ENABLE BIT(2)
  1067. #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
  1068. #define PORT_ACL_PRIO_ENABLE BIT(0)
  1069. #define REG_PORT_MRI_MAC_CTRL 0x0802
  1070. #define PORT_USER_PRIO_CEILING BIT(7)
  1071. #define PORT_DROP_NON_VLAN BIT(4)
  1072. #define PORT_DROP_TAG BIT(3)
  1073. #define PORT_BASED_PRIO_M KS_PRIO_M
  1074. #define PORT_BASED_PRIO_S 0
  1075. #define REG_PORT_MRI_AUTHEN_CTRL 0x0803
  1076. #define PORT_ACL_ENABLE BIT(2)
  1077. #define PORT_AUTHEN_MODE 0x3
  1078. #define PORT_AUTHEN_PASS 0
  1079. #define PORT_AUTHEN_BLOCK 1
  1080. #define PORT_AUTHEN_TRAP 2
  1081. #define REG_PORT_MRI_INDEX__4 0x0804
  1082. #define MRI_INDEX_P_M 0x7
  1083. #define MRI_INDEX_P_S 16
  1084. #define MRI_INDEX_Q_M 0x3
  1085. #define MRI_INDEX_Q_S 0
  1086. #define REG_PORT_MRI_TC_MAP__4 0x0808
  1087. #define PORT_TC_MAP_M 0xf
  1088. #define PORT_TC_MAP_S 4
  1089. #define REG_PORT_MRI_POLICE_CTRL__4 0x080C
  1090. #define POLICE_DROP_ALL BIT(10)
  1091. #define POLICE_PACKET_TYPE_M 0x3
  1092. #define POLICE_PACKET_TYPE_S 8
  1093. #define POLICE_PACKET_DROPPED 0
  1094. #define POLICE_PACKET_GREEN 1
  1095. #define POLICE_PACKET_YELLOW 2
  1096. #define POLICE_PACKET_RED 3
  1097. #define PORT_BASED_POLICING BIT(7)
  1098. #define NON_DSCP_COLOR_M 0x3
  1099. #define NON_DSCP_COLOR_S 5
  1100. #define COLOR_MARK_ENABLE BIT(4)
  1101. #define COLOR_REMAP_ENABLE BIT(3)
  1102. #define POLICE_DROP_SRP BIT(2)
  1103. #define POLICE_COLOR_NOT_AWARE BIT(1)
  1104. #define POLICE_ENABLE BIT(0)
  1105. #define REG_PORT_POLICE_COLOR_0__4 0x0810
  1106. #define REG_PORT_POLICE_COLOR_1__4 0x0814
  1107. #define REG_PORT_POLICE_COLOR_2__4 0x0818
  1108. #define REG_PORT_POLICE_COLOR_3__4 0x081C
  1109. #define POLICE_COLOR_MAP_S 2
  1110. #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
  1111. #define REG_PORT_POLICE_RATE__4 0x0820
  1112. #define POLICE_CIR_S 16
  1113. #define POLICE_PIR_S 0
  1114. #define REG_PORT_POLICE_BURST_SIZE__4 0x0824
  1115. #define POLICE_BURST_SIZE_M 0x3FFF
  1116. #define POLICE_CBS_S 16
  1117. #define POLICE_PBS_S 0
  1118. #define REG_PORT_WRED_PM_CTRL_0__4 0x0830
  1119. #define WRED_PM_CTRL_M (BIT(11) - 1)
  1120. #define WRED_PM_MAX_THRESHOLD_S 16
  1121. #define WRED_PM_MIN_THRESHOLD_S 0
  1122. #define REG_PORT_WRED_PM_CTRL_1__4 0x0834
  1123. #define WRED_PM_MULTIPLIER_S 16
  1124. #define WRED_PM_AVG_QUEUE_SIZE_S 0
  1125. #define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840
  1126. #define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844
  1127. #define REG_PORT_WRED_QUEUE_PMON__4 0x0848
  1128. #define WRED_RANDOM_DROP_ENABLE BIT(31)
  1129. #define WRED_PMON_FLUSH BIT(30)
  1130. #define WRED_DROP_GYR_DISABLE BIT(29)
  1131. #define WRED_DROP_YR_DISABLE BIT(28)
  1132. #define WRED_DROP_R_DISABLE BIT(27)
  1133. #define WRED_DROP_ALL BIT(26)
  1134. #define WRED_PMON_M (BIT(24) - 1)
  1135. /* 9 - Shaping */
  1136. #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
  1137. #define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904
  1138. #define MTI_PVID_REPLACE BIT(0)
  1139. #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
  1140. #define MTI_SCHEDULE_MODE_M 0x3
  1141. #define MTI_SCHEDULE_MODE_S 6
  1142. #define MTI_SCHEDULE_STRICT_PRIO 0
  1143. #define MTI_SCHEDULE_WRR 2
  1144. #define MTI_SHAPING_M 0x3
  1145. #define MTI_SHAPING_S 4
  1146. #define MTI_SHAPING_OFF 0
  1147. #define MTI_SHAPING_SRP 1
  1148. #define MTI_SHAPING_TIME_AWARE 2
  1149. #define REG_PORT_MTI_QUEUE_CTRL_1 0x0915
  1150. #define MTI_TX_RATIO_M (BIT(7) - 1)
  1151. #define REG_PORT_MTI_QUEUE_CTRL_2__2 0x0916
  1152. #define REG_PORT_MTI_HI_WATER_MARK 0x0916
  1153. #define REG_PORT_MTI_QUEUE_CTRL_3__2 0x0918
  1154. #define REG_PORT_MTI_LO_WATER_MARK 0x0918
  1155. #define REG_PORT_MTI_QUEUE_CTRL_4__2 0x091A
  1156. #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A
  1157. /* A - QM */
  1158. #define REG_PORT_QM_CTRL__4 0x0A00
  1159. #define PORT_QM_DROP_PRIO_M 0x3
  1160. #define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04
  1161. #define REG_PORT_QM_QUEUE_INDEX__4 0x0A08
  1162. #define PORT_QM_QUEUE_INDEX_S 24
  1163. #define PORT_QM_BURST_SIZE_S 16
  1164. #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
  1165. #define REG_PORT_QM_WATER_MARK__4 0x0A0C
  1166. #define PORT_QM_HI_WATER_MARK_S 16
  1167. #define PORT_QM_LO_WATER_MARK_S 0
  1168. #define PORT_QM_WATER_MARK_M (BIT(11) - 1)
  1169. #define REG_PORT_QM_TX_CNT_0__4 0x0A10
  1170. #define PORT_QM_TX_CNT_USED_S 0
  1171. #define PORT_QM_TX_CNT_M (BIT(11) - 1)
  1172. #define REG_PORT_QM_TX_CNT_1__4 0x0A14
  1173. #define PORT_QM_TX_CNT_CALCULATED_S 16
  1174. #define PORT_QM_TX_CNT_AVAIL_S 0
  1175. /* B - LUE */
  1176. #define REG_PORT_LUE_CTRL 0x0B00
  1177. #define PORT_VLAN_LOOKUP_VID_0 BIT(7)
  1178. #define PORT_INGRESS_FILTER BIT(6)
  1179. #define PORT_DISCARD_NON_VID BIT(5)
  1180. #define PORT_MAC_BASED_802_1X BIT(4)
  1181. #define PORT_SRC_ADDR_FILTER BIT(3)
  1182. #define REG_PORT_LUE_MSTP_INDEX 0x0B01
  1183. #define REG_PORT_LUE_MSTP_STATE 0x0B04
  1184. #define PORT_TX_ENABLE BIT(2)
  1185. #define PORT_RX_ENABLE BIT(1)
  1186. #define PORT_LEARN_DISABLE BIT(0)
  1187. /* C - PTP */
  1188. #define REG_PTP_PORT_RX_DELAY__2 0x0C00
  1189. #define REG_PTP_PORT_TX_DELAY__2 0x0C02
  1190. #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04
  1191. #define REG_PTP_PORT_XDELAY_TS 0x0C08
  1192. #define REG_PTP_PORT_XDELAY_TS_H 0x0C08
  1193. #define REG_PTP_PORT_XDELAY_TS_L 0x0C0A
  1194. #define REG_PTP_PORT_SYNC_TS 0x0C0C
  1195. #define REG_PTP_PORT_SYNC_TS_H 0x0C0C
  1196. #define REG_PTP_PORT_SYNC_TS_L 0x0C0E
  1197. #define REG_PTP_PORT_PDRESP_TS 0x0C10
  1198. #define REG_PTP_PORT_PDRESP_TS_H 0x0C10
  1199. #define REG_PTP_PORT_PDRESP_TS_L 0x0C12
  1200. #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14
  1201. #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16
  1202. #define PTP_PORT_SYNC_INT BIT(15)
  1203. #define PTP_PORT_XDELAY_REQ_INT BIT(14)
  1204. #define PTP_PORT_PDELAY_RESP_INT BIT(13)
  1205. #define REG_PTP_PORT_LINK_DELAY__4 0x0C18
  1206. #define PRIO_QUEUES 4
  1207. #define RX_PRIO_QUEUES 8
  1208. #define KS_PRIO_IN_REG 2
  1209. #define TOTAL_PORT_NUM 7
  1210. #define KSZ9477_COUNTER_NUM 0x20
  1211. #define TOTAL_KSZ9477_COUNTER_NUM (KSZ9477_COUNTER_NUM + 2 + 2)
  1212. #define SWITCH_COUNTER_NUM KSZ9477_COUNTER_NUM
  1213. #define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ9477_COUNTER_NUM
  1214. #define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_0
  1215. #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL
  1216. #define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL
  1217. #define P_STP_CTRL REG_PORT_LUE_MSTP_STATE
  1218. #define P_PHY_CTRL REG_PORT_PHY_CTRL
  1219. #define P_NEG_RESTART_CTRL REG_PORT_PHY_CTRL
  1220. #define P_LINK_STATUS REG_PORT_PHY_STATUS
  1221. #define P_SPEED_STATUS REG_PORT_PHY_PHY_CTRL
  1222. #define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT
  1223. #define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_1
  1224. #define S_MIRROR_CTRL REG_SW_MRI_CTRL_0
  1225. #define S_REPLACE_VID_CTRL REG_SW_MAC_CTRL_2
  1226. #define S_802_1P_PRIO_CTRL REG_SW_MAC_802_1P_MAP_0
  1227. #define S_TOS_PRIO_CTRL REG_SW_MAC_TOS_PRIO_0
  1228. #define S_FLUSH_TABLE_CTRL REG_SW_LUE_CTRL_1
  1229. #define SW_FLUSH_DYN_MAC_TABLE SW_FLUSH_MSTP_TABLE
  1230. #define MAX_TIMESTAMP_UNIT 2
  1231. #define MAX_TRIG_UNIT 3
  1232. #define MAX_TIMESTAMP_EVENT_UNIT 8
  1233. #define MAX_GPIO 4
  1234. #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
  1235. #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)
  1236. /* Driver set switch broadcast storm protection at 10% rate. */
  1237. #define BROADCAST_STORM_PROT_RATE 10
  1238. /* 148,800 frames * 67 ms / 100 */
  1239. #define BROADCAST_STORM_VALUE 9969
  1240. #endif /* KSZ9477_REGS_H */