mt7530.h 14 KB

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  1. /*
  2. * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef __MT7530_H
  14. #define __MT7530_H
  15. #define MT7530_NUM_PORTS 7
  16. #define MT7530_CPU_PORT 6
  17. #define MT7530_NUM_FDB_RECORDS 2048
  18. #define MT7530_ALL_MEMBERS 0xff
  19. #define NUM_TRGMII_CTRL 5
  20. #define TRGMII_BASE(x) (0x10000 + (x))
  21. /* Registers to ethsys access */
  22. #define ETHSYS_CLKCFG0 0x2c
  23. #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
  24. #define SYSC_REG_RSTCTRL 0x34
  25. #define RESET_MCM BIT(2)
  26. /* Registers to mac forward control for unknown frames */
  27. #define MT7530_MFC 0x10
  28. #define BC_FFP(x) (((x) & 0xff) << 24)
  29. #define UNM_FFP(x) (((x) & 0xff) << 16)
  30. #define UNM_FFP_MASK UNM_FFP(~0)
  31. #define UNU_FFP(x) (((x) & 0xff) << 8)
  32. #define UNU_FFP_MASK UNU_FFP(~0)
  33. /* Registers for address table access */
  34. #define MT7530_ATA1 0x74
  35. #define STATIC_EMP 0
  36. #define STATIC_ENT 3
  37. #define MT7530_ATA2 0x78
  38. /* Register for address table write data */
  39. #define MT7530_ATWD 0x7c
  40. /* Register for address table control */
  41. #define MT7530_ATC 0x80
  42. #define ATC_HASH (((x) & 0xfff) << 16)
  43. #define ATC_BUSY BIT(15)
  44. #define ATC_SRCH_END BIT(14)
  45. #define ATC_SRCH_HIT BIT(13)
  46. #define ATC_INVALID BIT(12)
  47. #define ATC_MAT(x) (((x) & 0xf) << 8)
  48. #define ATC_MAT_MACTAB ATC_MAT(0)
  49. enum mt7530_fdb_cmd {
  50. MT7530_FDB_READ = 0,
  51. MT7530_FDB_WRITE = 1,
  52. MT7530_FDB_FLUSH = 2,
  53. MT7530_FDB_START = 4,
  54. MT7530_FDB_NEXT = 5,
  55. };
  56. /* Registers for table search read address */
  57. #define MT7530_TSRA1 0x84
  58. #define MAC_BYTE_0 24
  59. #define MAC_BYTE_1 16
  60. #define MAC_BYTE_2 8
  61. #define MAC_BYTE_3 0
  62. #define MAC_BYTE_MASK 0xff
  63. #define MT7530_TSRA2 0x88
  64. #define MAC_BYTE_4 24
  65. #define MAC_BYTE_5 16
  66. #define CVID 0
  67. #define CVID_MASK 0xfff
  68. #define MT7530_ATRD 0x8C
  69. #define AGE_TIMER 24
  70. #define AGE_TIMER_MASK 0xff
  71. #define PORT_MAP 4
  72. #define PORT_MAP_MASK 0xff
  73. #define ENT_STATUS 2
  74. #define ENT_STATUS_MASK 0x3
  75. /* Register for vlan table control */
  76. #define MT7530_VTCR 0x90
  77. #define VTCR_BUSY BIT(31)
  78. #define VTCR_INVALID BIT(16)
  79. #define VTCR_FUNC(x) (((x) & 0xf) << 12)
  80. #define VTCR_VID ((x) & 0xfff)
  81. enum mt7530_vlan_cmd {
  82. /* Read/Write the specified VID entry from VAWD register based
  83. * on VID.
  84. */
  85. MT7530_VTCR_RD_VID = 0,
  86. MT7530_VTCR_WR_VID = 1,
  87. };
  88. /* Register for setup vlan and acl write data */
  89. #define MT7530_VAWD1 0x94
  90. #define PORT_STAG BIT(31)
  91. /* Independent VLAN Learning */
  92. #define IVL_MAC BIT(30)
  93. /* Per VLAN Egress Tag Control */
  94. #define VTAG_EN BIT(28)
  95. /* VLAN Member Control */
  96. #define PORT_MEM(x) (((x) & 0xff) << 16)
  97. /* VLAN Entry Valid */
  98. #define VLAN_VALID BIT(0)
  99. #define PORT_MEM_SHFT 16
  100. #define PORT_MEM_MASK 0xff
  101. #define MT7530_VAWD2 0x98
  102. /* Egress Tag Control */
  103. #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
  104. #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
  105. enum mt7530_vlan_egress_attr {
  106. MT7530_VLAN_EGRESS_UNTAG = 0,
  107. MT7530_VLAN_EGRESS_TAG = 2,
  108. MT7530_VLAN_EGRESS_STACK = 3,
  109. };
  110. /* Register for port STP state control */
  111. #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
  112. #define FID_PST(x) ((x) & 0x3)
  113. #define FID_PST_MASK FID_PST(0x3)
  114. enum mt7530_stp_state {
  115. MT7530_STP_DISABLED = 0,
  116. MT7530_STP_BLOCKING = 1,
  117. MT7530_STP_LISTENING = 1,
  118. MT7530_STP_LEARNING = 2,
  119. MT7530_STP_FORWARDING = 3
  120. };
  121. /* Register for port control */
  122. #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
  123. #define PORT_VLAN(x) ((x) & 0x3)
  124. enum mt7530_port_mode {
  125. /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
  126. MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
  127. /* Fallback Mode: Forward received frames with ingress ports that do
  128. * not belong to the VLAN member. Frames whose VID is not listed on
  129. * the VLAN table are forwarded by the PCR_MATRIX members.
  130. */
  131. MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
  132. /* Security Mode: Discard any frame due to ingress membership
  133. * violation or VID missed on the VLAN table.
  134. */
  135. MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
  136. };
  137. #define PCR_MATRIX(x) (((x) & 0xff) << 16)
  138. #define PORT_PRI(x) (((x) & 0x7) << 24)
  139. #define EG_TAG(x) (((x) & 0x3) << 28)
  140. #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
  141. #define PCR_MATRIX_CLR PCR_MATRIX(0)
  142. #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
  143. /* Register for port security control */
  144. #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
  145. #define SA_DIS BIT(4)
  146. /* Register for port vlan control */
  147. #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
  148. #define PORT_SPEC_TAG BIT(5)
  149. #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
  150. #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
  151. #define VLAN_ATTR(x) (((x) & 0x3) << 6)
  152. #define VLAN_ATTR_MASK VLAN_ATTR(3)
  153. enum mt7530_vlan_port_eg_tag {
  154. MT7530_VLAN_EG_DISABLED = 0,
  155. MT7530_VLAN_EG_CONSISTENT = 1,
  156. };
  157. enum mt7530_vlan_port_attr {
  158. MT7530_VLAN_USER = 0,
  159. MT7530_VLAN_TRANSPARENT = 3,
  160. };
  161. #define STAG_VPID (((x) & 0xffff) << 16)
  162. /* Register for port port-and-protocol based vlan 1 control */
  163. #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
  164. #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
  165. #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
  166. #define G0_PORT_VID_DEF G0_PORT_VID(1)
  167. /* Register for port MAC control register */
  168. #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
  169. #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
  170. #define PMCR_MAC_MODE BIT(16)
  171. #define PMCR_FORCE_MODE BIT(15)
  172. #define PMCR_TX_EN BIT(14)
  173. #define PMCR_RX_EN BIT(13)
  174. #define PMCR_BACKOFF_EN BIT(9)
  175. #define PMCR_BACKPR_EN BIT(8)
  176. #define PMCR_TX_FC_EN BIT(5)
  177. #define PMCR_RX_FC_EN BIT(4)
  178. #define PMCR_FORCE_SPEED_1000 BIT(3)
  179. #define PMCR_FORCE_SPEED_100 BIT(2)
  180. #define PMCR_FORCE_FDX BIT(1)
  181. #define PMCR_FORCE_LNK BIT(0)
  182. #define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
  183. PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
  184. PMCR_TX_EN | PMCR_RX_EN | \
  185. PMCR_TX_FC_EN | PMCR_RX_FC_EN)
  186. #define PMCR_CPUP_LINK (PMCR_COMMON_LINK | PMCR_FORCE_MODE | \
  187. PMCR_FORCE_SPEED_1000 | \
  188. PMCR_FORCE_FDX | \
  189. PMCR_FORCE_LNK)
  190. #define PMCR_USERP_LINK PMCR_COMMON_LINK
  191. #define PMCR_FIXED_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
  192. PMCR_FORCE_MODE | PMCR_TX_EN | \
  193. PMCR_RX_EN | PMCR_BACKPR_EN | \
  194. PMCR_BACKOFF_EN | \
  195. PMCR_FORCE_SPEED_1000 | \
  196. PMCR_FORCE_FDX | \
  197. PMCR_FORCE_LNK)
  198. #define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
  199. PMCR_TX_FC_EN | PMCR_RX_FC_EN)
  200. #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
  201. /* Register for MIB */
  202. #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
  203. #define MT7530_MIB_CCR 0x4fe0
  204. #define CCR_MIB_ENABLE BIT(31)
  205. #define CCR_RX_OCT_CNT_GOOD BIT(7)
  206. #define CCR_RX_OCT_CNT_BAD BIT(6)
  207. #define CCR_TX_OCT_CNT_GOOD BIT(5)
  208. #define CCR_TX_OCT_CNT_BAD BIT(4)
  209. #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
  210. CCR_RX_OCT_CNT_BAD | \
  211. CCR_TX_OCT_CNT_GOOD | \
  212. CCR_TX_OCT_CNT_BAD)
  213. #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
  214. CCR_RX_OCT_CNT_GOOD | \
  215. CCR_RX_OCT_CNT_BAD | \
  216. CCR_TX_OCT_CNT_GOOD | \
  217. CCR_TX_OCT_CNT_BAD)
  218. /* Register for system reset */
  219. #define MT7530_SYS_CTRL 0x7000
  220. #define SYS_CTRL_PHY_RST BIT(2)
  221. #define SYS_CTRL_SW_RST BIT(1)
  222. #define SYS_CTRL_REG_RST BIT(0)
  223. /* Register for hw trap status */
  224. #define MT7530_HWTRAP 0x7800
  225. /* Register for hw trap modification */
  226. #define MT7530_MHWTRAP 0x7804
  227. #define MHWTRAP_MANUAL BIT(16)
  228. #define MHWTRAP_P5_MAC_SEL BIT(13)
  229. #define MHWTRAP_P6_DIS BIT(8)
  230. #define MHWTRAP_P5_RGMII_MODE BIT(7)
  231. #define MHWTRAP_P5_DIS BIT(6)
  232. #define MHWTRAP_PHY_ACCESS BIT(5)
  233. /* Register for TOP signal control */
  234. #define MT7530_TOP_SIG_CTRL 0x7808
  235. #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
  236. #define MT7530_IO_DRV_CR 0x7810
  237. #define P5_IO_CLK_DRV(x) ((x) & 0x3)
  238. #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
  239. #define MT7530_P6ECR 0x7830
  240. #define P6_INTF_MODE_MASK 0x3
  241. #define P6_INTF_MODE(x) ((x) & 0x3)
  242. /* Registers for TRGMII on the both side */
  243. #define MT7530_TRGMII_RCK_CTRL 0x7a00
  244. #define GSW_TRGMII_RCK_CTRL 0x300
  245. #define RX_RST BIT(31)
  246. #define RXC_DQSISEL BIT(30)
  247. #define DQSI1_TAP_MASK (0x7f << 8)
  248. #define DQSI0_TAP_MASK 0x7f
  249. #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
  250. #define DQSI0_TAP(x) ((x) & 0x7f)
  251. #define MT7530_TRGMII_RCK_RTT 0x7a04
  252. #define GSW_TRGMII_RCK_RTT 0x304
  253. #define DQS1_GATE BIT(31)
  254. #define DQS0_GATE BIT(30)
  255. #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
  256. #define GSW_TRGMII_RD(x) (0x310 + (x) * 8)
  257. #define BSLIP_EN BIT(31)
  258. #define EDGE_CHK BIT(30)
  259. #define RD_TAP_MASK 0x7f
  260. #define RD_TAP(x) ((x) & 0x7f)
  261. #define GSW_TRGMII_TXCTRL 0x340
  262. #define MT7530_TRGMII_TXCTRL 0x7a40
  263. #define TRAIN_TXEN BIT(31)
  264. #define TXC_INV BIT(30)
  265. #define TX_RST BIT(28)
  266. #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
  267. #define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i))
  268. #define TD_DM_DRVP(x) ((x) & 0xf)
  269. #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
  270. #define GSW_INTF_MODE 0x390
  271. #define INTF_MODE_TRGMII BIT(1)
  272. #define MT7530_TRGMII_TCK_CTRL 0x7a78
  273. #define TCK_TAP(x) (((x) & 0xf) << 8)
  274. #define MT7530_P5RGMIIRXCR 0x7b00
  275. #define CSR_RGMII_EDGE_ALIGN BIT(8)
  276. #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
  277. #define MT7530_P5RGMIITXCR 0x7b04
  278. #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
  279. #define MT7530_CREV 0x7ffc
  280. #define CHIP_NAME_SHIFT 16
  281. #define MT7530_ID 0x7530
  282. /* Registers for core PLL access through mmd indirect */
  283. #define CORE_PLL_GROUP2 0x401
  284. #define RG_SYSPLL_EN_NORMAL BIT(15)
  285. #define RG_SYSPLL_VODEN BIT(14)
  286. #define RG_SYSPLL_LF BIT(13)
  287. #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
  288. #define RG_SYSPLL_LVROD_EN BIT(10)
  289. #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
  290. #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
  291. #define RG_SYSPLL_FBKSEL BIT(4)
  292. #define RT_SYSPLL_EN_AFE_OLT BIT(0)
  293. #define CORE_PLL_GROUP4 0x403
  294. #define RG_SYSPLL_DDSFBK_EN BIT(12)
  295. #define RG_SYSPLL_BIAS_EN BIT(11)
  296. #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
  297. #define CORE_PLL_GROUP5 0x404
  298. #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
  299. #define CORE_PLL_GROUP6 0x405
  300. #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
  301. #define CORE_PLL_GROUP7 0x406
  302. #define RG_LCDDS_PWDB BIT(15)
  303. #define RG_LCDDS_ISO_EN BIT(13)
  304. #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
  305. #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
  306. #define CORE_PLL_GROUP10 0x409
  307. #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
  308. #define CORE_PLL_GROUP11 0x40a
  309. #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
  310. #define CORE_GSWPLL_GRP1 0x40d
  311. #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
  312. #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
  313. #define RG_GSWPLL_EN_PRE BIT(11)
  314. #define RG_GSWPLL_FBKSEL BIT(10)
  315. #define RG_GSWPLL_BP BIT(9)
  316. #define RG_GSWPLL_BR BIT(8)
  317. #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
  318. #define CORE_GSWPLL_GRP2 0x40e
  319. #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
  320. #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
  321. #define CORE_TRGMII_GSW_CLK_CG 0x410
  322. #define REG_GSWCK_EN BIT(0)
  323. #define REG_TRGMIICK_EN BIT(1)
  324. #define MIB_DESC(_s, _o, _n) \
  325. { \
  326. .size = (_s), \
  327. .offset = (_o), \
  328. .name = (_n), \
  329. }
  330. struct mt7530_mib_desc {
  331. unsigned int size;
  332. unsigned int offset;
  333. const char *name;
  334. };
  335. struct mt7530_fdb {
  336. u16 vid;
  337. u8 port_mask;
  338. u8 aging;
  339. u8 mac[6];
  340. bool noarp;
  341. };
  342. /* struct mt7530_port - This is the main data structure for holding the state
  343. * of the port.
  344. * @enable: The status used for show port is enabled or not.
  345. * @pm: The matrix used to show all connections with the port.
  346. * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
  347. * untagged frames will be assigned to the related VLAN.
  348. * @vlan_filtering: The flags indicating whether the port that can recognize
  349. * VLAN-tagged frames.
  350. */
  351. struct mt7530_port {
  352. bool enable;
  353. u32 pm;
  354. u16 pvid;
  355. bool vlan_filtering;
  356. };
  357. /* struct mt7530_priv - This is the main data structure for holding the state
  358. * of the driver
  359. * @dev: The device pointer
  360. * @ds: The pointer to the dsa core structure
  361. * @bus: The bus used for the device and built-in PHY
  362. * @rstc: The pointer to reset control used by MCM
  363. * @ethernet: The regmap used for access TRGMII-based registers
  364. * @core_pwr: The power supplied into the core
  365. * @io_pwr: The power supplied into the I/O
  366. * @reset: The descriptor for GPIO line tied to its reset pin
  367. * @mcm: Flag for distinguishing if standalone IC or module
  368. * coupling
  369. * @ports: Holding the state among ports
  370. * @reg_mutex: The lock for protecting among process accessing
  371. * registers
  372. */
  373. struct mt7530_priv {
  374. struct device *dev;
  375. struct dsa_switch *ds;
  376. struct mii_bus *bus;
  377. struct reset_control *rstc;
  378. struct regmap *ethernet;
  379. struct regulator *core_pwr;
  380. struct regulator *io_pwr;
  381. struct gpio_desc *reset;
  382. bool mcm;
  383. struct mt7530_port ports[MT7530_NUM_PORTS];
  384. /* protect among processes for registers access*/
  385. struct mutex reg_mutex;
  386. };
  387. struct mt7530_hw_vlan_entry {
  388. int port;
  389. u8 old_members;
  390. bool untagged;
  391. };
  392. static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
  393. int port, bool untagged)
  394. {
  395. e->port = port;
  396. e->untagged = untagged;
  397. }
  398. typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
  399. struct mt7530_hw_vlan_entry *);
  400. struct mt7530_hw_stats {
  401. const char *string;
  402. u16 reg;
  403. u8 sizeof_stat;
  404. };
  405. struct mt7530_dummy_poll {
  406. struct mt7530_priv *priv;
  407. u32 reg;
  408. };
  409. static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
  410. struct mt7530_priv *priv, u32 reg)
  411. {
  412. p->priv = priv;
  413. p->reg = reg;
  414. }
  415. #endif /* __MT7530_H */