global1_atu.c 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403
  1. /*
  2. * Marvell 88E6xxx Address Translation Unit (ATU) support
  3. *
  4. * Copyright (c) 2008 Marvell Semiconductor
  5. * Copyright (c) 2017 Savoir-faire Linux, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include <linux/interrupt.h>
  13. #include <linux/irqdomain.h>
  14. #include "chip.h"
  15. #include "global1.h"
  16. /* Offset 0x01: ATU FID Register */
  17. static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
  18. {
  19. return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff);
  20. }
  21. /* Offset 0x0A: ATU Control Register */
  22. int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
  23. {
  24. u16 val;
  25. int err;
  26. err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
  27. if (err)
  28. return err;
  29. if (learn2all)
  30. val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
  31. else
  32. val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
  33. return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
  34. }
  35. int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
  36. unsigned int msecs)
  37. {
  38. const unsigned int coeff = chip->info->age_time_coeff;
  39. const unsigned int min = 0x01 * coeff;
  40. const unsigned int max = 0xff * coeff;
  41. u8 age_time;
  42. u16 val;
  43. int err;
  44. if (msecs < min || msecs > max)
  45. return -ERANGE;
  46. /* Round to nearest multiple of coeff */
  47. age_time = (msecs + coeff / 2) / coeff;
  48. err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
  49. if (err)
  50. return err;
  51. /* AgeTime is 11:4 bits */
  52. val &= ~0xff0;
  53. val |= age_time << 4;
  54. err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
  55. if (err)
  56. return err;
  57. dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time,
  58. age_time * coeff);
  59. return 0;
  60. }
  61. /* Offset 0x0B: ATU Operation Register */
  62. static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
  63. {
  64. return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_ATU_OP,
  65. MV88E6XXX_G1_ATU_OP_BUSY);
  66. }
  67. static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
  68. {
  69. u16 val;
  70. int err;
  71. /* FID bits are dispatched all around gradually as more are supported */
  72. if (mv88e6xxx_num_databases(chip) > 256) {
  73. err = mv88e6xxx_g1_atu_fid_write(chip, fid);
  74. if (err)
  75. return err;
  76. } else {
  77. if (mv88e6xxx_num_databases(chip) > 16) {
  78. /* ATU DBNum[7:4] are located in ATU Control 15:12 */
  79. err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
  80. &val);
  81. if (err)
  82. return err;
  83. val = (val & 0x0fff) | ((fid << 8) & 0xf000);
  84. err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL,
  85. val);
  86. if (err)
  87. return err;
  88. }
  89. /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
  90. op |= fid & 0xf;
  91. }
  92. err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
  93. MV88E6XXX_G1_ATU_OP_BUSY | op);
  94. if (err)
  95. return err;
  96. return mv88e6xxx_g1_atu_op_wait(chip);
  97. }
  98. /* Offset 0x0C: ATU Data Register */
  99. static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
  100. struct mv88e6xxx_atu_entry *entry)
  101. {
  102. u16 val;
  103. int err;
  104. err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val);
  105. if (err)
  106. return err;
  107. entry->state = val & 0xf;
  108. if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
  109. entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK);
  110. entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip);
  111. }
  112. return 0;
  113. }
  114. static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
  115. struct mv88e6xxx_atu_entry *entry)
  116. {
  117. u16 data = entry->state & 0xf;
  118. if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
  119. if (entry->trunk)
  120. data |= MV88E6XXX_G1_ATU_DATA_TRUNK;
  121. data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4;
  122. }
  123. return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data);
  124. }
  125. /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
  126. * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
  127. * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
  128. */
  129. static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
  130. struct mv88e6xxx_atu_entry *entry)
  131. {
  132. u16 val;
  133. int i, err;
  134. for (i = 0; i < 3; i++) {
  135. err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val);
  136. if (err)
  137. return err;
  138. entry->mac[i * 2] = val >> 8;
  139. entry->mac[i * 2 + 1] = val & 0xff;
  140. }
  141. return 0;
  142. }
  143. static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
  144. struct mv88e6xxx_atu_entry *entry)
  145. {
  146. u16 val;
  147. int i, err;
  148. for (i = 0; i < 3; i++) {
  149. val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1];
  150. err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val);
  151. if (err)
  152. return err;
  153. }
  154. return 0;
  155. }
  156. /* Address Translation Unit operations */
  157. int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
  158. struct mv88e6xxx_atu_entry *entry)
  159. {
  160. int err;
  161. err = mv88e6xxx_g1_atu_op_wait(chip);
  162. if (err)
  163. return err;
  164. /* Write the MAC address to iterate from only once */
  165. if (entry->state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
  166. err = mv88e6xxx_g1_atu_mac_write(chip, entry);
  167. if (err)
  168. return err;
  169. }
  170. err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
  171. if (err)
  172. return err;
  173. err = mv88e6xxx_g1_atu_data_read(chip, entry);
  174. if (err)
  175. return err;
  176. return mv88e6xxx_g1_atu_mac_read(chip, entry);
  177. }
  178. int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
  179. struct mv88e6xxx_atu_entry *entry)
  180. {
  181. int err;
  182. err = mv88e6xxx_g1_atu_op_wait(chip);
  183. if (err)
  184. return err;
  185. err = mv88e6xxx_g1_atu_mac_write(chip, entry);
  186. if (err)
  187. return err;
  188. err = mv88e6xxx_g1_atu_data_write(chip, entry);
  189. if (err)
  190. return err;
  191. return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB);
  192. }
  193. static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
  194. struct mv88e6xxx_atu_entry *entry,
  195. bool all)
  196. {
  197. u16 op;
  198. int err;
  199. err = mv88e6xxx_g1_atu_op_wait(chip);
  200. if (err)
  201. return err;
  202. err = mv88e6xxx_g1_atu_data_write(chip, entry);
  203. if (err)
  204. return err;
  205. /* Flush/Move all or non-static entries from all or a given database */
  206. if (all && fid)
  207. op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB;
  208. else if (fid)
  209. op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
  210. else if (all)
  211. op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL;
  212. else
  213. op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC;
  214. return mv88e6xxx_g1_atu_op(chip, fid, op);
  215. }
  216. int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all)
  217. {
  218. struct mv88e6xxx_atu_entry entry = {
  219. .state = 0, /* Null EntryState means Flush */
  220. };
  221. return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
  222. }
  223. static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
  224. int from_port, int to_port, bool all)
  225. {
  226. struct mv88e6xxx_atu_entry entry = { 0 };
  227. unsigned long mask;
  228. int shift;
  229. if (!chip->info->atu_move_port_mask)
  230. return -EOPNOTSUPP;
  231. mask = chip->info->atu_move_port_mask;
  232. shift = bitmap_weight(&mask, 16);
  233. entry.state = 0xf, /* Full EntryState means Move */
  234. entry.portvec = from_port & mask;
  235. entry.portvec |= (to_port & mask) << shift;
  236. return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
  237. }
  238. int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
  239. bool all)
  240. {
  241. int from_port = port;
  242. int to_port = chip->info->atu_move_port_mask;
  243. return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all);
  244. }
  245. static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id)
  246. {
  247. struct mv88e6xxx_chip *chip = dev_id;
  248. struct mv88e6xxx_atu_entry entry;
  249. int spid;
  250. int err;
  251. u16 val;
  252. mutex_lock(&chip->reg_lock);
  253. err = mv88e6xxx_g1_atu_op(chip, 0,
  254. MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION);
  255. if (err)
  256. goto out;
  257. err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val);
  258. if (err)
  259. goto out;
  260. err = mv88e6xxx_g1_atu_data_read(chip, &entry);
  261. if (err)
  262. goto out;
  263. err = mv88e6xxx_g1_atu_mac_read(chip, &entry);
  264. if (err)
  265. goto out;
  266. spid = entry.state;
  267. if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) {
  268. dev_err_ratelimited(chip->dev,
  269. "ATU age out violation for %pM\n",
  270. entry.mac);
  271. }
  272. if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) {
  273. dev_err_ratelimited(chip->dev,
  274. "ATU member violation for %pM portvec %x spid %d\n",
  275. entry.mac, entry.portvec, spid);
  276. chip->ports[spid].atu_member_violation++;
  277. }
  278. if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) {
  279. dev_err_ratelimited(chip->dev,
  280. "ATU miss violation for %pM portvec %x spid %d\n",
  281. entry.mac, entry.portvec, spid);
  282. chip->ports[spid].atu_miss_violation++;
  283. }
  284. if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) {
  285. dev_err_ratelimited(chip->dev,
  286. "ATU full violation for %pM portvec %x spid %d\n",
  287. entry.mac, entry.portvec, spid);
  288. chip->ports[spid].atu_full_violation++;
  289. }
  290. mutex_unlock(&chip->reg_lock);
  291. return IRQ_HANDLED;
  292. out:
  293. mutex_unlock(&chip->reg_lock);
  294. dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n",
  295. err);
  296. return IRQ_HANDLED;
  297. }
  298. int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip)
  299. {
  300. int err;
  301. chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
  302. MV88E6XXX_G1_STS_IRQ_ATU_PROB);
  303. if (chip->atu_prob_irq < 0)
  304. return chip->atu_prob_irq;
  305. err = request_threaded_irq(chip->atu_prob_irq, NULL,
  306. mv88e6xxx_g1_atu_prob_irq_thread_fn,
  307. IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob",
  308. chip);
  309. if (err)
  310. irq_dispose_mapping(chip->atu_prob_irq);
  311. return err;
  312. }
  313. void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip)
  314. {
  315. free_irq(chip->atu_prob_irq, chip);
  316. irq_dispose_mapping(chip->atu_prob_irq);
  317. }