qca8k.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
  4. * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  6. * Copyright (c) 2016 John Crispin <john@phrozen.org>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/phy.h>
  10. #include <linux/netdevice.h>
  11. #include <net/dsa.h>
  12. #include <linux/of_net.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/if_bridge.h>
  15. #include <linux/mdio.h>
  16. #include <linux/etherdevice.h>
  17. #include "qca8k.h"
  18. #define MIB_DESC(_s, _o, _n) \
  19. { \
  20. .size = (_s), \
  21. .offset = (_o), \
  22. .name = (_n), \
  23. }
  24. static const struct qca8k_mib_desc ar8327_mib[] = {
  25. MIB_DESC(1, 0x00, "RxBroad"),
  26. MIB_DESC(1, 0x04, "RxPause"),
  27. MIB_DESC(1, 0x08, "RxMulti"),
  28. MIB_DESC(1, 0x0c, "RxFcsErr"),
  29. MIB_DESC(1, 0x10, "RxAlignErr"),
  30. MIB_DESC(1, 0x14, "RxRunt"),
  31. MIB_DESC(1, 0x18, "RxFragment"),
  32. MIB_DESC(1, 0x1c, "Rx64Byte"),
  33. MIB_DESC(1, 0x20, "Rx128Byte"),
  34. MIB_DESC(1, 0x24, "Rx256Byte"),
  35. MIB_DESC(1, 0x28, "Rx512Byte"),
  36. MIB_DESC(1, 0x2c, "Rx1024Byte"),
  37. MIB_DESC(1, 0x30, "Rx1518Byte"),
  38. MIB_DESC(1, 0x34, "RxMaxByte"),
  39. MIB_DESC(1, 0x38, "RxTooLong"),
  40. MIB_DESC(2, 0x3c, "RxGoodByte"),
  41. MIB_DESC(2, 0x44, "RxBadByte"),
  42. MIB_DESC(1, 0x4c, "RxOverFlow"),
  43. MIB_DESC(1, 0x50, "Filtered"),
  44. MIB_DESC(1, 0x54, "TxBroad"),
  45. MIB_DESC(1, 0x58, "TxPause"),
  46. MIB_DESC(1, 0x5c, "TxMulti"),
  47. MIB_DESC(1, 0x60, "TxUnderRun"),
  48. MIB_DESC(1, 0x64, "Tx64Byte"),
  49. MIB_DESC(1, 0x68, "Tx128Byte"),
  50. MIB_DESC(1, 0x6c, "Tx256Byte"),
  51. MIB_DESC(1, 0x70, "Tx512Byte"),
  52. MIB_DESC(1, 0x74, "Tx1024Byte"),
  53. MIB_DESC(1, 0x78, "Tx1518Byte"),
  54. MIB_DESC(1, 0x7c, "TxMaxByte"),
  55. MIB_DESC(1, 0x80, "TxOverSize"),
  56. MIB_DESC(2, 0x84, "TxByte"),
  57. MIB_DESC(1, 0x8c, "TxCollision"),
  58. MIB_DESC(1, 0x90, "TxAbortCol"),
  59. MIB_DESC(1, 0x94, "TxMultiCol"),
  60. MIB_DESC(1, 0x98, "TxSingleCol"),
  61. MIB_DESC(1, 0x9c, "TxExcDefer"),
  62. MIB_DESC(1, 0xa0, "TxDefer"),
  63. MIB_DESC(1, 0xa4, "TxLateCol"),
  64. };
  65. /* The 32bit switch registers are accessed indirectly. To achieve this we need
  66. * to set the page of the register. Track the last page that was set to reduce
  67. * mdio writes
  68. */
  69. static u16 qca8k_current_page = 0xffff;
  70. static void
  71. qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  72. {
  73. regaddr >>= 1;
  74. *r1 = regaddr & 0x1e;
  75. regaddr >>= 5;
  76. *r2 = regaddr & 0x7;
  77. regaddr >>= 3;
  78. *page = regaddr & 0x3ff;
  79. }
  80. static u32
  81. qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
  82. {
  83. u32 val;
  84. int ret;
  85. ret = bus->read(bus, phy_id, regnum);
  86. if (ret >= 0) {
  87. val = ret;
  88. ret = bus->read(bus, phy_id, regnum + 1);
  89. val |= ret << 16;
  90. }
  91. if (ret < 0) {
  92. dev_err_ratelimited(&bus->dev,
  93. "failed to read qca8k 32bit register\n");
  94. return ret;
  95. }
  96. return val;
  97. }
  98. static void
  99. qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  100. {
  101. u16 lo, hi;
  102. int ret;
  103. lo = val & 0xffff;
  104. hi = (u16)(val >> 16);
  105. ret = bus->write(bus, phy_id, regnum, lo);
  106. if (ret >= 0)
  107. ret = bus->write(bus, phy_id, regnum + 1, hi);
  108. if (ret < 0)
  109. dev_err_ratelimited(&bus->dev,
  110. "failed to write qca8k 32bit register\n");
  111. }
  112. static void
  113. qca8k_set_page(struct mii_bus *bus, u16 page)
  114. {
  115. if (page == qca8k_current_page)
  116. return;
  117. if (bus->write(bus, 0x18, 0, page) < 0)
  118. dev_err_ratelimited(&bus->dev,
  119. "failed to set qca8k page\n");
  120. qca8k_current_page = page;
  121. }
  122. static u32
  123. qca8k_read(struct qca8k_priv *priv, u32 reg)
  124. {
  125. u16 r1, r2, page;
  126. u32 val;
  127. qca8k_split_addr(reg, &r1, &r2, &page);
  128. mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
  129. qca8k_set_page(priv->bus, page);
  130. val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
  131. mutex_unlock(&priv->bus->mdio_lock);
  132. return val;
  133. }
  134. static void
  135. qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
  136. {
  137. u16 r1, r2, page;
  138. qca8k_split_addr(reg, &r1, &r2, &page);
  139. mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
  140. qca8k_set_page(priv->bus, page);
  141. qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
  142. mutex_unlock(&priv->bus->mdio_lock);
  143. }
  144. static u32
  145. qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
  146. {
  147. u16 r1, r2, page;
  148. u32 ret;
  149. qca8k_split_addr(reg, &r1, &r2, &page);
  150. mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
  151. qca8k_set_page(priv->bus, page);
  152. ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
  153. ret &= ~mask;
  154. ret |= val;
  155. qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
  156. mutex_unlock(&priv->bus->mdio_lock);
  157. return ret;
  158. }
  159. static void
  160. qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
  161. {
  162. qca8k_rmw(priv, reg, 0, val);
  163. }
  164. static void
  165. qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
  166. {
  167. qca8k_rmw(priv, reg, val, 0);
  168. }
  169. static int
  170. qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
  171. {
  172. struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
  173. *val = qca8k_read(priv, reg);
  174. return 0;
  175. }
  176. static int
  177. qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
  178. {
  179. struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
  180. qca8k_write(priv, reg, val);
  181. return 0;
  182. }
  183. static const struct regmap_range qca8k_readable_ranges[] = {
  184. regmap_reg_range(0x0000, 0x00e4), /* Global control */
  185. regmap_reg_range(0x0100, 0x0168), /* EEE control */
  186. regmap_reg_range(0x0200, 0x0270), /* Parser control */
  187. regmap_reg_range(0x0400, 0x0454), /* ACL */
  188. regmap_reg_range(0x0600, 0x0718), /* Lookup */
  189. regmap_reg_range(0x0800, 0x0b70), /* QM */
  190. regmap_reg_range(0x0c00, 0x0c80), /* PKT */
  191. regmap_reg_range(0x0e00, 0x0e98), /* L3 */
  192. regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
  193. regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
  194. regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
  195. regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
  196. regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
  197. regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
  198. regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
  199. };
  200. static const struct regmap_access_table qca8k_readable_table = {
  201. .yes_ranges = qca8k_readable_ranges,
  202. .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
  203. };
  204. static struct regmap_config qca8k_regmap_config = {
  205. .reg_bits = 16,
  206. .val_bits = 32,
  207. .reg_stride = 4,
  208. .max_register = 0x16ac, /* end MIB - Port6 range */
  209. .reg_read = qca8k_regmap_read,
  210. .reg_write = qca8k_regmap_write,
  211. .rd_table = &qca8k_readable_table,
  212. };
  213. static int
  214. qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
  215. {
  216. unsigned long timeout;
  217. timeout = jiffies + msecs_to_jiffies(20);
  218. /* loop until the busy flag has cleared */
  219. do {
  220. u32 val = qca8k_read(priv, reg);
  221. int busy = val & mask;
  222. if (!busy)
  223. break;
  224. cond_resched();
  225. } while (!time_after_eq(jiffies, timeout));
  226. return time_after_eq(jiffies, timeout);
  227. }
  228. static void
  229. qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
  230. {
  231. u32 reg[4];
  232. int i;
  233. /* load the ARL table into an array */
  234. for (i = 0; i < 4; i++)
  235. reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
  236. /* vid - 83:72 */
  237. fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
  238. /* aging - 67:64 */
  239. fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
  240. /* portmask - 54:48 */
  241. fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
  242. /* mac - 47:0 */
  243. fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
  244. fdb->mac[1] = reg[1] & 0xff;
  245. fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
  246. fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
  247. fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
  248. fdb->mac[5] = reg[0] & 0xff;
  249. }
  250. static void
  251. qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
  252. u8 aging)
  253. {
  254. u32 reg[3] = { 0 };
  255. int i;
  256. /* vid - 83:72 */
  257. reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
  258. /* aging - 67:64 */
  259. reg[2] |= aging & QCA8K_ATU_STATUS_M;
  260. /* portmask - 54:48 */
  261. reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
  262. /* mac - 47:0 */
  263. reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
  264. reg[1] |= mac[1];
  265. reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
  266. reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
  267. reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
  268. reg[0] |= mac[5];
  269. /* load the array into the ARL table */
  270. for (i = 0; i < 3; i++)
  271. qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
  272. }
  273. static int
  274. qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
  275. {
  276. u32 reg;
  277. /* Set the command and FDB index */
  278. reg = QCA8K_ATU_FUNC_BUSY;
  279. reg |= cmd;
  280. if (port >= 0) {
  281. reg |= QCA8K_ATU_FUNC_PORT_EN;
  282. reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
  283. }
  284. /* Write the function register triggering the table access */
  285. qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
  286. /* wait for completion */
  287. if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
  288. return -1;
  289. /* Check for table full violation when adding an entry */
  290. if (cmd == QCA8K_FDB_LOAD) {
  291. reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
  292. if (reg & QCA8K_ATU_FUNC_FULL)
  293. return -1;
  294. }
  295. return 0;
  296. }
  297. static int
  298. qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
  299. {
  300. int ret;
  301. qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
  302. ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
  303. if (ret >= 0)
  304. qca8k_fdb_read(priv, fdb);
  305. return ret;
  306. }
  307. static int
  308. qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
  309. u16 vid, u8 aging)
  310. {
  311. int ret;
  312. mutex_lock(&priv->reg_mutex);
  313. qca8k_fdb_write(priv, vid, port_mask, mac, aging);
  314. ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
  315. mutex_unlock(&priv->reg_mutex);
  316. return ret;
  317. }
  318. static int
  319. qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
  320. {
  321. int ret;
  322. mutex_lock(&priv->reg_mutex);
  323. qca8k_fdb_write(priv, vid, port_mask, mac, 0);
  324. ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
  325. mutex_unlock(&priv->reg_mutex);
  326. return ret;
  327. }
  328. static void
  329. qca8k_fdb_flush(struct qca8k_priv *priv)
  330. {
  331. mutex_lock(&priv->reg_mutex);
  332. qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
  333. mutex_unlock(&priv->reg_mutex);
  334. }
  335. static void
  336. qca8k_mib_init(struct qca8k_priv *priv)
  337. {
  338. mutex_lock(&priv->reg_mutex);
  339. qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
  340. qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
  341. qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
  342. qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
  343. mutex_unlock(&priv->reg_mutex);
  344. }
  345. static int
  346. qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
  347. {
  348. u32 reg;
  349. switch (port) {
  350. case 0:
  351. reg = QCA8K_REG_PORT0_PAD_CTRL;
  352. break;
  353. case 6:
  354. reg = QCA8K_REG_PORT6_PAD_CTRL;
  355. break;
  356. default:
  357. pr_err("Can't set PAD_CTRL on port %d\n", port);
  358. return -EINVAL;
  359. }
  360. /* Configure a port to be directly connected to an external
  361. * PHY or MAC.
  362. */
  363. switch (mode) {
  364. case PHY_INTERFACE_MODE_RGMII:
  365. qca8k_write(priv, reg,
  366. QCA8K_PORT_PAD_RGMII_EN |
  367. QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
  368. QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
  369. /* According to the datasheet, RGMII delay is enabled through
  370. * PORT5_PAD_CTRL for all ports, rather than individual port
  371. * registers
  372. */
  373. qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
  374. QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  375. break;
  376. case PHY_INTERFACE_MODE_RGMII_ID:
  377. /* RGMII_ID needs internal delay. This is enabled through
  378. * PORT5_PAD_CTRL for all ports, rather than individual port
  379. * registers
  380. */
  381. qca8k_write(priv, reg,
  382. QCA8K_PORT_PAD_RGMII_EN |
  383. QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
  384. QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
  385. qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
  386. QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  387. break;
  388. case PHY_INTERFACE_MODE_SGMII:
  389. qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
  390. break;
  391. default:
  392. pr_err("xMII mode %d not supported\n", mode);
  393. return -EINVAL;
  394. }
  395. return 0;
  396. }
  397. static void
  398. qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
  399. {
  400. u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
  401. /* Port 0 and 6 have no internal PHY */
  402. if (port > 0 && port < 6)
  403. mask |= QCA8K_PORT_STATUS_LINK_AUTO;
  404. if (enable)
  405. qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
  406. else
  407. qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
  408. }
  409. static int
  410. qca8k_setup(struct dsa_switch *ds)
  411. {
  412. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  413. int ret, i, phy_mode = -1;
  414. u32 mask;
  415. /* Make sure that port 0 is the cpu port */
  416. if (!dsa_is_cpu_port(ds, 0)) {
  417. pr_err("port 0 is not the CPU port\n");
  418. return -EINVAL;
  419. }
  420. mutex_init(&priv->reg_mutex);
  421. /* Start by setting up the register mapping */
  422. priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
  423. &qca8k_regmap_config);
  424. if (IS_ERR(priv->regmap))
  425. pr_warn("regmap initialization failed");
  426. /* Initialize CPU port pad mode (xMII type, delays...) */
  427. phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
  428. if (phy_mode < 0) {
  429. pr_err("Can't find phy-mode for master device\n");
  430. return phy_mode;
  431. }
  432. ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
  433. if (ret < 0)
  434. return ret;
  435. /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
  436. mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
  437. QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
  438. qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
  439. qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
  440. QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
  441. qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
  442. priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
  443. /* Enable MIB counters */
  444. qca8k_mib_init(priv);
  445. /* Enable QCA header mode on the cpu port */
  446. qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
  447. QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
  448. QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
  449. /* Disable forwarding by default on all ports */
  450. for (i = 0; i < QCA8K_NUM_PORTS; i++)
  451. qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
  452. QCA8K_PORT_LOOKUP_MEMBER, 0);
  453. /* Disable MAC by default on all user ports */
  454. for (i = 1; i < QCA8K_NUM_PORTS; i++)
  455. if (dsa_is_user_port(ds, i))
  456. qca8k_port_set_status(priv, i, 0);
  457. /* Forward all unknown frames to CPU port for Linux processing */
  458. qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
  459. BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
  460. BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
  461. BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
  462. BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
  463. /* Setup connection between CPU port & user ports */
  464. for (i = 0; i < QCA8K_NUM_PORTS; i++) {
  465. /* CPU port gets connected to all user ports of the switch */
  466. if (dsa_is_cpu_port(ds, i)) {
  467. qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
  468. QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
  469. }
  470. /* Invividual user ports get connected to CPU port only */
  471. if (dsa_is_user_port(ds, i)) {
  472. int shift = 16 * (i % 2);
  473. qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
  474. QCA8K_PORT_LOOKUP_MEMBER,
  475. BIT(QCA8K_CPU_PORT));
  476. /* Enable ARP Auto-learning by default */
  477. qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
  478. QCA8K_PORT_LOOKUP_LEARN);
  479. /* For port based vlans to work we need to set the
  480. * default egress vid
  481. */
  482. qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
  483. 0xffff << shift, 1 << shift);
  484. qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
  485. QCA8K_PORT_VLAN_CVID(1) |
  486. QCA8K_PORT_VLAN_SVID(1));
  487. }
  488. }
  489. /* Flush the FDB table */
  490. qca8k_fdb_flush(priv);
  491. return 0;
  492. }
  493. static void
  494. qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
  495. {
  496. struct qca8k_priv *priv = ds->priv;
  497. u32 reg;
  498. /* Force fixed-link setting for CPU port, skip others. */
  499. if (!phy_is_pseudo_fixed_link(phy))
  500. return;
  501. /* Set port speed */
  502. switch (phy->speed) {
  503. case 10:
  504. reg = QCA8K_PORT_STATUS_SPEED_10;
  505. break;
  506. case 100:
  507. reg = QCA8K_PORT_STATUS_SPEED_100;
  508. break;
  509. case 1000:
  510. reg = QCA8K_PORT_STATUS_SPEED_1000;
  511. break;
  512. default:
  513. dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
  514. port, phy->speed);
  515. return;
  516. }
  517. /* Set duplex mode */
  518. if (phy->duplex == DUPLEX_FULL)
  519. reg |= QCA8K_PORT_STATUS_DUPLEX;
  520. /* Force flow control */
  521. if (dsa_is_cpu_port(ds, port))
  522. reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
  523. /* Force link down before changing MAC options */
  524. qca8k_port_set_status(priv, port, 0);
  525. qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
  526. qca8k_port_set_status(priv, port, 1);
  527. }
  528. static void
  529. qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
  530. {
  531. int i;
  532. if (stringset != ETH_SS_STATS)
  533. return;
  534. for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
  535. strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
  536. ETH_GSTRING_LEN);
  537. }
  538. static void
  539. qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
  540. uint64_t *data)
  541. {
  542. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  543. const struct qca8k_mib_desc *mib;
  544. u32 reg, i;
  545. u64 hi;
  546. for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
  547. mib = &ar8327_mib[i];
  548. reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
  549. data[i] = qca8k_read(priv, reg);
  550. if (mib->size == 2) {
  551. hi = qca8k_read(priv, reg + 4);
  552. data[i] |= hi << 32;
  553. }
  554. }
  555. }
  556. static int
  557. qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
  558. {
  559. if (sset != ETH_SS_STATS)
  560. return 0;
  561. return ARRAY_SIZE(ar8327_mib);
  562. }
  563. static int
  564. qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
  565. {
  566. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  567. u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
  568. u32 reg;
  569. mutex_lock(&priv->reg_mutex);
  570. reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
  571. if (eee->eee_enabled)
  572. reg |= lpi_en;
  573. else
  574. reg &= ~lpi_en;
  575. qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
  576. mutex_unlock(&priv->reg_mutex);
  577. return 0;
  578. }
  579. static int
  580. qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
  581. {
  582. /* Nothing to do on the port's MAC */
  583. return 0;
  584. }
  585. static void
  586. qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
  587. {
  588. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  589. u32 stp_state;
  590. switch (state) {
  591. case BR_STATE_DISABLED:
  592. stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
  593. break;
  594. case BR_STATE_BLOCKING:
  595. stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
  596. break;
  597. case BR_STATE_LISTENING:
  598. stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
  599. break;
  600. case BR_STATE_LEARNING:
  601. stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
  602. break;
  603. case BR_STATE_FORWARDING:
  604. default:
  605. stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
  606. break;
  607. }
  608. qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
  609. QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
  610. }
  611. static int
  612. qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
  613. {
  614. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  615. int port_mask = BIT(QCA8K_CPU_PORT);
  616. int i;
  617. for (i = 1; i < QCA8K_NUM_PORTS; i++) {
  618. if (dsa_to_port(ds, i)->bridge_dev != br)
  619. continue;
  620. /* Add this port to the portvlan mask of the other ports
  621. * in the bridge
  622. */
  623. qca8k_reg_set(priv,
  624. QCA8K_PORT_LOOKUP_CTRL(i),
  625. BIT(port));
  626. if (i != port)
  627. port_mask |= BIT(i);
  628. }
  629. /* Add all other ports to this ports portvlan mask */
  630. qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
  631. QCA8K_PORT_LOOKUP_MEMBER, port_mask);
  632. return 0;
  633. }
  634. static void
  635. qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
  636. {
  637. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  638. int i;
  639. for (i = 1; i < QCA8K_NUM_PORTS; i++) {
  640. if (dsa_to_port(ds, i)->bridge_dev != br)
  641. continue;
  642. /* Remove this port to the portvlan mask of the other ports
  643. * in the bridge
  644. */
  645. qca8k_reg_clear(priv,
  646. QCA8K_PORT_LOOKUP_CTRL(i),
  647. BIT(port));
  648. }
  649. /* Set the cpu port to be the only one in the portvlan mask of
  650. * this port
  651. */
  652. qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
  653. QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
  654. }
  655. static int
  656. qca8k_port_enable(struct dsa_switch *ds, int port,
  657. struct phy_device *phy)
  658. {
  659. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  660. qca8k_port_set_status(priv, port, 1);
  661. priv->port_sts[port].enabled = 1;
  662. return 0;
  663. }
  664. static void
  665. qca8k_port_disable(struct dsa_switch *ds, int port,
  666. struct phy_device *phy)
  667. {
  668. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  669. qca8k_port_set_status(priv, port, 0);
  670. priv->port_sts[port].enabled = 0;
  671. }
  672. static int
  673. qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
  674. u16 port_mask, u16 vid)
  675. {
  676. /* Set the vid to the port vlan id if no vid is set */
  677. if (!vid)
  678. vid = 1;
  679. return qca8k_fdb_add(priv, addr, port_mask, vid,
  680. QCA8K_ATU_STATUS_STATIC);
  681. }
  682. static int
  683. qca8k_port_fdb_add(struct dsa_switch *ds, int port,
  684. const unsigned char *addr, u16 vid)
  685. {
  686. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  687. u16 port_mask = BIT(port);
  688. return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
  689. }
  690. static int
  691. qca8k_port_fdb_del(struct dsa_switch *ds, int port,
  692. const unsigned char *addr, u16 vid)
  693. {
  694. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  695. u16 port_mask = BIT(port);
  696. if (!vid)
  697. vid = 1;
  698. return qca8k_fdb_del(priv, addr, port_mask, vid);
  699. }
  700. static int
  701. qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
  702. dsa_fdb_dump_cb_t *cb, void *data)
  703. {
  704. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  705. struct qca8k_fdb _fdb = { 0 };
  706. int cnt = QCA8K_NUM_FDB_RECORDS;
  707. bool is_static;
  708. int ret = 0;
  709. mutex_lock(&priv->reg_mutex);
  710. while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
  711. if (!_fdb.aging)
  712. break;
  713. is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
  714. ret = cb(_fdb.mac, _fdb.vid, is_static, data);
  715. if (ret)
  716. break;
  717. }
  718. mutex_unlock(&priv->reg_mutex);
  719. return 0;
  720. }
  721. static enum dsa_tag_protocol
  722. qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
  723. {
  724. return DSA_TAG_PROTO_QCA;
  725. }
  726. static const struct dsa_switch_ops qca8k_switch_ops = {
  727. .get_tag_protocol = qca8k_get_tag_protocol,
  728. .setup = qca8k_setup,
  729. .adjust_link = qca8k_adjust_link,
  730. .get_strings = qca8k_get_strings,
  731. .get_ethtool_stats = qca8k_get_ethtool_stats,
  732. .get_sset_count = qca8k_get_sset_count,
  733. .get_mac_eee = qca8k_get_mac_eee,
  734. .set_mac_eee = qca8k_set_mac_eee,
  735. .port_enable = qca8k_port_enable,
  736. .port_disable = qca8k_port_disable,
  737. .port_stp_state_set = qca8k_port_stp_state_set,
  738. .port_bridge_join = qca8k_port_bridge_join,
  739. .port_bridge_leave = qca8k_port_bridge_leave,
  740. .port_fdb_add = qca8k_port_fdb_add,
  741. .port_fdb_del = qca8k_port_fdb_del,
  742. .port_fdb_dump = qca8k_port_fdb_dump,
  743. };
  744. static int
  745. qca8k_sw_probe(struct mdio_device *mdiodev)
  746. {
  747. struct qca8k_priv *priv;
  748. u32 id;
  749. /* allocate the private data struct so that we can probe the switches
  750. * ID register
  751. */
  752. priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
  753. if (!priv)
  754. return -ENOMEM;
  755. priv->bus = mdiodev->bus;
  756. priv->dev = &mdiodev->dev;
  757. /* read the switches ID register */
  758. id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
  759. id >>= QCA8K_MASK_CTRL_ID_S;
  760. id &= QCA8K_MASK_CTRL_ID_M;
  761. if (id != QCA8K_ID_QCA8337)
  762. return -ENODEV;
  763. priv->ds = dsa_switch_alloc(&mdiodev->dev, QCA8K_NUM_PORTS);
  764. if (!priv->ds)
  765. return -ENOMEM;
  766. priv->ds->priv = priv;
  767. priv->ds->ops = &qca8k_switch_ops;
  768. mutex_init(&priv->reg_mutex);
  769. dev_set_drvdata(&mdiodev->dev, priv);
  770. return dsa_register_switch(priv->ds);
  771. }
  772. static void
  773. qca8k_sw_remove(struct mdio_device *mdiodev)
  774. {
  775. struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
  776. int i;
  777. for (i = 0; i < QCA8K_NUM_PORTS; i++)
  778. qca8k_port_set_status(priv, i, 0);
  779. dsa_unregister_switch(priv->ds);
  780. }
  781. #ifdef CONFIG_PM_SLEEP
  782. static void
  783. qca8k_set_pm(struct qca8k_priv *priv, int enable)
  784. {
  785. int i;
  786. for (i = 0; i < QCA8K_NUM_PORTS; i++) {
  787. if (!priv->port_sts[i].enabled)
  788. continue;
  789. qca8k_port_set_status(priv, i, enable);
  790. }
  791. }
  792. static int qca8k_suspend(struct device *dev)
  793. {
  794. struct platform_device *pdev = to_platform_device(dev);
  795. struct qca8k_priv *priv = platform_get_drvdata(pdev);
  796. qca8k_set_pm(priv, 0);
  797. return dsa_switch_suspend(priv->ds);
  798. }
  799. static int qca8k_resume(struct device *dev)
  800. {
  801. struct platform_device *pdev = to_platform_device(dev);
  802. struct qca8k_priv *priv = platform_get_drvdata(pdev);
  803. qca8k_set_pm(priv, 1);
  804. return dsa_switch_resume(priv->ds);
  805. }
  806. #endif /* CONFIG_PM_SLEEP */
  807. static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
  808. qca8k_suspend, qca8k_resume);
  809. static const struct of_device_id qca8k_of_match[] = {
  810. { .compatible = "qca,qca8334" },
  811. { .compatible = "qca,qca8337" },
  812. { /* sentinel */ },
  813. };
  814. static struct mdio_driver qca8kmdio_driver = {
  815. .probe = qca8k_sw_probe,
  816. .remove = qca8k_sw_remove,
  817. .mdiodrv.driver = {
  818. .name = "qca8k",
  819. .of_match_table = qca8k_of_match,
  820. .pm = &qca8k_pm_ops,
  821. },
  822. };
  823. mdio_module_driver(qca8kmdio_driver);
  824. MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
  825. MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
  826. MODULE_LICENSE("GPL v2");
  827. MODULE_ALIAS("platform:qca8k");