smsc75xx.c 57 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include <linux/of_net.h>
  32. #include "smsc75xx.h"
  33. #define SMSC_CHIPNAME "smsc75xx"
  34. #define SMSC_DRIVER_VERSION "1.0.0"
  35. #define HS_USB_PKT_SIZE (512)
  36. #define FS_USB_PKT_SIZE (64)
  37. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  38. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  39. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  40. #define MAX_SINGLE_PACKET_SIZE (9000)
  41. #define LAN75XX_EEPROM_MAGIC (0x7500)
  42. #define EEPROM_MAC_OFFSET (0x01)
  43. #define DEFAULT_TX_CSUM_ENABLE (true)
  44. #define DEFAULT_RX_CSUM_ENABLE (true)
  45. #define SMSC75XX_INTERNAL_PHY_ID (1)
  46. #define SMSC75XX_TX_OVERHEAD (8)
  47. #define MAX_RX_FIFO_SIZE (20 * 1024)
  48. #define MAX_TX_FIFO_SIZE (12 * 1024)
  49. #define USB_VENDOR_ID_SMSC (0x0424)
  50. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  51. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  52. #define RXW_PADDING 2
  53. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  54. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  55. #define SUSPEND_SUSPEND0 (0x01)
  56. #define SUSPEND_SUSPEND1 (0x02)
  57. #define SUSPEND_SUSPEND2 (0x04)
  58. #define SUSPEND_SUSPEND3 (0x08)
  59. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  60. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  61. struct smsc75xx_priv {
  62. struct usbnet *dev;
  63. u32 rfe_ctl;
  64. u32 wolopts;
  65. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  66. struct mutex dataport_mutex;
  67. spinlock_t rfe_ctl_lock;
  68. struct work_struct set_multicast;
  69. u8 suspend_flags;
  70. };
  71. struct usb_context {
  72. struct usb_ctrlrequest req;
  73. struct usbnet *dev;
  74. };
  75. static bool turbo_mode = true;
  76. module_param(turbo_mode, bool, 0644);
  77. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  78. static int smsc75xx_link_ok_nopm(struct usbnet *dev);
  79. static int smsc75xx_phy_gig_workaround(struct usbnet *dev);
  80. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  81. u32 *data, int in_pm)
  82. {
  83. u32 buf;
  84. int ret;
  85. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  86. BUG_ON(!dev);
  87. if (!in_pm)
  88. fn = usbnet_read_cmd;
  89. else
  90. fn = usbnet_read_cmd_nopm;
  91. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  92. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  93. 0, index, &buf, 4);
  94. if (unlikely(ret < 0)) {
  95. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  96. index, ret);
  97. return ret;
  98. }
  99. le32_to_cpus(&buf);
  100. *data = buf;
  101. return ret;
  102. }
  103. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  104. u32 data, int in_pm)
  105. {
  106. u32 buf;
  107. int ret;
  108. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  109. BUG_ON(!dev);
  110. if (!in_pm)
  111. fn = usbnet_write_cmd;
  112. else
  113. fn = usbnet_write_cmd_nopm;
  114. buf = data;
  115. cpu_to_le32s(&buf);
  116. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  117. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  118. 0, index, &buf, 4);
  119. if (unlikely(ret < 0))
  120. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  121. index, ret);
  122. return ret;
  123. }
  124. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  125. u32 *data)
  126. {
  127. return __smsc75xx_read_reg(dev, index, data, 1);
  128. }
  129. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  130. u32 data)
  131. {
  132. return __smsc75xx_write_reg(dev, index, data, 1);
  133. }
  134. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  135. u32 *data)
  136. {
  137. return __smsc75xx_read_reg(dev, index, data, 0);
  138. }
  139. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  140. u32 data)
  141. {
  142. return __smsc75xx_write_reg(dev, index, data, 0);
  143. }
  144. /* Loop until the read is completed with timeout
  145. * called with phy_mutex held */
  146. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  147. int in_pm)
  148. {
  149. unsigned long start_time = jiffies;
  150. u32 val;
  151. int ret;
  152. do {
  153. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  154. if (ret < 0) {
  155. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  156. return ret;
  157. }
  158. if (!(val & MII_ACCESS_BUSY))
  159. return 0;
  160. } while (!time_after(jiffies, start_time + HZ));
  161. return -EIO;
  162. }
  163. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  164. int in_pm)
  165. {
  166. struct usbnet *dev = netdev_priv(netdev);
  167. u32 val, addr;
  168. int ret;
  169. mutex_lock(&dev->phy_mutex);
  170. /* confirm MII not busy */
  171. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  172. if (ret < 0) {
  173. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  174. goto done;
  175. }
  176. /* set the address, index & direction (read from PHY) */
  177. phy_id &= dev->mii.phy_id_mask;
  178. idx &= dev->mii.reg_num_mask;
  179. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  180. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  181. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  182. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  183. if (ret < 0) {
  184. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  185. goto done;
  186. }
  187. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  188. if (ret < 0) {
  189. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  190. goto done;
  191. }
  192. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  193. if (ret < 0) {
  194. netdev_warn(dev->net, "Error reading MII_DATA\n");
  195. goto done;
  196. }
  197. ret = (u16)(val & 0xFFFF);
  198. done:
  199. mutex_unlock(&dev->phy_mutex);
  200. return ret;
  201. }
  202. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  203. int idx, int regval, int in_pm)
  204. {
  205. struct usbnet *dev = netdev_priv(netdev);
  206. u32 val, addr;
  207. int ret;
  208. mutex_lock(&dev->phy_mutex);
  209. /* confirm MII not busy */
  210. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  211. if (ret < 0) {
  212. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  213. goto done;
  214. }
  215. val = regval;
  216. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  217. if (ret < 0) {
  218. netdev_warn(dev->net, "Error writing MII_DATA\n");
  219. goto done;
  220. }
  221. /* set the address, index & direction (write to PHY) */
  222. phy_id &= dev->mii.phy_id_mask;
  223. idx &= dev->mii.reg_num_mask;
  224. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  225. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  226. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  227. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  228. if (ret < 0) {
  229. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  230. goto done;
  231. }
  232. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  233. if (ret < 0) {
  234. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  235. goto done;
  236. }
  237. done:
  238. mutex_unlock(&dev->phy_mutex);
  239. }
  240. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  241. int idx)
  242. {
  243. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  244. }
  245. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  246. int idx, int regval)
  247. {
  248. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  249. }
  250. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  251. {
  252. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  253. }
  254. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  255. int regval)
  256. {
  257. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  258. }
  259. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  260. {
  261. unsigned long start_time = jiffies;
  262. u32 val;
  263. int ret;
  264. do {
  265. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  266. if (ret < 0) {
  267. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  268. return ret;
  269. }
  270. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  271. break;
  272. udelay(40);
  273. } while (!time_after(jiffies, start_time + HZ));
  274. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  275. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  276. return -EIO;
  277. }
  278. return 0;
  279. }
  280. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  281. {
  282. unsigned long start_time = jiffies;
  283. u32 val;
  284. int ret;
  285. do {
  286. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  287. if (ret < 0) {
  288. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  289. return ret;
  290. }
  291. if (!(val & E2P_CMD_BUSY))
  292. return 0;
  293. udelay(40);
  294. } while (!time_after(jiffies, start_time + HZ));
  295. netdev_warn(dev->net, "EEPROM is busy\n");
  296. return -EIO;
  297. }
  298. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  299. u8 *data)
  300. {
  301. u32 val;
  302. int i, ret;
  303. BUG_ON(!dev);
  304. BUG_ON(!data);
  305. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  306. if (ret)
  307. return ret;
  308. for (i = 0; i < length; i++) {
  309. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  310. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  311. if (ret < 0) {
  312. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  313. return ret;
  314. }
  315. ret = smsc75xx_wait_eeprom(dev);
  316. if (ret < 0)
  317. return ret;
  318. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  319. if (ret < 0) {
  320. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  321. return ret;
  322. }
  323. data[i] = val & 0xFF;
  324. offset++;
  325. }
  326. return 0;
  327. }
  328. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  329. u8 *data)
  330. {
  331. u32 val;
  332. int i, ret;
  333. BUG_ON(!dev);
  334. BUG_ON(!data);
  335. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  336. if (ret)
  337. return ret;
  338. /* Issue write/erase enable command */
  339. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  340. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  341. if (ret < 0) {
  342. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  343. return ret;
  344. }
  345. ret = smsc75xx_wait_eeprom(dev);
  346. if (ret < 0)
  347. return ret;
  348. for (i = 0; i < length; i++) {
  349. /* Fill data register */
  350. val = data[i];
  351. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  352. if (ret < 0) {
  353. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  354. return ret;
  355. }
  356. /* Send "write" command */
  357. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  358. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  359. if (ret < 0) {
  360. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  361. return ret;
  362. }
  363. ret = smsc75xx_wait_eeprom(dev);
  364. if (ret < 0)
  365. return ret;
  366. offset++;
  367. }
  368. return 0;
  369. }
  370. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  371. {
  372. int i, ret;
  373. for (i = 0; i < 100; i++) {
  374. u32 dp_sel;
  375. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  376. if (ret < 0) {
  377. netdev_warn(dev->net, "Error reading DP_SEL\n");
  378. return ret;
  379. }
  380. if (dp_sel & DP_SEL_DPRDY)
  381. return 0;
  382. udelay(40);
  383. }
  384. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  385. return -EIO;
  386. }
  387. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  388. u32 length, u32 *buf)
  389. {
  390. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  391. u32 dp_sel;
  392. int i, ret;
  393. mutex_lock(&pdata->dataport_mutex);
  394. ret = smsc75xx_dataport_wait_not_busy(dev);
  395. if (ret < 0) {
  396. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  397. goto done;
  398. }
  399. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  400. if (ret < 0) {
  401. netdev_warn(dev->net, "Error reading DP_SEL\n");
  402. goto done;
  403. }
  404. dp_sel &= ~DP_SEL_RSEL;
  405. dp_sel |= ram_select;
  406. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  407. if (ret < 0) {
  408. netdev_warn(dev->net, "Error writing DP_SEL\n");
  409. goto done;
  410. }
  411. for (i = 0; i < length; i++) {
  412. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  413. if (ret < 0) {
  414. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  415. goto done;
  416. }
  417. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  418. if (ret < 0) {
  419. netdev_warn(dev->net, "Error writing DP_DATA\n");
  420. goto done;
  421. }
  422. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  423. if (ret < 0) {
  424. netdev_warn(dev->net, "Error writing DP_CMD\n");
  425. goto done;
  426. }
  427. ret = smsc75xx_dataport_wait_not_busy(dev);
  428. if (ret < 0) {
  429. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  430. goto done;
  431. }
  432. }
  433. done:
  434. mutex_unlock(&pdata->dataport_mutex);
  435. return ret;
  436. }
  437. /* returns hash bit number for given MAC address */
  438. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  439. {
  440. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  441. }
  442. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  443. {
  444. struct smsc75xx_priv *pdata =
  445. container_of(param, struct smsc75xx_priv, set_multicast);
  446. struct usbnet *dev = pdata->dev;
  447. int ret;
  448. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  449. pdata->rfe_ctl);
  450. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  451. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  452. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  453. if (ret < 0)
  454. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  455. }
  456. static void smsc75xx_set_multicast(struct net_device *netdev)
  457. {
  458. struct usbnet *dev = netdev_priv(netdev);
  459. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  460. unsigned long flags;
  461. int i;
  462. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  463. pdata->rfe_ctl &=
  464. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  465. pdata->rfe_ctl |= RFE_CTL_AB;
  466. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  467. pdata->multicast_hash_table[i] = 0;
  468. if (dev->net->flags & IFF_PROMISC) {
  469. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  470. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  471. } else if (dev->net->flags & IFF_ALLMULTI) {
  472. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  473. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  474. } else if (!netdev_mc_empty(dev->net)) {
  475. struct netdev_hw_addr *ha;
  476. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  477. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  478. netdev_for_each_mc_addr(ha, netdev) {
  479. u32 bitnum = smsc75xx_hash(ha->addr);
  480. pdata->multicast_hash_table[bitnum / 32] |=
  481. (1 << (bitnum % 32));
  482. }
  483. } else {
  484. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  485. pdata->rfe_ctl |= RFE_CTL_DPF;
  486. }
  487. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  488. /* defer register writes to a sleepable context */
  489. schedule_work(&pdata->set_multicast);
  490. }
  491. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  492. u16 lcladv, u16 rmtadv)
  493. {
  494. u32 flow = 0, fct_flow = 0;
  495. int ret;
  496. if (duplex == DUPLEX_FULL) {
  497. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  498. if (cap & FLOW_CTRL_TX) {
  499. flow = (FLOW_TX_FCEN | 0xFFFF);
  500. /* set fct_flow thresholds to 20% and 80% */
  501. fct_flow = (8 << 8) | 32;
  502. }
  503. if (cap & FLOW_CTRL_RX)
  504. flow |= FLOW_RX_FCEN;
  505. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  506. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  507. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  508. } else {
  509. netif_dbg(dev, link, dev->net, "half duplex\n");
  510. }
  511. ret = smsc75xx_write_reg(dev, FLOW, flow);
  512. if (ret < 0) {
  513. netdev_warn(dev->net, "Error writing FLOW\n");
  514. return ret;
  515. }
  516. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  517. if (ret < 0) {
  518. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  519. return ret;
  520. }
  521. return 0;
  522. }
  523. static int smsc75xx_link_reset(struct usbnet *dev)
  524. {
  525. struct mii_if_info *mii = &dev->mii;
  526. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  527. u16 lcladv, rmtadv;
  528. int ret;
  529. /* write to clear phy interrupt status */
  530. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  531. PHY_INT_SRC_CLEAR_ALL);
  532. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  533. if (ret < 0) {
  534. netdev_warn(dev->net, "Error writing INT_STS\n");
  535. return ret;
  536. }
  537. mii_check_media(mii, 1, 1);
  538. mii_ethtool_gset(&dev->mii, &ecmd);
  539. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  540. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  541. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  542. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  543. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  544. }
  545. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  546. {
  547. u32 intdata;
  548. if (urb->actual_length != 4) {
  549. netdev_warn(dev->net, "unexpected urb length %d\n",
  550. urb->actual_length);
  551. return;
  552. }
  553. memcpy(&intdata, urb->transfer_buffer, 4);
  554. le32_to_cpus(&intdata);
  555. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  556. if (intdata & INT_ENP_PHY_INT)
  557. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  558. else
  559. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  560. intdata);
  561. }
  562. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  563. {
  564. return MAX_EEPROM_SIZE;
  565. }
  566. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  567. struct ethtool_eeprom *ee, u8 *data)
  568. {
  569. struct usbnet *dev = netdev_priv(netdev);
  570. ee->magic = LAN75XX_EEPROM_MAGIC;
  571. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  572. }
  573. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  574. struct ethtool_eeprom *ee, u8 *data)
  575. {
  576. struct usbnet *dev = netdev_priv(netdev);
  577. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  578. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  579. ee->magic);
  580. return -EINVAL;
  581. }
  582. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  583. }
  584. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  585. struct ethtool_wolinfo *wolinfo)
  586. {
  587. struct usbnet *dev = netdev_priv(net);
  588. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  589. wolinfo->supported = SUPPORTED_WAKE;
  590. wolinfo->wolopts = pdata->wolopts;
  591. }
  592. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  593. struct ethtool_wolinfo *wolinfo)
  594. {
  595. struct usbnet *dev = netdev_priv(net);
  596. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  597. int ret;
  598. if (wolinfo->wolopts & ~SUPPORTED_WAKE)
  599. return -EINVAL;
  600. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  601. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  602. if (ret < 0)
  603. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  604. return ret;
  605. }
  606. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  607. .get_link = usbnet_get_link,
  608. .nway_reset = usbnet_nway_reset,
  609. .get_drvinfo = usbnet_get_drvinfo,
  610. .get_msglevel = usbnet_get_msglevel,
  611. .set_msglevel = usbnet_set_msglevel,
  612. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  613. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  614. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  615. .get_wol = smsc75xx_ethtool_get_wol,
  616. .set_wol = smsc75xx_ethtool_set_wol,
  617. .get_link_ksettings = usbnet_get_link_ksettings,
  618. .set_link_ksettings = usbnet_set_link_ksettings,
  619. };
  620. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  621. {
  622. struct usbnet *dev = netdev_priv(netdev);
  623. if (!netif_running(netdev))
  624. return -EINVAL;
  625. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  626. }
  627. static void smsc75xx_init_mac_address(struct usbnet *dev)
  628. {
  629. const u8 *mac_addr;
  630. /* maybe the boot loader passed the MAC address in devicetree */
  631. mac_addr = of_get_mac_address(dev->udev->dev.of_node);
  632. if (mac_addr) {
  633. memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
  634. return;
  635. }
  636. /* try reading mac address from EEPROM */
  637. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  638. dev->net->dev_addr) == 0) {
  639. if (is_valid_ether_addr(dev->net->dev_addr)) {
  640. /* eeprom values are valid so use them */
  641. netif_dbg(dev, ifup, dev->net,
  642. "MAC address read from EEPROM\n");
  643. return;
  644. }
  645. }
  646. /* no useful static MAC address found. generate a random one */
  647. eth_hw_addr_random(dev->net);
  648. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  649. }
  650. static int smsc75xx_set_mac_address(struct usbnet *dev)
  651. {
  652. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  653. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  654. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  655. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  656. if (ret < 0) {
  657. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  658. return ret;
  659. }
  660. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  661. if (ret < 0) {
  662. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  663. return ret;
  664. }
  665. addr_hi |= ADDR_FILTX_FB_VALID;
  666. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  667. if (ret < 0) {
  668. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  669. return ret;
  670. }
  671. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  672. if (ret < 0)
  673. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  674. return ret;
  675. }
  676. static int smsc75xx_phy_initialize(struct usbnet *dev)
  677. {
  678. int bmcr, ret, timeout = 0;
  679. /* Initialize MII structure */
  680. dev->mii.dev = dev->net;
  681. dev->mii.mdio_read = smsc75xx_mdio_read;
  682. dev->mii.mdio_write = smsc75xx_mdio_write;
  683. dev->mii.phy_id_mask = 0x1f;
  684. dev->mii.reg_num_mask = 0x1f;
  685. dev->mii.supports_gmii = 1;
  686. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  687. /* reset phy and wait for reset to complete */
  688. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  689. do {
  690. msleep(10);
  691. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  692. if (bmcr < 0) {
  693. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  694. return bmcr;
  695. }
  696. timeout++;
  697. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  698. if (timeout >= 100) {
  699. netdev_warn(dev->net, "timeout on PHY Reset\n");
  700. return -EIO;
  701. }
  702. /* phy workaround for gig link */
  703. smsc75xx_phy_gig_workaround(dev);
  704. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  705. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  706. ADVERTISE_PAUSE_ASYM);
  707. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  708. ADVERTISE_1000FULL);
  709. /* read and write to clear phy interrupt status */
  710. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  711. if (ret < 0) {
  712. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  713. return ret;
  714. }
  715. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  716. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  717. PHY_INT_MASK_DEFAULT);
  718. mii_nway_restart(&dev->mii);
  719. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  720. return 0;
  721. }
  722. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  723. {
  724. int ret = 0;
  725. u32 buf;
  726. bool rxenabled;
  727. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  728. if (ret < 0) {
  729. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  730. return ret;
  731. }
  732. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  733. if (rxenabled) {
  734. buf &= ~MAC_RX_RXEN;
  735. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  736. if (ret < 0) {
  737. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  738. return ret;
  739. }
  740. }
  741. /* add 4 to size for FCS */
  742. buf &= ~MAC_RX_MAX_SIZE;
  743. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  744. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  745. if (ret < 0) {
  746. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  747. return ret;
  748. }
  749. if (rxenabled) {
  750. buf |= MAC_RX_RXEN;
  751. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  752. if (ret < 0) {
  753. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  754. return ret;
  755. }
  756. }
  757. return 0;
  758. }
  759. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  760. {
  761. struct usbnet *dev = netdev_priv(netdev);
  762. int ret;
  763. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  764. if (ret < 0) {
  765. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  766. return ret;
  767. }
  768. return usbnet_change_mtu(netdev, new_mtu);
  769. }
  770. /* Enable or disable Rx checksum offload engine */
  771. static int smsc75xx_set_features(struct net_device *netdev,
  772. netdev_features_t features)
  773. {
  774. struct usbnet *dev = netdev_priv(netdev);
  775. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  776. unsigned long flags;
  777. int ret;
  778. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  779. if (features & NETIF_F_RXCSUM)
  780. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  781. else
  782. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  783. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  784. /* it's racing here! */
  785. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  786. if (ret < 0) {
  787. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  788. return ret;
  789. }
  790. return 0;
  791. }
  792. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  793. {
  794. int timeout = 0;
  795. do {
  796. u32 buf;
  797. int ret;
  798. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  799. if (ret < 0) {
  800. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  801. return ret;
  802. }
  803. if (buf & PMT_CTL_DEV_RDY)
  804. return 0;
  805. msleep(10);
  806. timeout++;
  807. } while (timeout < 100);
  808. netdev_warn(dev->net, "timeout waiting for device ready\n");
  809. return -EIO;
  810. }
  811. static int smsc75xx_phy_gig_workaround(struct usbnet *dev)
  812. {
  813. struct mii_if_info *mii = &dev->mii;
  814. int ret = 0, timeout = 0;
  815. u32 buf, link_up = 0;
  816. /* Set the phy in Gig loopback */
  817. smsc75xx_mdio_write(dev->net, mii->phy_id, MII_BMCR, 0x4040);
  818. /* Wait for the link up */
  819. do {
  820. link_up = smsc75xx_link_ok_nopm(dev);
  821. usleep_range(10000, 20000);
  822. timeout++;
  823. } while ((!link_up) && (timeout < 1000));
  824. if (timeout >= 1000) {
  825. netdev_warn(dev->net, "Timeout waiting for PHY link up\n");
  826. return -EIO;
  827. }
  828. /* phy reset */
  829. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  830. if (ret < 0) {
  831. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  832. return ret;
  833. }
  834. buf |= PMT_CTL_PHY_RST;
  835. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  836. if (ret < 0) {
  837. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  838. return ret;
  839. }
  840. timeout = 0;
  841. do {
  842. usleep_range(10000, 20000);
  843. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  844. if (ret < 0) {
  845. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n",
  846. ret);
  847. return ret;
  848. }
  849. timeout++;
  850. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  851. if (timeout >= 100) {
  852. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  853. return -EIO;
  854. }
  855. return 0;
  856. }
  857. static int smsc75xx_reset(struct usbnet *dev)
  858. {
  859. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  860. u32 buf;
  861. int ret = 0, timeout;
  862. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  863. ret = smsc75xx_wait_ready(dev, 0);
  864. if (ret < 0) {
  865. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  866. return ret;
  867. }
  868. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  869. if (ret < 0) {
  870. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  871. return ret;
  872. }
  873. buf |= HW_CFG_LRST;
  874. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  875. if (ret < 0) {
  876. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  877. return ret;
  878. }
  879. timeout = 0;
  880. do {
  881. msleep(10);
  882. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  883. if (ret < 0) {
  884. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  885. return ret;
  886. }
  887. timeout++;
  888. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  889. if (timeout >= 100) {
  890. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  891. return -EIO;
  892. }
  893. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  894. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  895. if (ret < 0) {
  896. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  897. return ret;
  898. }
  899. buf |= PMT_CTL_PHY_RST;
  900. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  901. if (ret < 0) {
  902. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  903. return ret;
  904. }
  905. timeout = 0;
  906. do {
  907. msleep(10);
  908. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  909. if (ret < 0) {
  910. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  911. return ret;
  912. }
  913. timeout++;
  914. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  915. if (timeout >= 100) {
  916. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  917. return -EIO;
  918. }
  919. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  920. ret = smsc75xx_set_mac_address(dev);
  921. if (ret < 0) {
  922. netdev_warn(dev->net, "Failed to set mac address\n");
  923. return ret;
  924. }
  925. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  926. dev->net->dev_addr);
  927. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  928. if (ret < 0) {
  929. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  930. return ret;
  931. }
  932. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  933. buf);
  934. buf |= HW_CFG_BIR;
  935. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  936. if (ret < 0) {
  937. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  938. return ret;
  939. }
  940. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  941. if (ret < 0) {
  942. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  943. return ret;
  944. }
  945. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  946. buf);
  947. if (!turbo_mode) {
  948. buf = 0;
  949. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  950. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  951. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  952. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  953. } else {
  954. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  955. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  956. }
  957. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  958. (ulong)dev->rx_urb_size);
  959. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  960. if (ret < 0) {
  961. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  962. return ret;
  963. }
  964. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  965. if (ret < 0) {
  966. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  967. return ret;
  968. }
  969. netif_dbg(dev, ifup, dev->net,
  970. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  971. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  972. if (ret < 0) {
  973. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  974. return ret;
  975. }
  976. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  977. if (ret < 0) {
  978. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  979. return ret;
  980. }
  981. netif_dbg(dev, ifup, dev->net,
  982. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  983. if (turbo_mode) {
  984. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  985. if (ret < 0) {
  986. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  987. return ret;
  988. }
  989. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  990. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  991. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  992. if (ret < 0) {
  993. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  994. return ret;
  995. }
  996. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  997. if (ret < 0) {
  998. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  999. return ret;
  1000. }
  1001. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  1002. }
  1003. /* set FIFO sizes */
  1004. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  1005. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  1006. if (ret < 0) {
  1007. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  1008. return ret;
  1009. }
  1010. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  1011. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  1012. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  1013. if (ret < 0) {
  1014. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  1015. return ret;
  1016. }
  1017. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  1018. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  1019. if (ret < 0) {
  1020. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  1021. return ret;
  1022. }
  1023. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  1024. if (ret < 0) {
  1025. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  1026. return ret;
  1027. }
  1028. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  1029. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  1030. if (ret < 0) {
  1031. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  1032. return ret;
  1033. }
  1034. /* only set default GPIO/LED settings if no EEPROM is detected */
  1035. if (!(buf & E2P_CMD_LOADED)) {
  1036. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  1037. if (ret < 0) {
  1038. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  1039. return ret;
  1040. }
  1041. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  1042. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  1043. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  1044. if (ret < 0) {
  1045. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  1046. return ret;
  1047. }
  1048. }
  1049. ret = smsc75xx_write_reg(dev, FLOW, 0);
  1050. if (ret < 0) {
  1051. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  1052. return ret;
  1053. }
  1054. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  1055. if (ret < 0) {
  1056. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  1057. return ret;
  1058. }
  1059. /* Don't need rfe_ctl_lock during initialisation */
  1060. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1061. if (ret < 0) {
  1062. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1063. return ret;
  1064. }
  1065. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1066. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1067. if (ret < 0) {
  1068. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1069. return ret;
  1070. }
  1071. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1072. if (ret < 0) {
  1073. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1074. return ret;
  1075. }
  1076. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1077. pdata->rfe_ctl);
  1078. /* Enable or disable checksum offload engines */
  1079. smsc75xx_set_features(dev->net, dev->net->features);
  1080. smsc75xx_set_multicast(dev->net);
  1081. ret = smsc75xx_phy_initialize(dev);
  1082. if (ret < 0) {
  1083. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1084. return ret;
  1085. }
  1086. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1087. if (ret < 0) {
  1088. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1089. return ret;
  1090. }
  1091. /* enable PHY interrupts */
  1092. buf |= INT_ENP_PHY_INT;
  1093. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1094. if (ret < 0) {
  1095. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1096. return ret;
  1097. }
  1098. /* allow mac to detect speed and duplex from phy */
  1099. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1100. if (ret < 0) {
  1101. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1102. return ret;
  1103. }
  1104. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1105. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1106. if (ret < 0) {
  1107. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1108. return ret;
  1109. }
  1110. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1111. if (ret < 0) {
  1112. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1113. return ret;
  1114. }
  1115. buf |= MAC_TX_TXEN;
  1116. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1117. if (ret < 0) {
  1118. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1119. return ret;
  1120. }
  1121. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1122. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1123. if (ret < 0) {
  1124. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1125. return ret;
  1126. }
  1127. buf |= FCT_TX_CTL_EN;
  1128. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1129. if (ret < 0) {
  1130. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1131. return ret;
  1132. }
  1133. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1134. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1135. if (ret < 0) {
  1136. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1137. return ret;
  1138. }
  1139. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1140. if (ret < 0) {
  1141. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1142. return ret;
  1143. }
  1144. buf |= MAC_RX_RXEN;
  1145. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1146. if (ret < 0) {
  1147. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1148. return ret;
  1149. }
  1150. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1151. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1152. if (ret < 0) {
  1153. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1154. return ret;
  1155. }
  1156. buf |= FCT_RX_CTL_EN;
  1157. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1158. if (ret < 0) {
  1159. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1160. return ret;
  1161. }
  1162. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1163. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1164. return 0;
  1165. }
  1166. static const struct net_device_ops smsc75xx_netdev_ops = {
  1167. .ndo_open = usbnet_open,
  1168. .ndo_stop = usbnet_stop,
  1169. .ndo_start_xmit = usbnet_start_xmit,
  1170. .ndo_tx_timeout = usbnet_tx_timeout,
  1171. .ndo_get_stats64 = usbnet_get_stats64,
  1172. .ndo_change_mtu = smsc75xx_change_mtu,
  1173. .ndo_set_mac_address = eth_mac_addr,
  1174. .ndo_validate_addr = eth_validate_addr,
  1175. .ndo_do_ioctl = smsc75xx_ioctl,
  1176. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1177. .ndo_set_features = smsc75xx_set_features,
  1178. };
  1179. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1180. {
  1181. struct smsc75xx_priv *pdata = NULL;
  1182. int ret;
  1183. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1184. ret = usbnet_get_endpoints(dev, intf);
  1185. if (ret < 0) {
  1186. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1187. return ret;
  1188. }
  1189. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1190. GFP_KERNEL);
  1191. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1192. if (!pdata)
  1193. return -ENOMEM;
  1194. pdata->dev = dev;
  1195. spin_lock_init(&pdata->rfe_ctl_lock);
  1196. mutex_init(&pdata->dataport_mutex);
  1197. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1198. if (DEFAULT_TX_CSUM_ENABLE)
  1199. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1200. if (DEFAULT_RX_CSUM_ENABLE)
  1201. dev->net->features |= NETIF_F_RXCSUM;
  1202. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1203. NETIF_F_RXCSUM;
  1204. ret = smsc75xx_wait_ready(dev, 0);
  1205. if (ret < 0) {
  1206. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1207. return ret;
  1208. }
  1209. smsc75xx_init_mac_address(dev);
  1210. /* Init all registers */
  1211. ret = smsc75xx_reset(dev);
  1212. if (ret < 0) {
  1213. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1214. return ret;
  1215. }
  1216. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1217. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1218. dev->net->flags |= IFF_MULTICAST;
  1219. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1220. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1221. dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
  1222. return 0;
  1223. }
  1224. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1225. {
  1226. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1227. if (pdata) {
  1228. cancel_work_sync(&pdata->set_multicast);
  1229. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1230. kfree(pdata);
  1231. pdata = NULL;
  1232. dev->data[0] = 0;
  1233. }
  1234. }
  1235. static u16 smsc_crc(const u8 *buffer, size_t len)
  1236. {
  1237. return bitrev16(crc16(0xFFFF, buffer, len));
  1238. }
  1239. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1240. u32 wuf_mask1)
  1241. {
  1242. int cfg_base = WUF_CFGX + filter * 4;
  1243. int mask_base = WUF_MASKX + filter * 16;
  1244. int ret;
  1245. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1246. if (ret < 0) {
  1247. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1248. return ret;
  1249. }
  1250. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1251. if (ret < 0) {
  1252. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1253. return ret;
  1254. }
  1255. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1256. if (ret < 0) {
  1257. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1258. return ret;
  1259. }
  1260. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1261. if (ret < 0) {
  1262. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1263. return ret;
  1264. }
  1265. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1266. if (ret < 0) {
  1267. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1268. return ret;
  1269. }
  1270. return 0;
  1271. }
  1272. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1273. {
  1274. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1275. u32 val;
  1276. int ret;
  1277. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1278. if (ret < 0) {
  1279. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1280. return ret;
  1281. }
  1282. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1283. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1284. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1285. if (ret < 0) {
  1286. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1287. return ret;
  1288. }
  1289. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1290. return 0;
  1291. }
  1292. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1293. {
  1294. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1295. u32 val;
  1296. int ret;
  1297. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1298. if (ret < 0) {
  1299. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1300. return ret;
  1301. }
  1302. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1303. val |= PMT_CTL_SUS_MODE_1;
  1304. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1305. if (ret < 0) {
  1306. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1307. return ret;
  1308. }
  1309. /* clear wol status, enable energy detection */
  1310. val &= ~PMT_CTL_WUPS;
  1311. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1312. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1313. if (ret < 0) {
  1314. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1315. return ret;
  1316. }
  1317. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1318. return 0;
  1319. }
  1320. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1321. {
  1322. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1323. u32 val;
  1324. int ret;
  1325. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1326. if (ret < 0) {
  1327. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1328. return ret;
  1329. }
  1330. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1331. val |= PMT_CTL_SUS_MODE_2;
  1332. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1333. if (ret < 0) {
  1334. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1335. return ret;
  1336. }
  1337. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1338. return 0;
  1339. }
  1340. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1341. {
  1342. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1343. u32 val;
  1344. int ret;
  1345. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1346. if (ret < 0) {
  1347. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1348. return ret;
  1349. }
  1350. if (val & FCT_RX_CTL_RXUSED) {
  1351. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1352. return -EBUSY;
  1353. }
  1354. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1355. if (ret < 0) {
  1356. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1357. return ret;
  1358. }
  1359. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1360. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1361. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1362. if (ret < 0) {
  1363. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1364. return ret;
  1365. }
  1366. /* clear wol status */
  1367. val &= ~PMT_CTL_WUPS;
  1368. val |= PMT_CTL_WUPS_WOL;
  1369. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1370. if (ret < 0) {
  1371. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1372. return ret;
  1373. }
  1374. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1375. return 0;
  1376. }
  1377. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1378. {
  1379. struct mii_if_info *mii = &dev->mii;
  1380. int ret;
  1381. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1382. /* read to clear */
  1383. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1384. if (ret < 0) {
  1385. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1386. return ret;
  1387. }
  1388. /* enable interrupt source */
  1389. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1390. if (ret < 0) {
  1391. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1392. return ret;
  1393. }
  1394. ret |= mask;
  1395. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1396. return 0;
  1397. }
  1398. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1399. {
  1400. struct mii_if_info *mii = &dev->mii;
  1401. int ret;
  1402. /* first, a dummy read, needed to latch some MII phys */
  1403. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1404. if (ret < 0) {
  1405. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1406. return ret;
  1407. }
  1408. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1409. if (ret < 0) {
  1410. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1411. return ret;
  1412. }
  1413. return !!(ret & BMSR_LSTATUS);
  1414. }
  1415. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1416. {
  1417. int ret;
  1418. if (!netif_running(dev->net)) {
  1419. /* interface is ifconfig down so fully power down hw */
  1420. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1421. return smsc75xx_enter_suspend2(dev);
  1422. }
  1423. if (!link_up) {
  1424. /* link is down so enter EDPD mode */
  1425. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1426. /* enable PHY wakeup events for if cable is attached */
  1427. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1428. PHY_INT_MASK_ANEG_COMP);
  1429. if (ret < 0) {
  1430. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1431. return ret;
  1432. }
  1433. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1434. return smsc75xx_enter_suspend1(dev);
  1435. }
  1436. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1437. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1438. PHY_INT_MASK_LINK_DOWN);
  1439. if (ret < 0) {
  1440. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1441. return ret;
  1442. }
  1443. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1444. return smsc75xx_enter_suspend3(dev);
  1445. }
  1446. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1447. {
  1448. struct usbnet *dev = usb_get_intfdata(intf);
  1449. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1450. u32 val, link_up;
  1451. int ret;
  1452. ret = usbnet_suspend(intf, message);
  1453. if (ret < 0) {
  1454. netdev_warn(dev->net, "usbnet_suspend error\n");
  1455. return ret;
  1456. }
  1457. if (pdata->suspend_flags) {
  1458. netdev_warn(dev->net, "error during last resume\n");
  1459. pdata->suspend_flags = 0;
  1460. }
  1461. /* determine if link is up using only _nopm functions */
  1462. link_up = smsc75xx_link_ok_nopm(dev);
  1463. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1464. ret = smsc75xx_autosuspend(dev, link_up);
  1465. goto done;
  1466. }
  1467. /* if we get this far we're not autosuspending */
  1468. /* if no wol options set, or if link is down and we're not waking on
  1469. * PHY activity, enter lowest power SUSPEND2 mode
  1470. */
  1471. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1472. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1473. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1474. /* disable energy detect (link up) & wake up events */
  1475. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1476. if (ret < 0) {
  1477. netdev_warn(dev->net, "Error reading WUCSR\n");
  1478. goto done;
  1479. }
  1480. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1481. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1482. if (ret < 0) {
  1483. netdev_warn(dev->net, "Error writing WUCSR\n");
  1484. goto done;
  1485. }
  1486. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1487. if (ret < 0) {
  1488. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1489. goto done;
  1490. }
  1491. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1492. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1493. if (ret < 0) {
  1494. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1495. goto done;
  1496. }
  1497. ret = smsc75xx_enter_suspend2(dev);
  1498. goto done;
  1499. }
  1500. if (pdata->wolopts & WAKE_PHY) {
  1501. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1502. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1503. if (ret < 0) {
  1504. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1505. goto done;
  1506. }
  1507. /* if link is down then configure EDPD and enter SUSPEND1,
  1508. * otherwise enter SUSPEND0 below
  1509. */
  1510. if (!link_up) {
  1511. struct mii_if_info *mii = &dev->mii;
  1512. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1513. /* enable energy detect power-down mode */
  1514. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1515. PHY_MODE_CTRL_STS);
  1516. if (ret < 0) {
  1517. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1518. goto done;
  1519. }
  1520. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1521. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1522. PHY_MODE_CTRL_STS, ret);
  1523. /* enter SUSPEND1 mode */
  1524. ret = smsc75xx_enter_suspend1(dev);
  1525. goto done;
  1526. }
  1527. }
  1528. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1529. int i, filter = 0;
  1530. /* disable all filters */
  1531. for (i = 0; i < WUF_NUM; i++) {
  1532. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1533. if (ret < 0) {
  1534. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1535. goto done;
  1536. }
  1537. }
  1538. if (pdata->wolopts & WAKE_MCAST) {
  1539. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1540. netdev_info(dev->net, "enabling multicast detection\n");
  1541. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1542. | smsc_crc(mcast, 3);
  1543. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1544. if (ret < 0) {
  1545. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1546. goto done;
  1547. }
  1548. }
  1549. if (pdata->wolopts & WAKE_ARP) {
  1550. const u8 arp[] = {0x08, 0x06};
  1551. netdev_info(dev->net, "enabling ARP detection\n");
  1552. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1553. | smsc_crc(arp, 2);
  1554. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1555. if (ret < 0) {
  1556. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1557. goto done;
  1558. }
  1559. }
  1560. /* clear any pending pattern match packet status */
  1561. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1562. if (ret < 0) {
  1563. netdev_warn(dev->net, "Error reading WUCSR\n");
  1564. goto done;
  1565. }
  1566. val |= WUCSR_WUFR;
  1567. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1568. if (ret < 0) {
  1569. netdev_warn(dev->net, "Error writing WUCSR\n");
  1570. goto done;
  1571. }
  1572. netdev_info(dev->net, "enabling packet match detection\n");
  1573. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1574. if (ret < 0) {
  1575. netdev_warn(dev->net, "Error reading WUCSR\n");
  1576. goto done;
  1577. }
  1578. val |= WUCSR_WUEN;
  1579. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1580. if (ret < 0) {
  1581. netdev_warn(dev->net, "Error writing WUCSR\n");
  1582. goto done;
  1583. }
  1584. } else {
  1585. netdev_info(dev->net, "disabling packet match detection\n");
  1586. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1587. if (ret < 0) {
  1588. netdev_warn(dev->net, "Error reading WUCSR\n");
  1589. goto done;
  1590. }
  1591. val &= ~WUCSR_WUEN;
  1592. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1593. if (ret < 0) {
  1594. netdev_warn(dev->net, "Error writing WUCSR\n");
  1595. goto done;
  1596. }
  1597. }
  1598. /* disable magic, bcast & unicast wakeup sources */
  1599. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1600. if (ret < 0) {
  1601. netdev_warn(dev->net, "Error reading WUCSR\n");
  1602. goto done;
  1603. }
  1604. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1605. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1606. if (ret < 0) {
  1607. netdev_warn(dev->net, "Error writing WUCSR\n");
  1608. goto done;
  1609. }
  1610. if (pdata->wolopts & WAKE_PHY) {
  1611. netdev_info(dev->net, "enabling PHY wakeup\n");
  1612. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1613. if (ret < 0) {
  1614. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1615. goto done;
  1616. }
  1617. /* clear wol status, enable energy detection */
  1618. val &= ~PMT_CTL_WUPS;
  1619. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1620. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1621. if (ret < 0) {
  1622. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1623. goto done;
  1624. }
  1625. }
  1626. if (pdata->wolopts & WAKE_MAGIC) {
  1627. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1628. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1629. if (ret < 0) {
  1630. netdev_warn(dev->net, "Error reading WUCSR\n");
  1631. goto done;
  1632. }
  1633. /* clear any pending magic packet status */
  1634. val |= WUCSR_MPR | WUCSR_MPEN;
  1635. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1636. if (ret < 0) {
  1637. netdev_warn(dev->net, "Error writing WUCSR\n");
  1638. goto done;
  1639. }
  1640. }
  1641. if (pdata->wolopts & WAKE_BCAST) {
  1642. netdev_info(dev->net, "enabling broadcast detection\n");
  1643. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1644. if (ret < 0) {
  1645. netdev_warn(dev->net, "Error reading WUCSR\n");
  1646. goto done;
  1647. }
  1648. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1649. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1650. if (ret < 0) {
  1651. netdev_warn(dev->net, "Error writing WUCSR\n");
  1652. goto done;
  1653. }
  1654. }
  1655. if (pdata->wolopts & WAKE_UCAST) {
  1656. netdev_info(dev->net, "enabling unicast detection\n");
  1657. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1658. if (ret < 0) {
  1659. netdev_warn(dev->net, "Error reading WUCSR\n");
  1660. goto done;
  1661. }
  1662. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1663. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1664. if (ret < 0) {
  1665. netdev_warn(dev->net, "Error writing WUCSR\n");
  1666. goto done;
  1667. }
  1668. }
  1669. /* enable receiver to enable frame reception */
  1670. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1671. if (ret < 0) {
  1672. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1673. goto done;
  1674. }
  1675. val |= MAC_RX_RXEN;
  1676. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1677. if (ret < 0) {
  1678. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1679. goto done;
  1680. }
  1681. /* some wol options are enabled, so enter SUSPEND0 */
  1682. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1683. ret = smsc75xx_enter_suspend0(dev);
  1684. done:
  1685. /*
  1686. * TODO: resume() might need to handle the suspend failure
  1687. * in system sleep
  1688. */
  1689. if (ret && PMSG_IS_AUTO(message))
  1690. usbnet_resume(intf);
  1691. return ret;
  1692. }
  1693. static int smsc75xx_resume(struct usb_interface *intf)
  1694. {
  1695. struct usbnet *dev = usb_get_intfdata(intf);
  1696. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1697. u8 suspend_flags = pdata->suspend_flags;
  1698. int ret;
  1699. u32 val;
  1700. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1701. /* do this first to ensure it's cleared even in error case */
  1702. pdata->suspend_flags = 0;
  1703. if (suspend_flags & SUSPEND_ALLMODES) {
  1704. /* Disable wakeup sources */
  1705. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1706. if (ret < 0) {
  1707. netdev_warn(dev->net, "Error reading WUCSR\n");
  1708. return ret;
  1709. }
  1710. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1711. | WUCSR_BCST_EN);
  1712. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1713. if (ret < 0) {
  1714. netdev_warn(dev->net, "Error writing WUCSR\n");
  1715. return ret;
  1716. }
  1717. /* clear wake-up status */
  1718. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1719. if (ret < 0) {
  1720. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1721. return ret;
  1722. }
  1723. val &= ~PMT_CTL_WOL_EN;
  1724. val |= PMT_CTL_WUPS;
  1725. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1726. if (ret < 0) {
  1727. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1728. return ret;
  1729. }
  1730. }
  1731. if (suspend_flags & SUSPEND_SUSPEND2) {
  1732. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1733. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1734. if (ret < 0) {
  1735. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1736. return ret;
  1737. }
  1738. val |= PMT_CTL_PHY_PWRUP;
  1739. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1740. if (ret < 0) {
  1741. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1742. return ret;
  1743. }
  1744. }
  1745. ret = smsc75xx_wait_ready(dev, 1);
  1746. if (ret < 0) {
  1747. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1748. return ret;
  1749. }
  1750. return usbnet_resume(intf);
  1751. }
  1752. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1753. u32 rx_cmd_a, u32 rx_cmd_b)
  1754. {
  1755. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1756. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1757. skb->ip_summed = CHECKSUM_NONE;
  1758. } else {
  1759. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1760. skb->ip_summed = CHECKSUM_COMPLETE;
  1761. }
  1762. }
  1763. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1764. {
  1765. /* This check is no longer done by usbnet */
  1766. if (skb->len < dev->net->hard_header_len)
  1767. return 0;
  1768. while (skb->len > 0) {
  1769. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1770. struct sk_buff *ax_skb;
  1771. unsigned char *packet;
  1772. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1773. le32_to_cpus(&rx_cmd_a);
  1774. skb_pull(skb, 4);
  1775. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1776. le32_to_cpus(&rx_cmd_b);
  1777. skb_pull(skb, 4 + RXW_PADDING);
  1778. packet = skb->data;
  1779. /* get the packet length */
  1780. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1781. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1782. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1783. netif_dbg(dev, rx_err, dev->net,
  1784. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1785. dev->net->stats.rx_errors++;
  1786. dev->net->stats.rx_dropped++;
  1787. if (rx_cmd_a & RX_CMD_A_FCS)
  1788. dev->net->stats.rx_crc_errors++;
  1789. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1790. dev->net->stats.rx_frame_errors++;
  1791. } else {
  1792. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1793. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1794. netif_dbg(dev, rx_err, dev->net,
  1795. "size err rx_cmd_a=0x%08x\n",
  1796. rx_cmd_a);
  1797. return 0;
  1798. }
  1799. /* last frame in this batch */
  1800. if (skb->len == size) {
  1801. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1802. rx_cmd_b);
  1803. skb_trim(skb, skb->len - 4); /* remove fcs */
  1804. skb->truesize = size + sizeof(struct sk_buff);
  1805. return 1;
  1806. }
  1807. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1808. if (unlikely(!ax_skb)) {
  1809. netdev_warn(dev->net, "Error allocating skb\n");
  1810. return 0;
  1811. }
  1812. ax_skb->len = size;
  1813. ax_skb->data = packet;
  1814. skb_set_tail_pointer(ax_skb, size);
  1815. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1816. rx_cmd_b);
  1817. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1818. ax_skb->truesize = size + sizeof(struct sk_buff);
  1819. usbnet_skb_return(dev, ax_skb);
  1820. }
  1821. skb_pull(skb, size);
  1822. /* padding bytes before the next frame starts */
  1823. if (skb->len)
  1824. skb_pull(skb, align_count);
  1825. }
  1826. return 1;
  1827. }
  1828. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1829. struct sk_buff *skb, gfp_t flags)
  1830. {
  1831. u32 tx_cmd_a, tx_cmd_b;
  1832. if (skb_cow_head(skb, SMSC75XX_TX_OVERHEAD)) {
  1833. dev_kfree_skb_any(skb);
  1834. return NULL;
  1835. }
  1836. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1837. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1838. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1839. if (skb_is_gso(skb)) {
  1840. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1841. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1842. tx_cmd_a |= TX_CMD_A_LSO;
  1843. } else {
  1844. tx_cmd_b = 0;
  1845. }
  1846. skb_push(skb, 4);
  1847. cpu_to_le32s(&tx_cmd_b);
  1848. memcpy(skb->data, &tx_cmd_b, 4);
  1849. skb_push(skb, 4);
  1850. cpu_to_le32s(&tx_cmd_a);
  1851. memcpy(skb->data, &tx_cmd_a, 4);
  1852. return skb;
  1853. }
  1854. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1855. {
  1856. dev->intf->needs_remote_wakeup = on;
  1857. return 0;
  1858. }
  1859. static const struct driver_info smsc75xx_info = {
  1860. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1861. .bind = smsc75xx_bind,
  1862. .unbind = smsc75xx_unbind,
  1863. .link_reset = smsc75xx_link_reset,
  1864. .reset = smsc75xx_reset,
  1865. .rx_fixup = smsc75xx_rx_fixup,
  1866. .tx_fixup = smsc75xx_tx_fixup,
  1867. .status = smsc75xx_status,
  1868. .manage_power = smsc75xx_manage_power,
  1869. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1870. };
  1871. static const struct usb_device_id products[] = {
  1872. {
  1873. /* SMSC7500 USB Gigabit Ethernet Device */
  1874. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1875. .driver_info = (unsigned long) &smsc75xx_info,
  1876. },
  1877. {
  1878. /* SMSC7500 USB Gigabit Ethernet Device */
  1879. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1880. .driver_info = (unsigned long) &smsc75xx_info,
  1881. },
  1882. { }, /* END */
  1883. };
  1884. MODULE_DEVICE_TABLE(usb, products);
  1885. static struct usb_driver smsc75xx_driver = {
  1886. .name = SMSC_CHIPNAME,
  1887. .id_table = products,
  1888. .probe = usbnet_probe,
  1889. .suspend = smsc75xx_suspend,
  1890. .resume = smsc75xx_resume,
  1891. .reset_resume = smsc75xx_resume,
  1892. .disconnect = usbnet_disconnect,
  1893. .disable_hub_initiated_lpm = 1,
  1894. .supports_autosuspend = 1,
  1895. };
  1896. module_usb_driver(smsc75xx_driver);
  1897. MODULE_AUTHOR("Nancy Lin");
  1898. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1899. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1900. MODULE_LICENSE("GPL");