dscc4.c 53 KB

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  1. /*
  2. * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
  3. *
  4. * This software may be used and distributed according to the terms of the
  5. * GNU General Public License.
  6. *
  7. * The author may be reached as romieu@cogenit.fr.
  8. * Specific bug reports/asian food will be welcome.
  9. *
  10. * Special thanks to the nice people at CS-Telecom for the hardware and the
  11. * access to the test/measure tools.
  12. *
  13. *
  14. * Theory of Operation
  15. *
  16. * I. Board Compatibility
  17. *
  18. * This device driver is designed for the Siemens PEB20534 4 ports serial
  19. * controller as found on Etinc PCISYNC cards. The documentation for the
  20. * chipset is available at http://www.infineon.com:
  21. * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
  22. * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
  23. * - Application Hint "Management of DSCC4 on-chip FIFO resources".
  24. * - Errata sheet DS5 (courtesy of Michael Skerritt).
  25. * Jens David has built an adapter based on the same chipset. Take a look
  26. * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
  27. * driver.
  28. * Sample code (2 revisions) is available at Infineon.
  29. *
  30. * II. Board-specific settings
  31. *
  32. * Pcisync can transmit some clock signal to the outside world on the
  33. * *first two* ports provided you put a quartz and a line driver on it and
  34. * remove the jumpers. The operation is described on Etinc web site. If you
  35. * go DCE on these ports, don't forget to use an adequate cable.
  36. *
  37. * Sharing of the PCI interrupt line for this board is possible.
  38. *
  39. * III. Driver operation
  40. *
  41. * The rx/tx operations are based on a linked list of descriptors. The driver
  42. * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
  43. * I tried to fix it, the more it started to look like (convoluted) software
  44. * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
  45. * this a rfc2119 MUST.
  46. *
  47. * Tx direction
  48. * When the tx ring is full, the xmit routine issues a call to netdev_stop.
  49. * The device is supposed to be enabled again during an ALLS irq (we could
  50. * use HI but as it's easy to lose events, it's fscked).
  51. *
  52. * Rx direction
  53. * The received frames aren't supposed to span over multiple receiving areas.
  54. * I may implement it some day but it isn't the highest ranked item.
  55. *
  56. * IV. Notes
  57. * The current error (XDU, RFO) recovery code is untested.
  58. * So far, RDO takes his RX channel down and the right sequence to enable it
  59. * again is still a mystery. If RDO happens, plan a reboot. More details
  60. * in the code (NB: as this happens, TX still works).
  61. * Don't mess the cables during operation, especially on DTE ports. I don't
  62. * suggest it for DCE either but at least one can get some messages instead
  63. * of a complete instant freeze.
  64. * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
  65. * the documentation/chipset releases.
  66. *
  67. * TODO:
  68. * - test X25.
  69. * - use polling at high irq/s,
  70. * - performance analysis,
  71. * - endianness.
  72. *
  73. * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
  74. * - Contribution to support the new generic HDLC layer.
  75. *
  76. * 2002/01 Ueimor
  77. * - old style interface removal
  78. * - dscc4_release_ring fix (related to DMA mapping)
  79. * - hard_start_xmit fix (hint: TxSizeMax)
  80. * - misc crapectomy.
  81. */
  82. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  83. #include <linux/module.h>
  84. #include <linux/sched.h>
  85. #include <linux/types.h>
  86. #include <linux/errno.h>
  87. #include <linux/list.h>
  88. #include <linux/ioport.h>
  89. #include <linux/pci.h>
  90. #include <linux/kernel.h>
  91. #include <linux/mm.h>
  92. #include <linux/slab.h>
  93. #include <asm/cache.h>
  94. #include <asm/byteorder.h>
  95. #include <linux/uaccess.h>
  96. #include <asm/io.h>
  97. #include <asm/irq.h>
  98. #include <linux/init.h>
  99. #include <linux/interrupt.h>
  100. #include <linux/string.h>
  101. #include <linux/if_arp.h>
  102. #include <linux/netdevice.h>
  103. #include <linux/skbuff.h>
  104. #include <linux/delay.h>
  105. #include <linux/hdlc.h>
  106. #include <linux/mutex.h>
  107. /* Version */
  108. static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
  109. static int debug;
  110. static int quartz;
  111. #ifdef CONFIG_DSCC4_PCI_RST
  112. static DEFINE_MUTEX(dscc4_mutex);
  113. static u32 dscc4_pci_config_store[16];
  114. #endif
  115. #define DRV_NAME "dscc4"
  116. #undef DSCC4_POLLING
  117. /* Module parameters */
  118. MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
  119. MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller");
  120. MODULE_LICENSE("GPL");
  121. module_param(debug, int, 0);
  122. MODULE_PARM_DESC(debug,"Enable/disable extra messages");
  123. module_param(quartz, int, 0);
  124. MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
  125. /* Structures */
  126. struct thingie {
  127. int define;
  128. u32 bits;
  129. };
  130. struct TxFD {
  131. __le32 state;
  132. __le32 next;
  133. __le32 data;
  134. __le32 complete;
  135. u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
  136. /* FWIW, datasheet calls that "dummy" and says that card
  137. * never looks at it; neither does the driver */
  138. };
  139. struct RxFD {
  140. __le32 state1;
  141. __le32 next;
  142. __le32 data;
  143. __le32 state2;
  144. __le32 end;
  145. };
  146. #define DUMMY_SKB_SIZE 64
  147. #define TX_LOW 8
  148. #define TX_RING_SIZE 32
  149. #define RX_RING_SIZE 32
  150. #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
  151. #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
  152. #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
  153. #define TX_TIMEOUT (HZ/10)
  154. #define DSCC4_HZ_MAX 33000000
  155. #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
  156. #define dev_per_card 4
  157. #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
  158. #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
  159. #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
  160. /*
  161. * Given the operating range of Linux HDLC, the 2 defines below could be
  162. * made simpler. However they are a fine reminder for the limitations of
  163. * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
  164. */
  165. #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
  166. #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
  167. #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
  168. #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
  169. struct dscc4_pci_priv {
  170. __le32 *iqcfg;
  171. int cfg_cur;
  172. spinlock_t lock;
  173. struct pci_dev *pdev;
  174. struct dscc4_dev_priv *root;
  175. dma_addr_t iqcfg_dma;
  176. u32 xtal_hz;
  177. };
  178. struct dscc4_dev_priv {
  179. struct sk_buff *rx_skbuff[RX_RING_SIZE];
  180. struct sk_buff *tx_skbuff[TX_RING_SIZE];
  181. struct RxFD *rx_fd;
  182. struct TxFD *tx_fd;
  183. __le32 *iqrx;
  184. __le32 *iqtx;
  185. /* FIXME: check all the volatile are required */
  186. volatile u32 tx_current;
  187. u32 rx_current;
  188. u32 iqtx_current;
  189. u32 iqrx_current;
  190. volatile u32 tx_dirty;
  191. volatile u32 ltda;
  192. u32 rx_dirty;
  193. u32 lrda;
  194. dma_addr_t tx_fd_dma;
  195. dma_addr_t rx_fd_dma;
  196. dma_addr_t iqtx_dma;
  197. dma_addr_t iqrx_dma;
  198. u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
  199. struct dscc4_pci_priv *pci_priv;
  200. spinlock_t lock;
  201. int dev_id;
  202. volatile u32 flags;
  203. u32 timer_help;
  204. unsigned short encoding;
  205. unsigned short parity;
  206. struct net_device *dev;
  207. sync_serial_settings settings;
  208. void __iomem *base_addr;
  209. u32 __pad __attribute__ ((aligned (4)));
  210. };
  211. /* GLOBAL registers definitions */
  212. #define GCMDR 0x00
  213. #define GSTAR 0x04
  214. #define GMODE 0x08
  215. #define IQLENR0 0x0C
  216. #define IQLENR1 0x10
  217. #define IQRX0 0x14
  218. #define IQTX0 0x24
  219. #define IQCFG 0x3c
  220. #define FIFOCR1 0x44
  221. #define FIFOCR2 0x48
  222. #define FIFOCR3 0x4c
  223. #define FIFOCR4 0x34
  224. #define CH0CFG 0x50
  225. #define CH0BRDA 0x54
  226. #define CH0BTDA 0x58
  227. #define CH0FRDA 0x98
  228. #define CH0FTDA 0xb0
  229. #define CH0LRDA 0xc8
  230. #define CH0LTDA 0xe0
  231. /* SCC registers definitions */
  232. #define SCC_START 0x0100
  233. #define SCC_OFFSET 0x80
  234. #define CMDR 0x00
  235. #define STAR 0x04
  236. #define CCR0 0x08
  237. #define CCR1 0x0c
  238. #define CCR2 0x10
  239. #define BRR 0x2C
  240. #define RLCR 0x40
  241. #define IMR 0x54
  242. #define ISR 0x58
  243. #define GPDIR 0x0400
  244. #define GPDATA 0x0404
  245. #define GPIM 0x0408
  246. /* Bit masks */
  247. #define EncodingMask 0x00700000
  248. #define CrcMask 0x00000003
  249. #define IntRxScc0 0x10000000
  250. #define IntTxScc0 0x01000000
  251. #define TxPollCmd 0x00000400
  252. #define RxActivate 0x08000000
  253. #define MTFi 0x04000000
  254. #define Rdr 0x00400000
  255. #define Rdt 0x00200000
  256. #define Idr 0x00100000
  257. #define Idt 0x00080000
  258. #define TxSccRes 0x01000000
  259. #define RxSccRes 0x00010000
  260. #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
  261. #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
  262. #define Ccr0ClockMask 0x0000003f
  263. #define Ccr1LoopMask 0x00000200
  264. #define IsrMask 0x000fffff
  265. #define BrrExpMask 0x00000f00
  266. #define BrrMultMask 0x0000003f
  267. #define EncodingMask 0x00700000
  268. #define Hold cpu_to_le32(0x40000000)
  269. #define SccBusy 0x10000000
  270. #define PowerUp 0x80000000
  271. #define Vis 0x00001000
  272. #define FrameOk (FrameVfr | FrameCrc)
  273. #define FrameVfr 0x80
  274. #define FrameRdo 0x40
  275. #define FrameCrc 0x20
  276. #define FrameRab 0x10
  277. #define FrameAborted cpu_to_le32(0x00000200)
  278. #define FrameEnd cpu_to_le32(0x80000000)
  279. #define DataComplete cpu_to_le32(0x40000000)
  280. #define LengthCheck 0x00008000
  281. #define SccEvt 0x02000000
  282. #define NoAck 0x00000200
  283. #define Action 0x00000001
  284. #define HiDesc cpu_to_le32(0x20000000)
  285. /* SCC events */
  286. #define RxEvt 0xf0000000
  287. #define TxEvt 0x0f000000
  288. #define Alls 0x00040000
  289. #define Xdu 0x00010000
  290. #define Cts 0x00004000
  291. #define Xmr 0x00002000
  292. #define Xpr 0x00001000
  293. #define Rdo 0x00000080
  294. #define Rfs 0x00000040
  295. #define Cd 0x00000004
  296. #define Rfo 0x00000002
  297. #define Flex 0x00000001
  298. /* DMA core events */
  299. #define Cfg 0x00200000
  300. #define Hi 0x00040000
  301. #define Fi 0x00020000
  302. #define Err 0x00010000
  303. #define Arf 0x00000002
  304. #define ArAck 0x00000001
  305. /* State flags */
  306. #define Ready 0x00000000
  307. #define NeedIDR 0x00000001
  308. #define NeedIDT 0x00000002
  309. #define RdoSet 0x00000004
  310. #define FakeReset 0x00000008
  311. /* Don't mask RDO. Ever. */
  312. #ifdef DSCC4_POLLING
  313. #define EventsMask 0xfffeef7f
  314. #else
  315. #define EventsMask 0xfffa8f7a
  316. #endif
  317. /* Functions prototypes */
  318. static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
  319. static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
  320. static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
  321. static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
  322. static int dscc4_open(struct net_device *);
  323. static netdev_tx_t dscc4_start_xmit(struct sk_buff *,
  324. struct net_device *);
  325. static int dscc4_close(struct net_device *);
  326. static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  327. static int dscc4_init_ring(struct net_device *);
  328. static void dscc4_release_ring(struct dscc4_dev_priv *);
  329. static void dscc4_tx_timeout(struct net_device *);
  330. static irqreturn_t dscc4_irq(int irq, void *dev_id);
  331. static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
  332. static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
  333. #ifdef DSCC4_POLLING
  334. static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
  335. #endif
  336. static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
  337. {
  338. return dev_to_hdlc(dev)->priv;
  339. }
  340. static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
  341. {
  342. return p->dev;
  343. }
  344. static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
  345. struct net_device *dev, int offset)
  346. {
  347. u32 state;
  348. /* Cf scc_writel for concern regarding thread-safety */
  349. state = dpriv->scc_regs[offset >> 2];
  350. state &= ~mask;
  351. state |= value;
  352. dpriv->scc_regs[offset >> 2] = state;
  353. writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
  354. }
  355. static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
  356. struct net_device *dev, int offset)
  357. {
  358. /*
  359. * Thread-UNsafe.
  360. * As of 2002/02/16, there are no thread racing for access.
  361. */
  362. dpriv->scc_regs[offset >> 2] = bits;
  363. writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
  364. }
  365. static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
  366. {
  367. return dpriv->scc_regs[offset >> 2];
  368. }
  369. static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
  370. {
  371. /* Cf errata DS5 p.4 */
  372. readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
  373. return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
  374. }
  375. static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
  376. struct net_device *dev)
  377. {
  378. dpriv->ltda = dpriv->tx_fd_dma +
  379. ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
  380. writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
  381. /* Flush posted writes *NOW* */
  382. readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
  383. }
  384. static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
  385. struct net_device *dev)
  386. {
  387. dpriv->lrda = dpriv->rx_fd_dma +
  388. ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
  389. writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
  390. }
  391. static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
  392. {
  393. return dpriv->tx_current == dpriv->tx_dirty;
  394. }
  395. static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
  396. struct net_device *dev)
  397. {
  398. return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
  399. }
  400. static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
  401. struct net_device *dev, const char *msg)
  402. {
  403. int ret = 0;
  404. if (debug > 1) {
  405. if (SOURCE_ID(state) != dpriv->dev_id) {
  406. printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
  407. dev->name, msg, SOURCE_ID(state), state );
  408. ret = -1;
  409. }
  410. if (state & 0x0df80c00) {
  411. printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
  412. dev->name, msg, state);
  413. ret = -1;
  414. }
  415. }
  416. return ret;
  417. }
  418. static void dscc4_tx_print(struct net_device *dev,
  419. struct dscc4_dev_priv *dpriv,
  420. char *msg)
  421. {
  422. printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
  423. dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
  424. }
  425. static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
  426. {
  427. struct device *d = &dpriv->pci_priv->pdev->dev;
  428. struct TxFD *tx_fd = dpriv->tx_fd;
  429. struct RxFD *rx_fd = dpriv->rx_fd;
  430. struct sk_buff **skbuff;
  431. int i;
  432. dma_free_coherent(d, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
  433. dma_free_coherent(d, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
  434. skbuff = dpriv->tx_skbuff;
  435. for (i = 0; i < TX_RING_SIZE; i++) {
  436. if (*skbuff) {
  437. dma_unmap_single(d, le32_to_cpu(tx_fd->data),
  438. (*skbuff)->len, DMA_TO_DEVICE);
  439. dev_kfree_skb(*skbuff);
  440. }
  441. skbuff++;
  442. tx_fd++;
  443. }
  444. skbuff = dpriv->rx_skbuff;
  445. for (i = 0; i < RX_RING_SIZE; i++) {
  446. if (*skbuff) {
  447. dma_unmap_single(d, le32_to_cpu(rx_fd->data),
  448. RX_MAX(HDLC_MAX_MRU),
  449. DMA_FROM_DEVICE);
  450. dev_kfree_skb(*skbuff);
  451. }
  452. skbuff++;
  453. rx_fd++;
  454. }
  455. }
  456. static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
  457. struct net_device *dev)
  458. {
  459. unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
  460. struct device *d = &dpriv->pci_priv->pdev->dev;
  461. struct RxFD *rx_fd = dpriv->rx_fd + dirty;
  462. const int len = RX_MAX(HDLC_MAX_MRU);
  463. struct sk_buff *skb;
  464. dma_addr_t addr;
  465. skb = dev_alloc_skb(len);
  466. if (!skb)
  467. goto err_out;
  468. skb->protocol = hdlc_type_trans(skb, dev);
  469. addr = dma_map_single(d, skb->data, len, DMA_FROM_DEVICE);
  470. if (dma_mapping_error(d, addr))
  471. goto err_free_skb;
  472. dpriv->rx_skbuff[dirty] = skb;
  473. rx_fd->data = cpu_to_le32(addr);
  474. return 0;
  475. err_free_skb:
  476. dev_kfree_skb_any(skb);
  477. err_out:
  478. rx_fd->data = 0;
  479. return -1;
  480. }
  481. /*
  482. * IRQ/thread/whatever safe
  483. */
  484. static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
  485. struct net_device *dev, char *msg)
  486. {
  487. s8 i = 0;
  488. do {
  489. if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
  490. printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
  491. msg, i);
  492. goto done;
  493. }
  494. schedule_timeout_uninterruptible(msecs_to_jiffies(100));
  495. rmb();
  496. } while (++i > 0);
  497. netdev_err(dev, "%s timeout\n", msg);
  498. done:
  499. return (i >= 0) ? i : -EAGAIN;
  500. }
  501. static int dscc4_do_action(struct net_device *dev, char *msg)
  502. {
  503. void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
  504. s16 i = 0;
  505. writel(Action, ioaddr + GCMDR);
  506. ioaddr += GSTAR;
  507. do {
  508. u32 state = readl(ioaddr);
  509. if (state & ArAck) {
  510. netdev_dbg(dev, "%s ack\n", msg);
  511. writel(ArAck, ioaddr);
  512. goto done;
  513. } else if (state & Arf) {
  514. netdev_err(dev, "%s failed\n", msg);
  515. writel(Arf, ioaddr);
  516. i = -1;
  517. goto done;
  518. }
  519. rmb();
  520. } while (++i > 0);
  521. netdev_err(dev, "%s timeout\n", msg);
  522. done:
  523. return i;
  524. }
  525. static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
  526. {
  527. int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
  528. s8 i = 0;
  529. do {
  530. if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
  531. (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
  532. break;
  533. smp_rmb();
  534. schedule_timeout_uninterruptible(msecs_to_jiffies(100));
  535. } while (++i > 0);
  536. return (i >= 0 ) ? i : -EAGAIN;
  537. }
  538. #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
  539. static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
  540. {
  541. unsigned long flags;
  542. spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
  543. /* Cf errata DS5 p.6 */
  544. writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
  545. scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
  546. readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
  547. writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
  548. writel(Action, dpriv->base_addr + GCMDR);
  549. spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
  550. }
  551. #endif
  552. #if 0
  553. static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
  554. {
  555. u16 i = 0;
  556. /* Cf errata DS5 p.7 */
  557. scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
  558. scc_writel(0x00050000, dpriv, dev, CCR2);
  559. /*
  560. * Must be longer than the time required to fill the fifo.
  561. */
  562. while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
  563. udelay(1);
  564. wmb();
  565. }
  566. writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
  567. if (dscc4_do_action(dev, "Rdt") < 0)
  568. netdev_err(dev, "Tx reset failed\n");
  569. }
  570. #endif
  571. /* TODO: (ab)use this function to refill a completely depleted RX ring. */
  572. static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
  573. struct net_device *dev)
  574. {
  575. struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
  576. struct device *d = &dpriv->pci_priv->pdev->dev;
  577. struct sk_buff *skb;
  578. int pkt_len;
  579. skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
  580. if (!skb) {
  581. printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
  582. goto refill;
  583. }
  584. pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
  585. dma_unmap_single(d, le32_to_cpu(rx_fd->data),
  586. RX_MAX(HDLC_MAX_MRU), DMA_FROM_DEVICE);
  587. if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
  588. dev->stats.rx_packets++;
  589. dev->stats.rx_bytes += pkt_len;
  590. skb_put(skb, pkt_len);
  591. if (netif_running(dev))
  592. skb->protocol = hdlc_type_trans(skb, dev);
  593. netif_rx(skb);
  594. } else {
  595. if (skb->data[pkt_len] & FrameRdo)
  596. dev->stats.rx_fifo_errors++;
  597. else if (!(skb->data[pkt_len] & FrameCrc))
  598. dev->stats.rx_crc_errors++;
  599. else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) !=
  600. (FrameVfr | FrameRab))
  601. dev->stats.rx_length_errors++;
  602. dev->stats.rx_errors++;
  603. dev_kfree_skb_irq(skb);
  604. }
  605. refill:
  606. while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
  607. if (try_get_rx_skb(dpriv, dev) < 0)
  608. break;
  609. dpriv->rx_dirty++;
  610. }
  611. dscc4_rx_update(dpriv, dev);
  612. rx_fd->state2 = 0x00000000;
  613. rx_fd->end = cpu_to_le32(0xbabeface);
  614. }
  615. static void dscc4_free1(struct pci_dev *pdev)
  616. {
  617. struct dscc4_pci_priv *ppriv;
  618. struct dscc4_dev_priv *root;
  619. int i;
  620. ppriv = pci_get_drvdata(pdev);
  621. root = ppriv->root;
  622. for (i = 0; i < dev_per_card; i++)
  623. unregister_hdlc_device(dscc4_to_dev(root + i));
  624. for (i = 0; i < dev_per_card; i++)
  625. free_netdev(root[i].dev);
  626. kfree(root);
  627. kfree(ppriv);
  628. }
  629. static int dscc4_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  630. {
  631. struct dscc4_pci_priv *priv;
  632. struct dscc4_dev_priv *dpriv;
  633. void __iomem *ioaddr;
  634. int i, rc;
  635. printk(KERN_DEBUG "%s", version);
  636. rc = pci_enable_device(pdev);
  637. if (rc < 0)
  638. goto out;
  639. rc = pci_request_region(pdev, 0, "registers");
  640. if (rc < 0) {
  641. pr_err("can't reserve MMIO region (regs)\n");
  642. goto err_disable_0;
  643. }
  644. rc = pci_request_region(pdev, 1, "LBI interface");
  645. if (rc < 0) {
  646. pr_err("can't reserve MMIO region (lbi)\n");
  647. goto err_free_mmio_region_1;
  648. }
  649. ioaddr = pci_ioremap_bar(pdev, 0);
  650. if (!ioaddr) {
  651. pr_err("cannot remap MMIO region %llx @ %llx\n",
  652. (unsigned long long)pci_resource_len(pdev, 0),
  653. (unsigned long long)pci_resource_start(pdev, 0));
  654. rc = -EIO;
  655. goto err_free_mmio_regions_2;
  656. }
  657. printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
  658. (unsigned long long)pci_resource_start(pdev, 0),
  659. (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
  660. /* Cf errata DS5 p.2 */
  661. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
  662. pci_set_master(pdev);
  663. rc = dscc4_found1(pdev, ioaddr);
  664. if (rc < 0)
  665. goto err_iounmap_3;
  666. priv = pci_get_drvdata(pdev);
  667. rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
  668. if (rc < 0) {
  669. pr_warn("IRQ %d busy\n", pdev->irq);
  670. goto err_release_4;
  671. }
  672. /* power up/little endian/dma core controlled via lrda/ltda */
  673. writel(0x00000001, ioaddr + GMODE);
  674. /* Shared interrupt queue */
  675. {
  676. u32 bits;
  677. bits = (IRQ_RING_SIZE >> 5) - 1;
  678. bits |= bits << 4;
  679. bits |= bits << 8;
  680. bits |= bits << 16;
  681. writel(bits, ioaddr + IQLENR0);
  682. }
  683. /* Global interrupt queue */
  684. writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
  685. rc = -ENOMEM;
  686. priv->iqcfg = (__le32 *)dma_alloc_coherent(&pdev->dev,
  687. IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma, GFP_KERNEL);
  688. if (!priv->iqcfg)
  689. goto err_free_irq_5;
  690. writel(priv->iqcfg_dma, ioaddr + IQCFG);
  691. /*
  692. * SCC 0-3 private rx/tx irq structures
  693. * IQRX/TXi needs to be set soon. Learned it the hard way...
  694. */
  695. for (i = 0; i < dev_per_card; i++) {
  696. dpriv = priv->root + i;
  697. dpriv->iqtx = (__le32 *)dma_alloc_coherent(&pdev->dev,
  698. IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma,
  699. GFP_KERNEL);
  700. if (!dpriv->iqtx)
  701. goto err_free_iqtx_6;
  702. writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
  703. }
  704. for (i = 0; i < dev_per_card; i++) {
  705. dpriv = priv->root + i;
  706. dpriv->iqrx = (__le32 *)dma_alloc_coherent(&pdev->dev,
  707. IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma,
  708. GFP_KERNEL);
  709. if (!dpriv->iqrx)
  710. goto err_free_iqrx_7;
  711. writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
  712. }
  713. /* Cf application hint. Beware of hard-lock condition on threshold. */
  714. writel(0x42104000, ioaddr + FIFOCR1);
  715. //writel(0x9ce69800, ioaddr + FIFOCR2);
  716. writel(0xdef6d800, ioaddr + FIFOCR2);
  717. //writel(0x11111111, ioaddr + FIFOCR4);
  718. writel(0x18181818, ioaddr + FIFOCR4);
  719. // FIXME: should depend on the chipset revision
  720. writel(0x0000000e, ioaddr + FIFOCR3);
  721. writel(0xff200001, ioaddr + GCMDR);
  722. rc = 0;
  723. out:
  724. return rc;
  725. err_free_iqrx_7:
  726. while (--i >= 0) {
  727. dpriv = priv->root + i;
  728. dma_free_coherent(&pdev->dev, IRQ_RING_SIZE*sizeof(u32),
  729. dpriv->iqrx, dpriv->iqrx_dma);
  730. }
  731. i = dev_per_card;
  732. err_free_iqtx_6:
  733. while (--i >= 0) {
  734. dpriv = priv->root + i;
  735. dma_free_coherent(&pdev->dev, IRQ_RING_SIZE*sizeof(u32),
  736. dpriv->iqtx, dpriv->iqtx_dma);
  737. }
  738. dma_free_coherent(&pdev->dev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
  739. priv->iqcfg_dma);
  740. err_free_irq_5:
  741. free_irq(pdev->irq, priv->root);
  742. err_release_4:
  743. dscc4_free1(pdev);
  744. err_iounmap_3:
  745. iounmap (ioaddr);
  746. err_free_mmio_regions_2:
  747. pci_release_region(pdev, 1);
  748. err_free_mmio_region_1:
  749. pci_release_region(pdev, 0);
  750. err_disable_0:
  751. pci_disable_device(pdev);
  752. goto out;
  753. };
  754. /*
  755. * Let's hope the default values are decent enough to protect my
  756. * feet from the user's gun - Ueimor
  757. */
  758. static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
  759. struct net_device *dev)
  760. {
  761. /* No interrupts, SCC core disabled. Let's relax */
  762. scc_writel(0x00000000, dpriv, dev, CCR0);
  763. scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
  764. /*
  765. * No address recognition/crc-CCITT/cts enabled
  766. * Shared flags transmission disabled - cf errata DS5 p.11
  767. * Carrier detect disabled - cf errata p.14
  768. * FIXME: carrier detection/polarity may be handled more gracefully.
  769. */
  770. scc_writel(0x02408000, dpriv, dev, CCR1);
  771. /* crc not forwarded - Cf errata DS5 p.11 */
  772. scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
  773. // crc forwarded
  774. //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
  775. }
  776. static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
  777. {
  778. int ret = 0;
  779. if ((hz < 0) || (hz > DSCC4_HZ_MAX))
  780. ret = -EOPNOTSUPP;
  781. else
  782. dpriv->pci_priv->xtal_hz = hz;
  783. return ret;
  784. }
  785. static const struct net_device_ops dscc4_ops = {
  786. .ndo_open = dscc4_open,
  787. .ndo_stop = dscc4_close,
  788. .ndo_start_xmit = hdlc_start_xmit,
  789. .ndo_do_ioctl = dscc4_ioctl,
  790. .ndo_tx_timeout = dscc4_tx_timeout,
  791. };
  792. static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
  793. {
  794. struct dscc4_pci_priv *ppriv;
  795. struct dscc4_dev_priv *root;
  796. int i, ret = -ENOMEM;
  797. root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
  798. if (!root)
  799. goto err_out;
  800. for (i = 0; i < dev_per_card; i++) {
  801. root[i].dev = alloc_hdlcdev(root + i);
  802. if (!root[i].dev)
  803. goto err_free_dev;
  804. }
  805. ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
  806. if (!ppriv)
  807. goto err_free_dev;
  808. ppriv->root = root;
  809. spin_lock_init(&ppriv->lock);
  810. for (i = 0; i < dev_per_card; i++) {
  811. struct dscc4_dev_priv *dpriv = root + i;
  812. struct net_device *d = dscc4_to_dev(dpriv);
  813. hdlc_device *hdlc = dev_to_hdlc(d);
  814. d->base_addr = (unsigned long)ioaddr;
  815. d->irq = pdev->irq;
  816. d->netdev_ops = &dscc4_ops;
  817. d->watchdog_timeo = TX_TIMEOUT;
  818. SET_NETDEV_DEV(d, &pdev->dev);
  819. dpriv->dev_id = i;
  820. dpriv->pci_priv = ppriv;
  821. dpriv->base_addr = ioaddr;
  822. spin_lock_init(&dpriv->lock);
  823. hdlc->xmit = dscc4_start_xmit;
  824. hdlc->attach = dscc4_hdlc_attach;
  825. dscc4_init_registers(dpriv, d);
  826. dpriv->parity = PARITY_CRC16_PR0_CCITT;
  827. dpriv->encoding = ENCODING_NRZ;
  828. ret = dscc4_init_ring(d);
  829. if (ret < 0)
  830. goto err_unregister;
  831. ret = register_hdlc_device(d);
  832. if (ret < 0) {
  833. pr_err("unable to register\n");
  834. dscc4_release_ring(dpriv);
  835. goto err_unregister;
  836. }
  837. }
  838. ret = dscc4_set_quartz(root, quartz);
  839. if (ret < 0)
  840. goto err_unregister;
  841. pci_set_drvdata(pdev, ppriv);
  842. return ret;
  843. err_unregister:
  844. while (i-- > 0) {
  845. dscc4_release_ring(root + i);
  846. unregister_hdlc_device(dscc4_to_dev(root + i));
  847. }
  848. kfree(ppriv);
  849. i = dev_per_card;
  850. err_free_dev:
  851. while (i-- > 0)
  852. free_netdev(root[i].dev);
  853. kfree(root);
  854. err_out:
  855. return ret;
  856. };
  857. static void dscc4_tx_timeout(struct net_device *dev)
  858. {
  859. /* FIXME: something is missing there */
  860. }
  861. static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
  862. {
  863. sync_serial_settings *settings = &dpriv->settings;
  864. if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
  865. struct net_device *dev = dscc4_to_dev(dpriv);
  866. netdev_info(dev, "loopback requires clock\n");
  867. return -1;
  868. }
  869. return 0;
  870. }
  871. #ifdef CONFIG_DSCC4_PCI_RST
  872. /*
  873. * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
  874. * so as to provide a safe way to reset the asic while not the whole machine
  875. * rebooting.
  876. *
  877. * This code doesn't need to be efficient. Keep It Simple
  878. */
  879. static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
  880. {
  881. int i;
  882. mutex_lock(&dscc4_mutex);
  883. for (i = 0; i < 16; i++)
  884. pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
  885. /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
  886. writel(0x001c0000, ioaddr + GMODE);
  887. /* Configure GPIO port as output */
  888. writel(0x0000ffff, ioaddr + GPDIR);
  889. /* Disable interruption */
  890. writel(0x0000ffff, ioaddr + GPIM);
  891. writel(0x0000ffff, ioaddr + GPDATA);
  892. writel(0x00000000, ioaddr + GPDATA);
  893. /* Flush posted writes */
  894. readl(ioaddr + GSTAR);
  895. schedule_timeout_uninterruptible(msecs_to_jiffies(100));
  896. for (i = 0; i < 16; i++)
  897. pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
  898. mutex_unlock(&dscc4_mutex);
  899. }
  900. #else
  901. #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
  902. #endif /* CONFIG_DSCC4_PCI_RST */
  903. static int dscc4_open(struct net_device *dev)
  904. {
  905. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  906. int ret = -EAGAIN;
  907. if ((dscc4_loopback_check(dpriv) < 0))
  908. goto err;
  909. if ((ret = hdlc_open(dev)))
  910. goto err;
  911. /*
  912. * Due to various bugs, there is no way to reliably reset a
  913. * specific port (manufacturer's dependent special PCI #RST wiring
  914. * apart: it affects all ports). Thus the device goes in the best
  915. * silent mode possible at dscc4_close() time and simply claims to
  916. * be up if it's opened again. It still isn't possible to change
  917. * the HDLC configuration without rebooting but at least the ports
  918. * can be up/down ifconfig'ed without killing the host.
  919. */
  920. if (dpriv->flags & FakeReset) {
  921. dpriv->flags &= ~FakeReset;
  922. scc_patchl(0, PowerUp, dpriv, dev, CCR0);
  923. scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
  924. scc_writel(EventsMask, dpriv, dev, IMR);
  925. netdev_info(dev, "up again\n");
  926. goto done;
  927. }
  928. /* IDT+IDR during XPR */
  929. dpriv->flags = NeedIDR | NeedIDT;
  930. scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
  931. /*
  932. * The following is a bit paranoid...
  933. *
  934. * NB: the datasheet "...CEC will stay active if the SCC is in
  935. * power-down mode or..." and CCR2.RAC = 1 are two different
  936. * situations.
  937. */
  938. if (scc_readl_star(dpriv, dev) & SccBusy) {
  939. netdev_err(dev, "busy - try later\n");
  940. ret = -EAGAIN;
  941. goto err_out;
  942. } else
  943. netdev_info(dev, "available - good\n");
  944. scc_writel(EventsMask, dpriv, dev, IMR);
  945. /* Posted write is flushed in the wait_ack loop */
  946. scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
  947. if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
  948. goto err_disable_scc_events;
  949. /*
  950. * I would expect XPR near CE completion (before ? after ?).
  951. * At worst, this code won't see a late XPR and people
  952. * will have to re-issue an ifconfig (this is harmless).
  953. * WARNING, a really missing XPR usually means a hardware
  954. * reset is needed. Suggestions anyone ?
  955. */
  956. if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
  957. pr_err("XPR timeout\n");
  958. goto err_disable_scc_events;
  959. }
  960. if (debug > 2)
  961. dscc4_tx_print(dev, dpriv, "Open");
  962. done:
  963. netif_start_queue(dev);
  964. netif_carrier_on(dev);
  965. return 0;
  966. err_disable_scc_events:
  967. scc_writel(0xffffffff, dpriv, dev, IMR);
  968. scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
  969. err_out:
  970. hdlc_close(dev);
  971. err:
  972. return ret;
  973. }
  974. #ifdef DSCC4_POLLING
  975. static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
  976. {
  977. /* FIXME: it's gonna be easy (TM), for sure */
  978. }
  979. #endif /* DSCC4_POLLING */
  980. static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb,
  981. struct net_device *dev)
  982. {
  983. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  984. struct device *d = &dpriv->pci_priv->pdev->dev;
  985. struct TxFD *tx_fd;
  986. dma_addr_t addr;
  987. int next;
  988. addr = dma_map_single(d, skb->data, skb->len, DMA_TO_DEVICE);
  989. if (dma_mapping_error(d, addr)) {
  990. dev_kfree_skb_any(skb);
  991. dev->stats.tx_dropped++;
  992. return NETDEV_TX_OK;
  993. }
  994. next = dpriv->tx_current%TX_RING_SIZE;
  995. dpriv->tx_skbuff[next] = skb;
  996. tx_fd = dpriv->tx_fd + next;
  997. tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
  998. tx_fd->data = cpu_to_le32(addr);
  999. tx_fd->complete = 0x00000000;
  1000. tx_fd->jiffies = jiffies;
  1001. mb();
  1002. #ifdef DSCC4_POLLING
  1003. spin_lock(&dpriv->lock);
  1004. while (dscc4_tx_poll(dpriv, dev));
  1005. spin_unlock(&dpriv->lock);
  1006. #endif
  1007. if (debug > 2)
  1008. dscc4_tx_print(dev, dpriv, "Xmit");
  1009. /* To be cleaned(unsigned int)/optimized. Later, ok ? */
  1010. if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
  1011. netif_stop_queue(dev);
  1012. if (dscc4_tx_quiescent(dpriv, dev))
  1013. dscc4_do_tx(dpriv, dev);
  1014. return NETDEV_TX_OK;
  1015. }
  1016. static int dscc4_close(struct net_device *dev)
  1017. {
  1018. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  1019. netif_stop_queue(dev);
  1020. scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
  1021. scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
  1022. scc_writel(0xffffffff, dpriv, dev, IMR);
  1023. dpriv->flags |= FakeReset;
  1024. hdlc_close(dev);
  1025. return 0;
  1026. }
  1027. static inline int dscc4_check_clock_ability(int port)
  1028. {
  1029. int ret = 0;
  1030. #ifdef CONFIG_DSCC4_PCISYNC
  1031. if (port >= 2)
  1032. ret = -1;
  1033. #endif
  1034. return ret;
  1035. }
  1036. /*
  1037. * DS1 p.137: "There are a total of 13 different clocking modes..."
  1038. * ^^
  1039. * Design choices:
  1040. * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
  1041. * Clock mode 3b _should_ work but the testing seems to make this point
  1042. * dubious (DIY testing requires setting CCR0 at 0x00000033).
  1043. * This is supposed to provide least surprise "DTE like" behavior.
  1044. * - if line rate is specified, clocks are assumed to be locally generated.
  1045. * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
  1046. * between these it automagically done according on the required frequency
  1047. * scaling. Of course some rounding may take place.
  1048. * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
  1049. * appropriate external clocking device for testing.
  1050. * - no time-slot/clock mode 5: shameless laziness.
  1051. *
  1052. * The clock signals wiring can be (is ?) manufacturer dependent. Good luck.
  1053. *
  1054. * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
  1055. * won't pass the init sequence. For example, straight back-to-back DTE without
  1056. * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
  1057. * called.
  1058. *
  1059. * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
  1060. * DS0 for example)
  1061. *
  1062. * Clock mode related bits of CCR0:
  1063. * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
  1064. * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
  1065. * | | +-------- High Speed: say 0
  1066. * | | | +-+-+-- Clock Mode: 0..7
  1067. * | | | | | |
  1068. * -+-+-+-+-+-+-+-+
  1069. * x|x|5|4|3|2|1|0| lower bits
  1070. *
  1071. * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
  1072. * +-+-+-+------------------ M (0..15)
  1073. * | | | | +-+-+-+-+-+-- N (0..63)
  1074. * 0 0 0 0 | | | | 0 0 | | | | | |
  1075. * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  1076. * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
  1077. *
  1078. */
  1079. static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
  1080. {
  1081. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  1082. int ret = -1;
  1083. u32 brr;
  1084. *state &= ~Ccr0ClockMask;
  1085. if (*bps) { /* Clock generated - required for DCE */
  1086. u32 n = 0, m = 0, divider;
  1087. int xtal;
  1088. xtal = dpriv->pci_priv->xtal_hz;
  1089. if (!xtal)
  1090. goto done;
  1091. if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
  1092. goto done;
  1093. divider = xtal / *bps;
  1094. if (divider > BRR_DIVIDER_MAX) {
  1095. divider >>= 4;
  1096. *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
  1097. } else
  1098. *state |= 0x00000037; /* Clock mode 7b (BRG) */
  1099. if (divider >> 22) {
  1100. n = 63;
  1101. m = 15;
  1102. } else if (divider) {
  1103. /* Extraction of the 6 highest weighted bits */
  1104. m = 0;
  1105. while (0xffffffc0 & divider) {
  1106. m++;
  1107. divider >>= 1;
  1108. }
  1109. n = divider;
  1110. }
  1111. brr = (m << 8) | n;
  1112. divider = n << m;
  1113. if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
  1114. divider <<= 4;
  1115. *bps = xtal / divider;
  1116. } else {
  1117. /*
  1118. * External clock - DTE
  1119. * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
  1120. * Nothing more to be done
  1121. */
  1122. brr = 0;
  1123. }
  1124. scc_writel(brr, dpriv, dev, BRR);
  1125. ret = 0;
  1126. done:
  1127. return ret;
  1128. }
  1129. static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1130. {
  1131. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  1132. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  1133. const size_t size = sizeof(dpriv->settings);
  1134. int ret = 0;
  1135. if (dev->flags & IFF_UP)
  1136. return -EBUSY;
  1137. if (cmd != SIOCWANDEV)
  1138. return -EOPNOTSUPP;
  1139. switch(ifr->ifr_settings.type) {
  1140. case IF_GET_IFACE:
  1141. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  1142. if (ifr->ifr_settings.size < size) {
  1143. ifr->ifr_settings.size = size; /* data size wanted */
  1144. return -ENOBUFS;
  1145. }
  1146. if (copy_to_user(line, &dpriv->settings, size))
  1147. return -EFAULT;
  1148. break;
  1149. case IF_IFACE_SYNC_SERIAL:
  1150. if (!capable(CAP_NET_ADMIN))
  1151. return -EPERM;
  1152. if (dpriv->flags & FakeReset) {
  1153. netdev_info(dev, "please reset the device before this command\n");
  1154. return -EPERM;
  1155. }
  1156. if (copy_from_user(&dpriv->settings, line, size))
  1157. return -EFAULT;
  1158. ret = dscc4_set_iface(dpriv, dev);
  1159. break;
  1160. default:
  1161. ret = hdlc_ioctl(dev, ifr, cmd);
  1162. break;
  1163. }
  1164. return ret;
  1165. }
  1166. static int dscc4_match(const struct thingie *p, int value)
  1167. {
  1168. int i;
  1169. for (i = 0; p[i].define != -1; i++) {
  1170. if (value == p[i].define)
  1171. break;
  1172. }
  1173. if (p[i].define == -1)
  1174. return -1;
  1175. else
  1176. return i;
  1177. }
  1178. static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
  1179. struct net_device *dev)
  1180. {
  1181. sync_serial_settings *settings = &dpriv->settings;
  1182. int ret = -EOPNOTSUPP;
  1183. u32 bps, state;
  1184. bps = settings->clock_rate;
  1185. state = scc_readl(dpriv, CCR0);
  1186. if (dscc4_set_clock(dev, &bps, &state) < 0)
  1187. goto done;
  1188. if (bps) { /* DCE */
  1189. printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
  1190. if (settings->clock_rate != bps) {
  1191. printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
  1192. dev->name, settings->clock_rate, bps);
  1193. settings->clock_rate = bps;
  1194. }
  1195. } else { /* DTE */
  1196. state |= PowerUp | Vis;
  1197. printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
  1198. }
  1199. scc_writel(state, dpriv, dev, CCR0);
  1200. ret = 0;
  1201. done:
  1202. return ret;
  1203. }
  1204. static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
  1205. struct net_device *dev)
  1206. {
  1207. static const struct thingie encoding[] = {
  1208. { ENCODING_NRZ, 0x00000000 },
  1209. { ENCODING_NRZI, 0x00200000 },
  1210. { ENCODING_FM_MARK, 0x00400000 },
  1211. { ENCODING_FM_SPACE, 0x00500000 },
  1212. { ENCODING_MANCHESTER, 0x00600000 },
  1213. { -1, 0}
  1214. };
  1215. int i, ret = 0;
  1216. i = dscc4_match(encoding, dpriv->encoding);
  1217. if (i >= 0)
  1218. scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
  1219. else
  1220. ret = -EOPNOTSUPP;
  1221. return ret;
  1222. }
  1223. static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
  1224. struct net_device *dev)
  1225. {
  1226. sync_serial_settings *settings = &dpriv->settings;
  1227. u32 state;
  1228. state = scc_readl(dpriv, CCR1);
  1229. if (settings->loopback) {
  1230. printk(KERN_DEBUG "%s: loopback\n", dev->name);
  1231. state |= 0x00000100;
  1232. } else {
  1233. printk(KERN_DEBUG "%s: normal\n", dev->name);
  1234. state &= ~0x00000100;
  1235. }
  1236. scc_writel(state, dpriv, dev, CCR1);
  1237. return 0;
  1238. }
  1239. static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
  1240. struct net_device *dev)
  1241. {
  1242. static const struct thingie crc[] = {
  1243. { PARITY_CRC16_PR0_CCITT, 0x00000010 },
  1244. { PARITY_CRC16_PR1_CCITT, 0x00000000 },
  1245. { PARITY_CRC32_PR0_CCITT, 0x00000011 },
  1246. { PARITY_CRC32_PR1_CCITT, 0x00000001 }
  1247. };
  1248. int i, ret = 0;
  1249. i = dscc4_match(crc, dpriv->parity);
  1250. if (i >= 0)
  1251. scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
  1252. else
  1253. ret = -EOPNOTSUPP;
  1254. return ret;
  1255. }
  1256. static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
  1257. {
  1258. struct {
  1259. int (*action)(struct dscc4_dev_priv *, struct net_device *);
  1260. } *p, do_setting[] = {
  1261. { dscc4_encoding_setting },
  1262. { dscc4_clock_setting },
  1263. { dscc4_loopback_setting },
  1264. { dscc4_crc_setting },
  1265. { NULL }
  1266. };
  1267. int ret = 0;
  1268. for (p = do_setting; p->action; p++) {
  1269. if ((ret = p->action(dpriv, dev)) < 0)
  1270. break;
  1271. }
  1272. return ret;
  1273. }
  1274. static irqreturn_t dscc4_irq(int irq, void *token)
  1275. {
  1276. struct dscc4_dev_priv *root = token;
  1277. struct dscc4_pci_priv *priv;
  1278. struct net_device *dev;
  1279. void __iomem *ioaddr;
  1280. u32 state;
  1281. unsigned long flags;
  1282. int i, handled = 1;
  1283. priv = root->pci_priv;
  1284. dev = dscc4_to_dev(root);
  1285. spin_lock_irqsave(&priv->lock, flags);
  1286. ioaddr = root->base_addr;
  1287. state = readl(ioaddr + GSTAR);
  1288. if (!state) {
  1289. handled = 0;
  1290. goto out;
  1291. }
  1292. if (debug > 3)
  1293. printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
  1294. writel(state, ioaddr + GSTAR);
  1295. if (state & Arf) {
  1296. netdev_err(dev, "failure (Arf). Harass the maintainer\n");
  1297. goto out;
  1298. }
  1299. state &= ~ArAck;
  1300. if (state & Cfg) {
  1301. if (debug > 0)
  1302. printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
  1303. if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
  1304. netdev_err(dev, "CFG failed\n");
  1305. if (!(state &= ~Cfg))
  1306. goto out;
  1307. }
  1308. if (state & RxEvt) {
  1309. i = dev_per_card - 1;
  1310. do {
  1311. dscc4_rx_irq(priv, root + i);
  1312. } while (--i >= 0);
  1313. state &= ~RxEvt;
  1314. }
  1315. if (state & TxEvt) {
  1316. i = dev_per_card - 1;
  1317. do {
  1318. dscc4_tx_irq(priv, root + i);
  1319. } while (--i >= 0);
  1320. state &= ~TxEvt;
  1321. }
  1322. out:
  1323. spin_unlock_irqrestore(&priv->lock, flags);
  1324. return IRQ_RETVAL(handled);
  1325. }
  1326. static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
  1327. struct dscc4_dev_priv *dpriv)
  1328. {
  1329. struct net_device *dev = dscc4_to_dev(dpriv);
  1330. u32 state;
  1331. int cur, loop = 0;
  1332. try:
  1333. cur = dpriv->iqtx_current%IRQ_RING_SIZE;
  1334. state = le32_to_cpu(dpriv->iqtx[cur]);
  1335. if (!state) {
  1336. if (debug > 4)
  1337. printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
  1338. state);
  1339. if ((debug > 1) && (loop > 1))
  1340. printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
  1341. if (loop && netif_queue_stopped(dev))
  1342. if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
  1343. netif_wake_queue(dev);
  1344. if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
  1345. !dscc4_tx_done(dpriv))
  1346. dscc4_do_tx(dpriv, dev);
  1347. return;
  1348. }
  1349. loop++;
  1350. dpriv->iqtx[cur] = 0;
  1351. dpriv->iqtx_current++;
  1352. if (state_check(state, dpriv, dev, "Tx") < 0)
  1353. return;
  1354. if (state & SccEvt) {
  1355. if (state & Alls) {
  1356. struct sk_buff *skb;
  1357. struct TxFD *tx_fd;
  1358. if (debug > 2)
  1359. dscc4_tx_print(dev, dpriv, "Alls");
  1360. /*
  1361. * DataComplete can't be trusted for Tx completion.
  1362. * Cf errata DS5 p.8
  1363. */
  1364. cur = dpriv->tx_dirty%TX_RING_SIZE;
  1365. tx_fd = dpriv->tx_fd + cur;
  1366. skb = dpriv->tx_skbuff[cur];
  1367. if (skb) {
  1368. dma_unmap_single(&ppriv->pdev->dev,
  1369. le32_to_cpu(tx_fd->data),
  1370. skb->len, DMA_TO_DEVICE);
  1371. if (tx_fd->state & FrameEnd) {
  1372. dev->stats.tx_packets++;
  1373. dev->stats.tx_bytes += skb->len;
  1374. }
  1375. dev_kfree_skb_irq(skb);
  1376. dpriv->tx_skbuff[cur] = NULL;
  1377. ++dpriv->tx_dirty;
  1378. } else {
  1379. if (debug > 1)
  1380. netdev_err(dev, "Tx: NULL skb %d\n",
  1381. cur);
  1382. }
  1383. /*
  1384. * If the driver ends sending crap on the wire, it
  1385. * will be way easier to diagnose than the (not so)
  1386. * random freeze induced by null sized tx frames.
  1387. */
  1388. tx_fd->data = tx_fd->next;
  1389. tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
  1390. tx_fd->complete = 0x00000000;
  1391. tx_fd->jiffies = 0;
  1392. if (!(state &= ~Alls))
  1393. goto try;
  1394. }
  1395. /*
  1396. * Transmit Data Underrun
  1397. */
  1398. if (state & Xdu) {
  1399. netdev_err(dev, "Tx Data Underrun. Ask maintainer\n");
  1400. dpriv->flags = NeedIDT;
  1401. /* Tx reset */
  1402. writel(MTFi | Rdt,
  1403. dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
  1404. writel(Action, dpriv->base_addr + GCMDR);
  1405. return;
  1406. }
  1407. if (state & Cts) {
  1408. netdev_info(dev, "CTS transition\n");
  1409. if (!(state &= ~Cts)) /* DEBUG */
  1410. goto try;
  1411. }
  1412. if (state & Xmr) {
  1413. /* Frame needs to be sent again - FIXME */
  1414. netdev_err(dev, "Tx ReTx. Ask maintainer\n");
  1415. if (!(state &= ~Xmr)) /* DEBUG */
  1416. goto try;
  1417. }
  1418. if (state & Xpr) {
  1419. void __iomem *scc_addr;
  1420. unsigned long ring;
  1421. unsigned int i;
  1422. /*
  1423. * - the busy condition happens (sometimes);
  1424. * - it doesn't seem to make the handler unreliable.
  1425. */
  1426. for (i = 1; i; i <<= 1) {
  1427. if (!(scc_readl_star(dpriv, dev) & SccBusy))
  1428. break;
  1429. }
  1430. if (!i)
  1431. netdev_info(dev, "busy in irq\n");
  1432. scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
  1433. /* Keep this order: IDT before IDR */
  1434. if (dpriv->flags & NeedIDT) {
  1435. if (debug > 2)
  1436. dscc4_tx_print(dev, dpriv, "Xpr");
  1437. ring = dpriv->tx_fd_dma +
  1438. (dpriv->tx_dirty%TX_RING_SIZE)*
  1439. sizeof(struct TxFD);
  1440. writel(ring, scc_addr + CH0BTDA);
  1441. dscc4_do_tx(dpriv, dev);
  1442. writel(MTFi | Idt, scc_addr + CH0CFG);
  1443. if (dscc4_do_action(dev, "IDT") < 0)
  1444. goto err_xpr;
  1445. dpriv->flags &= ~NeedIDT;
  1446. }
  1447. if (dpriv->flags & NeedIDR) {
  1448. ring = dpriv->rx_fd_dma +
  1449. (dpriv->rx_current%RX_RING_SIZE)*
  1450. sizeof(struct RxFD);
  1451. writel(ring, scc_addr + CH0BRDA);
  1452. dscc4_rx_update(dpriv, dev);
  1453. writel(MTFi | Idr, scc_addr + CH0CFG);
  1454. if (dscc4_do_action(dev, "IDR") < 0)
  1455. goto err_xpr;
  1456. dpriv->flags &= ~NeedIDR;
  1457. smp_wmb();
  1458. /* Activate receiver and misc */
  1459. scc_writel(0x08050008, dpriv, dev, CCR2);
  1460. }
  1461. err_xpr:
  1462. if (!(state &= ~Xpr))
  1463. goto try;
  1464. }
  1465. if (state & Cd) {
  1466. if (debug > 0)
  1467. netdev_info(dev, "CD transition\n");
  1468. if (!(state &= ~Cd)) /* DEBUG */
  1469. goto try;
  1470. }
  1471. } else { /* ! SccEvt */
  1472. if (state & Hi) {
  1473. #ifdef DSCC4_POLLING
  1474. while (!dscc4_tx_poll(dpriv, dev));
  1475. #endif
  1476. netdev_info(dev, "Tx Hi\n");
  1477. state &= ~Hi;
  1478. }
  1479. if (state & Err) {
  1480. netdev_info(dev, "Tx ERR\n");
  1481. dev->stats.tx_errors++;
  1482. state &= ~Err;
  1483. }
  1484. }
  1485. goto try;
  1486. }
  1487. static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
  1488. struct dscc4_dev_priv *dpriv)
  1489. {
  1490. struct net_device *dev = dscc4_to_dev(dpriv);
  1491. u32 state;
  1492. int cur;
  1493. try:
  1494. cur = dpriv->iqrx_current%IRQ_RING_SIZE;
  1495. state = le32_to_cpu(dpriv->iqrx[cur]);
  1496. if (!state)
  1497. return;
  1498. dpriv->iqrx[cur] = 0;
  1499. dpriv->iqrx_current++;
  1500. if (state_check(state, dpriv, dev, "Rx") < 0)
  1501. return;
  1502. if (!(state & SccEvt)){
  1503. struct RxFD *rx_fd;
  1504. if (debug > 4)
  1505. printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
  1506. state);
  1507. state &= 0x00ffffff;
  1508. if (state & Err) { /* Hold or reset */
  1509. printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
  1510. cur = dpriv->rx_current%RX_RING_SIZE;
  1511. rx_fd = dpriv->rx_fd + cur;
  1512. /*
  1513. * Presume we're not facing a DMAC receiver reset.
  1514. * As We use the rx size-filtering feature of the
  1515. * DSCC4, the beginning of a new frame is waiting in
  1516. * the rx fifo. I bet a Receive Data Overflow will
  1517. * happen most of time but let's try and avoid it.
  1518. * Btw (as for RDO) if one experiences ERR whereas
  1519. * the system looks rather idle, there may be a
  1520. * problem with latency. In this case, increasing
  1521. * RX_RING_SIZE may help.
  1522. */
  1523. //while (dpriv->rx_needs_refill) {
  1524. while (!(rx_fd->state1 & Hold)) {
  1525. rx_fd++;
  1526. cur++;
  1527. if (!(cur = cur%RX_RING_SIZE))
  1528. rx_fd = dpriv->rx_fd;
  1529. }
  1530. //dpriv->rx_needs_refill--;
  1531. try_get_rx_skb(dpriv, dev);
  1532. if (!rx_fd->data)
  1533. goto try;
  1534. rx_fd->state1 &= ~Hold;
  1535. rx_fd->state2 = 0x00000000;
  1536. rx_fd->end = cpu_to_le32(0xbabeface);
  1537. //}
  1538. goto try;
  1539. }
  1540. if (state & Fi) {
  1541. dscc4_rx_skb(dpriv, dev);
  1542. goto try;
  1543. }
  1544. if (state & Hi ) { /* HI bit */
  1545. netdev_info(dev, "Rx Hi\n");
  1546. state &= ~Hi;
  1547. goto try;
  1548. }
  1549. } else { /* SccEvt */
  1550. if (debug > 1) {
  1551. //FIXME: verifier la presence de tous les evenements
  1552. static struct {
  1553. u32 mask;
  1554. const char *irq_name;
  1555. } evts[] = {
  1556. { 0x00008000, "TIN"},
  1557. { 0x00000020, "RSC"},
  1558. { 0x00000010, "PCE"},
  1559. { 0x00000008, "PLLA"},
  1560. { 0, NULL}
  1561. }, *evt;
  1562. for (evt = evts; evt->irq_name; evt++) {
  1563. if (state & evt->mask) {
  1564. printk(KERN_DEBUG "%s: %s\n",
  1565. dev->name, evt->irq_name);
  1566. if (!(state &= ~evt->mask))
  1567. goto try;
  1568. }
  1569. }
  1570. } else {
  1571. if (!(state &= ~0x0000c03c))
  1572. goto try;
  1573. }
  1574. if (state & Cts) {
  1575. netdev_info(dev, "CTS transition\n");
  1576. if (!(state &= ~Cts)) /* DEBUG */
  1577. goto try;
  1578. }
  1579. /*
  1580. * Receive Data Overflow (FIXME: fscked)
  1581. */
  1582. if (state & Rdo) {
  1583. struct RxFD *rx_fd;
  1584. void __iomem *scc_addr;
  1585. int cur;
  1586. //if (debug)
  1587. // dscc4_rx_dump(dpriv);
  1588. scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
  1589. scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
  1590. /*
  1591. * This has no effect. Why ?
  1592. * ORed with TxSccRes, one sees the CFG ack (for
  1593. * the TX part only).
  1594. */
  1595. scc_writel(RxSccRes, dpriv, dev, CMDR);
  1596. dpriv->flags |= RdoSet;
  1597. /*
  1598. * Let's try and save something in the received data.
  1599. * rx_current must be incremented at least once to
  1600. * avoid HOLD in the BRDA-to-be-pointed desc.
  1601. */
  1602. do {
  1603. cur = dpriv->rx_current++%RX_RING_SIZE;
  1604. rx_fd = dpriv->rx_fd + cur;
  1605. if (!(rx_fd->state2 & DataComplete))
  1606. break;
  1607. if (rx_fd->state2 & FrameAborted) {
  1608. dev->stats.rx_over_errors++;
  1609. rx_fd->state1 |= Hold;
  1610. rx_fd->state2 = 0x00000000;
  1611. rx_fd->end = cpu_to_le32(0xbabeface);
  1612. } else
  1613. dscc4_rx_skb(dpriv, dev);
  1614. } while (1);
  1615. if (debug > 0) {
  1616. if (dpriv->flags & RdoSet)
  1617. printk(KERN_DEBUG
  1618. "%s: no RDO in Rx data\n", DRV_NAME);
  1619. }
  1620. #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
  1621. /*
  1622. * FIXME: must the reset be this violent ?
  1623. */
  1624. #warning "FIXME: CH0BRDA"
  1625. writel(dpriv->rx_fd_dma +
  1626. (dpriv->rx_current%RX_RING_SIZE)*
  1627. sizeof(struct RxFD), scc_addr + CH0BRDA);
  1628. writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
  1629. if (dscc4_do_action(dev, "RDR") < 0) {
  1630. netdev_err(dev, "RDO recovery failed(RDR)\n");
  1631. goto rdo_end;
  1632. }
  1633. writel(MTFi|Idr, scc_addr + CH0CFG);
  1634. if (dscc4_do_action(dev, "IDR") < 0) {
  1635. netdev_err(dev, "RDO recovery failed(IDR)\n");
  1636. goto rdo_end;
  1637. }
  1638. rdo_end:
  1639. #endif
  1640. scc_patchl(0, RxActivate, dpriv, dev, CCR2);
  1641. goto try;
  1642. }
  1643. if (state & Cd) {
  1644. netdev_info(dev, "CD transition\n");
  1645. if (!(state &= ~Cd)) /* DEBUG */
  1646. goto try;
  1647. }
  1648. if (state & Flex) {
  1649. printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
  1650. if (!(state &= ~Flex))
  1651. goto try;
  1652. }
  1653. }
  1654. }
  1655. /*
  1656. * I had expected the following to work for the first descriptor
  1657. * (tx_fd->state = 0xc0000000)
  1658. * - Hold=1 (don't try and branch to the next descripto);
  1659. * - No=0 (I want an empty data section, i.e. size=0);
  1660. * - Fe=1 (required by No=0 or we got an Err irq and must reset).
  1661. * It failed and locked solid. Thus the introduction of a dummy skb.
  1662. * Problem is acknowledged in errata sheet DS5. Joy :o/
  1663. */
  1664. static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
  1665. {
  1666. struct sk_buff *skb;
  1667. skb = dev_alloc_skb(DUMMY_SKB_SIZE);
  1668. if (skb) {
  1669. struct device *d = &dpriv->pci_priv->pdev->dev;
  1670. int last = dpriv->tx_dirty%TX_RING_SIZE;
  1671. struct TxFD *tx_fd = dpriv->tx_fd + last;
  1672. dma_addr_t addr;
  1673. skb->len = DUMMY_SKB_SIZE;
  1674. skb_copy_to_linear_data(skb, version,
  1675. strlen(version) % DUMMY_SKB_SIZE);
  1676. addr = dma_map_single(d, skb->data, DUMMY_SKB_SIZE,
  1677. DMA_TO_DEVICE);
  1678. if (dma_mapping_error(d, addr)) {
  1679. dev_kfree_skb_any(skb);
  1680. return NULL;
  1681. }
  1682. tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
  1683. tx_fd->data = cpu_to_le32(addr);
  1684. dpriv->tx_skbuff[last] = skb;
  1685. }
  1686. return skb;
  1687. }
  1688. static int dscc4_init_ring(struct net_device *dev)
  1689. {
  1690. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  1691. struct device *d = &dpriv->pci_priv->pdev->dev;
  1692. struct TxFD *tx_fd;
  1693. struct RxFD *rx_fd;
  1694. void *ring;
  1695. int i;
  1696. ring = dma_alloc_coherent(d, RX_TOTAL_SIZE, &dpriv->rx_fd_dma,
  1697. GFP_KERNEL);
  1698. if (!ring)
  1699. goto err_out;
  1700. dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
  1701. ring = dma_alloc_coherent(d, TX_TOTAL_SIZE, &dpriv->tx_fd_dma,
  1702. GFP_KERNEL);
  1703. if (!ring)
  1704. goto err_free_dma_rx;
  1705. dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
  1706. memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
  1707. dpriv->tx_dirty = 0xffffffff;
  1708. i = dpriv->tx_current = 0;
  1709. do {
  1710. tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
  1711. tx_fd->complete = 0x00000000;
  1712. /* FIXME: NULL should be ok - to be tried */
  1713. tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
  1714. (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
  1715. (++i%TX_RING_SIZE)*sizeof(*tx_fd));
  1716. } while (i < TX_RING_SIZE);
  1717. if (!dscc4_init_dummy_skb(dpriv))
  1718. goto err_free_dma_tx;
  1719. memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
  1720. i = dpriv->rx_dirty = dpriv->rx_current = 0;
  1721. do {
  1722. /* size set by the host. Multiple of 4 bytes please */
  1723. rx_fd->state1 = HiDesc;
  1724. rx_fd->state2 = 0x00000000;
  1725. rx_fd->end = cpu_to_le32(0xbabeface);
  1726. rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
  1727. // FIXME: return value verifiee mais traitement suspect
  1728. if (try_get_rx_skb(dpriv, dev) >= 0)
  1729. dpriv->rx_dirty++;
  1730. (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
  1731. (++i%RX_RING_SIZE)*sizeof(*rx_fd));
  1732. } while (i < RX_RING_SIZE);
  1733. return 0;
  1734. err_free_dma_tx:
  1735. dma_free_coherent(d, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
  1736. err_free_dma_rx:
  1737. dma_free_coherent(d, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
  1738. err_out:
  1739. return -ENOMEM;
  1740. }
  1741. static void dscc4_remove_one(struct pci_dev *pdev)
  1742. {
  1743. struct dscc4_pci_priv *ppriv;
  1744. struct dscc4_dev_priv *root;
  1745. void __iomem *ioaddr;
  1746. int i;
  1747. ppriv = pci_get_drvdata(pdev);
  1748. root = ppriv->root;
  1749. ioaddr = root->base_addr;
  1750. dscc4_pci_reset(pdev, ioaddr);
  1751. free_irq(pdev->irq, root);
  1752. dma_free_coherent(&pdev->dev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
  1753. ppriv->iqcfg_dma);
  1754. for (i = 0; i < dev_per_card; i++) {
  1755. struct dscc4_dev_priv *dpriv = root + i;
  1756. dscc4_release_ring(dpriv);
  1757. dma_free_coherent(&pdev->dev, IRQ_RING_SIZE*sizeof(u32),
  1758. dpriv->iqrx, dpriv->iqrx_dma);
  1759. dma_free_coherent(&pdev->dev, IRQ_RING_SIZE*sizeof(u32),
  1760. dpriv->iqtx, dpriv->iqtx_dma);
  1761. }
  1762. dscc4_free1(pdev);
  1763. iounmap(ioaddr);
  1764. pci_release_region(pdev, 1);
  1765. pci_release_region(pdev, 0);
  1766. pci_disable_device(pdev);
  1767. }
  1768. static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
  1769. unsigned short parity)
  1770. {
  1771. struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
  1772. if (encoding != ENCODING_NRZ &&
  1773. encoding != ENCODING_NRZI &&
  1774. encoding != ENCODING_FM_MARK &&
  1775. encoding != ENCODING_FM_SPACE &&
  1776. encoding != ENCODING_MANCHESTER)
  1777. return -EINVAL;
  1778. if (parity != PARITY_NONE &&
  1779. parity != PARITY_CRC16_PR0_CCITT &&
  1780. parity != PARITY_CRC16_PR1_CCITT &&
  1781. parity != PARITY_CRC32_PR0_CCITT &&
  1782. parity != PARITY_CRC32_PR1_CCITT)
  1783. return -EINVAL;
  1784. dpriv->encoding = encoding;
  1785. dpriv->parity = parity;
  1786. return 0;
  1787. }
  1788. #ifndef MODULE
  1789. static int __init dscc4_setup(char *str)
  1790. {
  1791. int *args[] = { &debug, &quartz, NULL }, **p = args;
  1792. while (*p && (get_option(&str, *p) == 2))
  1793. p++;
  1794. return 1;
  1795. }
  1796. __setup("dscc4.setup=", dscc4_setup);
  1797. #endif
  1798. static const struct pci_device_id dscc4_pci_tbl[] = {
  1799. { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
  1800. PCI_ANY_ID, PCI_ANY_ID, },
  1801. { 0,}
  1802. };
  1803. MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
  1804. static struct pci_driver dscc4_driver = {
  1805. .name = DRV_NAME,
  1806. .id_table = dscc4_pci_tbl,
  1807. .probe = dscc4_init_one,
  1808. .remove = dscc4_remove_one,
  1809. };
  1810. module_pci_driver(dscc4_driver);