main.c 49 KB

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  1. /*
  2. * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/moduleparam.h>
  18. #include <linux/if_arp.h>
  19. #include <linux/etherdevice.h>
  20. #include "wil6210.h"
  21. #include "txrx.h"
  22. #include "txrx_edma.h"
  23. #include "wmi.h"
  24. #include "boot_loader.h"
  25. #define WAIT_FOR_HALP_VOTE_MS 100
  26. #define WAIT_FOR_SCAN_ABORT_MS 1000
  27. #define WIL_DEFAULT_NUM_RX_STATUS_RINGS 1
  28. #define WIL_BOARD_FILE_MAX_NAMELEN 128
  29. bool debug_fw; /* = false; */
  30. module_param(debug_fw, bool, 0444);
  31. MODULE_PARM_DESC(debug_fw, " do not perform card reset. For FW debug");
  32. static u8 oob_mode;
  33. module_param(oob_mode, byte, 0444);
  34. MODULE_PARM_DESC(oob_mode,
  35. " enable out of the box (OOB) mode in FW, for diagnostics and certification");
  36. bool no_fw_recovery;
  37. module_param(no_fw_recovery, bool, 0644);
  38. MODULE_PARM_DESC(no_fw_recovery, " disable automatic FW error recovery");
  39. /* if not set via modparam, will be set to default value of 1/8 of
  40. * rx ring size during init flow
  41. */
  42. unsigned short rx_ring_overflow_thrsh = WIL6210_RX_HIGH_TRSH_INIT;
  43. module_param(rx_ring_overflow_thrsh, ushort, 0444);
  44. MODULE_PARM_DESC(rx_ring_overflow_thrsh,
  45. " RX ring overflow threshold in descriptors.");
  46. /* We allow allocation of more than 1 page buffers to support large packets.
  47. * It is suboptimal behavior performance wise in case MTU above page size.
  48. */
  49. unsigned int mtu_max = TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD;
  50. static int mtu_max_set(const char *val, const struct kernel_param *kp)
  51. {
  52. int ret;
  53. /* sets mtu_max directly. no need to restore it in case of
  54. * illegal value since we assume this will fail insmod
  55. */
  56. ret = param_set_uint(val, kp);
  57. if (ret)
  58. return ret;
  59. if (mtu_max < 68 || mtu_max > WIL_MAX_ETH_MTU)
  60. ret = -EINVAL;
  61. return ret;
  62. }
  63. static const struct kernel_param_ops mtu_max_ops = {
  64. .set = mtu_max_set,
  65. .get = param_get_uint,
  66. };
  67. module_param_cb(mtu_max, &mtu_max_ops, &mtu_max, 0444);
  68. MODULE_PARM_DESC(mtu_max, " Max MTU value.");
  69. static uint rx_ring_order = WIL_RX_RING_SIZE_ORDER_DEFAULT;
  70. static uint tx_ring_order = WIL_TX_RING_SIZE_ORDER_DEFAULT;
  71. static uint bcast_ring_order = WIL_BCAST_RING_SIZE_ORDER_DEFAULT;
  72. static int ring_order_set(const char *val, const struct kernel_param *kp)
  73. {
  74. int ret;
  75. uint x;
  76. ret = kstrtouint(val, 0, &x);
  77. if (ret)
  78. return ret;
  79. if ((x < WIL_RING_SIZE_ORDER_MIN) || (x > WIL_RING_SIZE_ORDER_MAX))
  80. return -EINVAL;
  81. *((uint *)kp->arg) = x;
  82. return 0;
  83. }
  84. static const struct kernel_param_ops ring_order_ops = {
  85. .set = ring_order_set,
  86. .get = param_get_uint,
  87. };
  88. module_param_cb(rx_ring_order, &ring_order_ops, &rx_ring_order, 0444);
  89. MODULE_PARM_DESC(rx_ring_order, " Rx ring order; size = 1 << order");
  90. module_param_cb(tx_ring_order, &ring_order_ops, &tx_ring_order, 0444);
  91. MODULE_PARM_DESC(tx_ring_order, " Tx ring order; size = 1 << order");
  92. module_param_cb(bcast_ring_order, &ring_order_ops, &bcast_ring_order, 0444);
  93. MODULE_PARM_DESC(bcast_ring_order, " Bcast ring order; size = 1 << order");
  94. enum {
  95. WIL_BOOT_ERR,
  96. WIL_BOOT_VANILLA,
  97. WIL_BOOT_PRODUCTION,
  98. WIL_BOOT_DEVELOPMENT,
  99. };
  100. enum {
  101. WIL_SIG_STATUS_VANILLA = 0x0,
  102. WIL_SIG_STATUS_DEVELOPMENT = 0x1,
  103. WIL_SIG_STATUS_PRODUCTION = 0x2,
  104. WIL_SIG_STATUS_CORRUPTED_PRODUCTION = 0x3,
  105. };
  106. #define RST_DELAY (20) /* msec, for loop in @wil_wait_device_ready */
  107. #define RST_COUNT (1 + 1000/RST_DELAY) /* round up to be above 1 sec total */
  108. #define PMU_READY_DELAY_MS (4) /* ms, for sleep in @wil_wait_device_ready */
  109. #define OTP_HW_DELAY (200) /* usec, loop in @wil_wait_device_ready_talyn_mb */
  110. /* round up to be above 2 ms total */
  111. #define OTP_HW_COUNT (1 + 2000 / OTP_HW_DELAY)
  112. /*
  113. * Due to a hardware issue,
  114. * one has to read/write to/from NIC in 32-bit chunks;
  115. * regular memcpy_fromio and siblings will
  116. * not work on 64-bit platform - it uses 64-bit transactions
  117. *
  118. * Force 32-bit transactions to enable NIC on 64-bit platforms
  119. *
  120. * To avoid byte swap on big endian host, __raw_{read|write}l
  121. * should be used - {read|write}l would swap bytes to provide
  122. * little endian on PCI value in host endianness.
  123. */
  124. void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
  125. size_t count)
  126. {
  127. u32 *d = dst;
  128. const volatile u32 __iomem *s = src;
  129. for (; count >= 4; count -= 4)
  130. *d++ = __raw_readl(s++);
  131. if (unlikely(count)) {
  132. /* count can be 1..3 */
  133. u32 tmp = __raw_readl(s);
  134. memcpy(d, &tmp, count);
  135. }
  136. }
  137. void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
  138. size_t count)
  139. {
  140. volatile u32 __iomem *d = dst;
  141. const u32 *s = src;
  142. for (; count >= 4; count -= 4)
  143. __raw_writel(*s++, d++);
  144. if (unlikely(count)) {
  145. /* count can be 1..3 */
  146. u32 tmp = 0;
  147. memcpy(&tmp, s, count);
  148. __raw_writel(tmp, d);
  149. }
  150. }
  151. static void wil_ring_fini_tx(struct wil6210_priv *wil, int id)
  152. {
  153. struct wil_ring *ring = &wil->ring_tx[id];
  154. struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id];
  155. lockdep_assert_held(&wil->mutex);
  156. if (!ring->va)
  157. return;
  158. wil_dbg_misc(wil, "vring_fini_tx: id=%d\n", id);
  159. spin_lock_bh(&txdata->lock);
  160. txdata->dot1x_open = false;
  161. txdata->mid = U8_MAX;
  162. txdata->enabled = 0; /* no Tx can be in progress or start anew */
  163. spin_unlock_bh(&txdata->lock);
  164. /* napi_synchronize waits for completion of the current NAPI but will
  165. * not prevent the next NAPI run.
  166. * Add a memory barrier to guarantee that txdata->enabled is zeroed
  167. * before napi_synchronize so that the next scheduled NAPI will not
  168. * handle this vring
  169. */
  170. wmb();
  171. /* make sure NAPI won't touch this vring */
  172. if (test_bit(wil_status_napi_en, wil->status))
  173. napi_synchronize(&wil->napi_tx);
  174. wil->txrx_ops.ring_fini_tx(wil, ring);
  175. }
  176. static void wil_disconnect_cid(struct wil6210_vif *vif, int cid,
  177. u16 reason_code, bool from_event)
  178. __acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock)
  179. {
  180. uint i;
  181. struct wil6210_priv *wil = vif_to_wil(vif);
  182. struct net_device *ndev = vif_to_ndev(vif);
  183. struct wireless_dev *wdev = vif_to_wdev(vif);
  184. struct wil_sta_info *sta = &wil->sta[cid];
  185. int min_ring_id = wil_get_min_tx_ring_id(wil);
  186. might_sleep();
  187. wil_dbg_misc(wil, "disconnect_cid: CID %d, MID %d, status %d\n",
  188. cid, sta->mid, sta->status);
  189. /* inform upper/lower layers */
  190. if (sta->status != wil_sta_unused) {
  191. if (vif->mid != sta->mid) {
  192. wil_err(wil, "STA MID mismatch with VIF MID(%d)\n",
  193. vif->mid);
  194. /* let FW override sta->mid but be more strict with
  195. * user space requests
  196. */
  197. if (!from_event)
  198. return;
  199. }
  200. if (!from_event) {
  201. bool del_sta = (wdev->iftype == NL80211_IFTYPE_AP) ?
  202. disable_ap_sme : false;
  203. wmi_disconnect_sta(vif, sta->addr, reason_code,
  204. true, del_sta);
  205. }
  206. switch (wdev->iftype) {
  207. case NL80211_IFTYPE_AP:
  208. case NL80211_IFTYPE_P2P_GO:
  209. /* AP-like interface */
  210. cfg80211_del_sta(ndev, sta->addr, GFP_KERNEL);
  211. break;
  212. default:
  213. break;
  214. }
  215. sta->status = wil_sta_unused;
  216. sta->mid = U8_MAX;
  217. }
  218. /* reorder buffers */
  219. for (i = 0; i < WIL_STA_TID_NUM; i++) {
  220. struct wil_tid_ampdu_rx *r;
  221. spin_lock_bh(&sta->tid_rx_lock);
  222. r = sta->tid_rx[i];
  223. sta->tid_rx[i] = NULL;
  224. wil_tid_ampdu_rx_free(wil, r);
  225. spin_unlock_bh(&sta->tid_rx_lock);
  226. }
  227. /* crypto context */
  228. memset(sta->tid_crypto_rx, 0, sizeof(sta->tid_crypto_rx));
  229. memset(&sta->group_crypto_rx, 0, sizeof(sta->group_crypto_rx));
  230. /* release vrings */
  231. for (i = min_ring_id; i < ARRAY_SIZE(wil->ring_tx); i++) {
  232. if (wil->ring2cid_tid[i][0] == cid)
  233. wil_ring_fini_tx(wil, i);
  234. }
  235. /* statistics */
  236. memset(&sta->stats, 0, sizeof(sta->stats));
  237. sta->stats.tx_latency_min_us = U32_MAX;
  238. }
  239. static bool wil_vif_is_connected(struct wil6210_priv *wil, u8 mid)
  240. {
  241. int i;
  242. for (i = 0; i < ARRAY_SIZE(wil->sta); i++) {
  243. if (wil->sta[i].mid == mid &&
  244. wil->sta[i].status == wil_sta_connected)
  245. return true;
  246. }
  247. return false;
  248. }
  249. static void _wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid,
  250. u16 reason_code, bool from_event)
  251. {
  252. struct wil6210_priv *wil = vif_to_wil(vif);
  253. int cid = -ENOENT;
  254. struct net_device *ndev;
  255. struct wireless_dev *wdev;
  256. if (unlikely(!vif))
  257. return;
  258. ndev = vif_to_ndev(vif);
  259. wdev = vif_to_wdev(vif);
  260. might_sleep();
  261. wil_info(wil, "bssid=%pM, reason=%d, ev%s\n", bssid,
  262. reason_code, from_event ? "+" : "-");
  263. /* Cases are:
  264. * - disconnect single STA, still connected
  265. * - disconnect single STA, already disconnected
  266. * - disconnect all
  267. *
  268. * For "disconnect all", there are 3 options:
  269. * - bssid == NULL
  270. * - bssid is broadcast address (ff:ff:ff:ff:ff:ff)
  271. * - bssid is our MAC address
  272. */
  273. if (bssid && !is_broadcast_ether_addr(bssid) &&
  274. !ether_addr_equal_unaligned(ndev->dev_addr, bssid)) {
  275. cid = wil_find_cid(wil, vif->mid, bssid);
  276. wil_dbg_misc(wil, "Disconnect %pM, CID=%d, reason=%d\n",
  277. bssid, cid, reason_code);
  278. if (cid >= 0) /* disconnect 1 peer */
  279. wil_disconnect_cid(vif, cid, reason_code, from_event);
  280. } else { /* all */
  281. wil_dbg_misc(wil, "Disconnect all\n");
  282. for (cid = 0; cid < WIL6210_MAX_CID; cid++)
  283. wil_disconnect_cid(vif, cid, reason_code, from_event);
  284. }
  285. /* link state */
  286. switch (wdev->iftype) {
  287. case NL80211_IFTYPE_STATION:
  288. case NL80211_IFTYPE_P2P_CLIENT:
  289. wil_bcast_fini(vif);
  290. wil_update_net_queues_bh(wil, vif, NULL, true);
  291. netif_carrier_off(ndev);
  292. if (!wil_has_other_active_ifaces(wil, ndev, false, true))
  293. wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
  294. if (test_and_clear_bit(wil_vif_fwconnected, vif->status)) {
  295. atomic_dec(&wil->connected_vifs);
  296. cfg80211_disconnected(ndev, reason_code,
  297. NULL, 0,
  298. vif->locally_generated_disc,
  299. GFP_KERNEL);
  300. vif->locally_generated_disc = false;
  301. } else if (test_bit(wil_vif_fwconnecting, vif->status)) {
  302. cfg80211_connect_result(ndev, bssid, NULL, 0, NULL, 0,
  303. WLAN_STATUS_UNSPECIFIED_FAILURE,
  304. GFP_KERNEL);
  305. vif->bss = NULL;
  306. }
  307. clear_bit(wil_vif_fwconnecting, vif->status);
  308. break;
  309. case NL80211_IFTYPE_AP:
  310. case NL80211_IFTYPE_P2P_GO:
  311. if (!wil_vif_is_connected(wil, vif->mid)) {
  312. wil_update_net_queues_bh(wil, vif, NULL, true);
  313. if (test_and_clear_bit(wil_vif_fwconnected,
  314. vif->status))
  315. atomic_dec(&wil->connected_vifs);
  316. } else {
  317. wil_update_net_queues_bh(wil, vif, NULL, false);
  318. }
  319. break;
  320. default:
  321. break;
  322. }
  323. }
  324. void wil_disconnect_worker(struct work_struct *work)
  325. {
  326. struct wil6210_vif *vif = container_of(work,
  327. struct wil6210_vif, disconnect_worker);
  328. struct wil6210_priv *wil = vif_to_wil(vif);
  329. struct net_device *ndev = vif_to_ndev(vif);
  330. int rc;
  331. struct {
  332. struct wmi_cmd_hdr wmi;
  333. struct wmi_disconnect_event evt;
  334. } __packed reply;
  335. if (test_bit(wil_vif_fwconnected, vif->status))
  336. /* connect succeeded after all */
  337. return;
  338. if (!test_bit(wil_vif_fwconnecting, vif->status))
  339. /* already disconnected */
  340. return;
  341. memset(&reply, 0, sizeof(reply));
  342. rc = wmi_call(wil, WMI_DISCONNECT_CMDID, vif->mid, NULL, 0,
  343. WMI_DISCONNECT_EVENTID, &reply, sizeof(reply),
  344. WIL6210_DISCONNECT_TO_MS);
  345. if (rc) {
  346. wil_err(wil, "disconnect error %d\n", rc);
  347. return;
  348. }
  349. wil_update_net_queues_bh(wil, vif, NULL, true);
  350. netif_carrier_off(ndev);
  351. cfg80211_connect_result(ndev, NULL, NULL, 0, NULL, 0,
  352. WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_KERNEL);
  353. clear_bit(wil_vif_fwconnecting, vif->status);
  354. }
  355. static int wil_wait_for_recovery(struct wil6210_priv *wil)
  356. {
  357. if (wait_event_interruptible(wil->wq, wil->recovery_state !=
  358. fw_recovery_pending)) {
  359. wil_err(wil, "Interrupt, canceling recovery\n");
  360. return -ERESTARTSYS;
  361. }
  362. if (wil->recovery_state != fw_recovery_running) {
  363. wil_info(wil, "Recovery cancelled\n");
  364. return -EINTR;
  365. }
  366. wil_info(wil, "Proceed with recovery\n");
  367. return 0;
  368. }
  369. void wil_set_recovery_state(struct wil6210_priv *wil, int state)
  370. {
  371. wil_dbg_misc(wil, "set_recovery_state: %d -> %d\n",
  372. wil->recovery_state, state);
  373. wil->recovery_state = state;
  374. wake_up_interruptible(&wil->wq);
  375. }
  376. bool wil_is_recovery_blocked(struct wil6210_priv *wil)
  377. {
  378. return no_fw_recovery && (wil->recovery_state == fw_recovery_pending);
  379. }
  380. static void wil_fw_error_worker(struct work_struct *work)
  381. {
  382. struct wil6210_priv *wil = container_of(work, struct wil6210_priv,
  383. fw_error_worker);
  384. struct net_device *ndev = wil->main_ndev;
  385. struct wireless_dev *wdev;
  386. wil_dbg_misc(wil, "fw error worker\n");
  387. if (!ndev || !(ndev->flags & IFF_UP)) {
  388. wil_info(wil, "No recovery - interface is down\n");
  389. return;
  390. }
  391. wdev = ndev->ieee80211_ptr;
  392. /* increment @recovery_count if less then WIL6210_FW_RECOVERY_TO
  393. * passed since last recovery attempt
  394. */
  395. if (time_is_after_jiffies(wil->last_fw_recovery +
  396. WIL6210_FW_RECOVERY_TO))
  397. wil->recovery_count++;
  398. else
  399. wil->recovery_count = 1; /* fw was alive for a long time */
  400. if (wil->recovery_count > WIL6210_FW_RECOVERY_RETRIES) {
  401. wil_err(wil, "too many recovery attempts (%d), giving up\n",
  402. wil->recovery_count);
  403. return;
  404. }
  405. wil->last_fw_recovery = jiffies;
  406. wil_info(wil, "fw error recovery requested (try %d)...\n",
  407. wil->recovery_count);
  408. if (!no_fw_recovery)
  409. wil->recovery_state = fw_recovery_running;
  410. if (wil_wait_for_recovery(wil) != 0)
  411. return;
  412. mutex_lock(&wil->mutex);
  413. /* Needs adaptation for multiple VIFs
  414. * need to go over all VIFs and consider the appropriate
  415. * recovery.
  416. */
  417. switch (wdev->iftype) {
  418. case NL80211_IFTYPE_STATION:
  419. case NL80211_IFTYPE_P2P_CLIENT:
  420. case NL80211_IFTYPE_MONITOR:
  421. /* silent recovery, upper layers will see disconnect */
  422. __wil_down(wil);
  423. __wil_up(wil);
  424. break;
  425. case NL80211_IFTYPE_AP:
  426. case NL80211_IFTYPE_P2P_GO:
  427. wil_info(wil, "No recovery for AP-like interface\n");
  428. /* recovery in these modes is done by upper layers */
  429. break;
  430. default:
  431. wil_err(wil, "No recovery - unknown interface type %d\n",
  432. wdev->iftype);
  433. break;
  434. }
  435. mutex_unlock(&wil->mutex);
  436. }
  437. static int wil_find_free_ring(struct wil6210_priv *wil)
  438. {
  439. int i;
  440. int min_ring_id = wil_get_min_tx_ring_id(wil);
  441. for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) {
  442. if (!wil->ring_tx[i].va)
  443. return i;
  444. }
  445. return -EINVAL;
  446. }
  447. int wil_ring_init_tx(struct wil6210_vif *vif, int cid)
  448. {
  449. struct wil6210_priv *wil = vif_to_wil(vif);
  450. int rc = -EINVAL, ringid;
  451. if (cid < 0) {
  452. wil_err(wil, "No connection pending\n");
  453. goto out;
  454. }
  455. ringid = wil_find_free_ring(wil);
  456. if (ringid < 0) {
  457. wil_err(wil, "No free vring found\n");
  458. goto out;
  459. }
  460. wil_dbg_wmi(wil, "Configure for connection CID %d MID %d ring %d\n",
  461. cid, vif->mid, ringid);
  462. rc = wil->txrx_ops.ring_init_tx(vif, ringid, 1 << tx_ring_order,
  463. cid, 0);
  464. if (rc)
  465. wil_err(wil, "init TX for CID %d MID %d vring %d failed\n",
  466. cid, vif->mid, ringid);
  467. out:
  468. return rc;
  469. }
  470. int wil_bcast_init(struct wil6210_vif *vif)
  471. {
  472. struct wil6210_priv *wil = vif_to_wil(vif);
  473. int ri = vif->bcast_ring, rc;
  474. if (ri >= 0 && wil->ring_tx[ri].va)
  475. return 0;
  476. ri = wil_find_free_ring(wil);
  477. if (ri < 0)
  478. return ri;
  479. vif->bcast_ring = ri;
  480. rc = wil->txrx_ops.ring_init_bcast(vif, ri, 1 << bcast_ring_order);
  481. if (rc)
  482. vif->bcast_ring = -1;
  483. return rc;
  484. }
  485. void wil_bcast_fini(struct wil6210_vif *vif)
  486. {
  487. struct wil6210_priv *wil = vif_to_wil(vif);
  488. int ri = vif->bcast_ring;
  489. if (ri < 0)
  490. return;
  491. vif->bcast_ring = -1;
  492. wil_ring_fini_tx(wil, ri);
  493. }
  494. void wil_bcast_fini_all(struct wil6210_priv *wil)
  495. {
  496. int i;
  497. struct wil6210_vif *vif;
  498. for (i = 0; i < wil->max_vifs; i++) {
  499. vif = wil->vifs[i];
  500. if (vif)
  501. wil_bcast_fini(vif);
  502. }
  503. }
  504. int wil_priv_init(struct wil6210_priv *wil)
  505. {
  506. uint i;
  507. wil_dbg_misc(wil, "priv_init\n");
  508. memset(wil->sta, 0, sizeof(wil->sta));
  509. for (i = 0; i < WIL6210_MAX_CID; i++) {
  510. spin_lock_init(&wil->sta[i].tid_rx_lock);
  511. wil->sta[i].mid = U8_MAX;
  512. }
  513. for (i = 0; i < WIL6210_MAX_TX_RINGS; i++) {
  514. spin_lock_init(&wil->ring_tx_data[i].lock);
  515. wil->ring2cid_tid[i][0] = WIL6210_MAX_CID;
  516. }
  517. mutex_init(&wil->mutex);
  518. mutex_init(&wil->vif_mutex);
  519. mutex_init(&wil->wmi_mutex);
  520. mutex_init(&wil->halp.lock);
  521. init_completion(&wil->wmi_ready);
  522. init_completion(&wil->wmi_call);
  523. init_completion(&wil->halp.comp);
  524. INIT_WORK(&wil->wmi_event_worker, wmi_event_worker);
  525. INIT_WORK(&wil->fw_error_worker, wil_fw_error_worker);
  526. INIT_LIST_HEAD(&wil->pending_wmi_ev);
  527. spin_lock_init(&wil->wmi_ev_lock);
  528. spin_lock_init(&wil->net_queue_lock);
  529. init_waitqueue_head(&wil->wq);
  530. wil->wmi_wq = create_singlethread_workqueue(WIL_NAME "_wmi");
  531. if (!wil->wmi_wq)
  532. return -EAGAIN;
  533. wil->wq_service = create_singlethread_workqueue(WIL_NAME "_service");
  534. if (!wil->wq_service)
  535. goto out_wmi_wq;
  536. wil->last_fw_recovery = jiffies;
  537. wil->tx_interframe_timeout = WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT;
  538. wil->rx_interframe_timeout = WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT;
  539. wil->tx_max_burst_duration = WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT;
  540. wil->rx_max_burst_duration = WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT;
  541. if (rx_ring_overflow_thrsh == WIL6210_RX_HIGH_TRSH_INIT)
  542. rx_ring_overflow_thrsh = WIL6210_RX_HIGH_TRSH_DEFAULT;
  543. wil->ps_profile = WMI_PS_PROFILE_TYPE_DEFAULT;
  544. wil->wakeup_trigger = WMI_WAKEUP_TRIGGER_UCAST |
  545. WMI_WAKEUP_TRIGGER_BCAST;
  546. memset(&wil->suspend_stats, 0, sizeof(wil->suspend_stats));
  547. wil->ring_idle_trsh = 16;
  548. wil->reply_mid = U8_MAX;
  549. wil->max_vifs = 1;
  550. /* edma configuration can be updated via debugfs before allocation */
  551. wil->num_rx_status_rings = WIL_DEFAULT_NUM_RX_STATUS_RINGS;
  552. wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT;
  553. /* Rx status ring size should be bigger than the number of RX buffers
  554. * in order to prevent backpressure on the status ring, which may
  555. * cause HW freeze.
  556. */
  557. wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT;
  558. /* Number of RX buffer IDs should be bigger than the RX descriptor
  559. * ring size as in HW reorder flow, the HW can consume additional
  560. * buffers before releasing the previous ones.
  561. */
  562. wil->rx_buff_id_count = WIL_RX_BUFF_ARR_SIZE_DEFAULT;
  563. wil->amsdu_en = 1;
  564. return 0;
  565. out_wmi_wq:
  566. destroy_workqueue(wil->wmi_wq);
  567. return -EAGAIN;
  568. }
  569. void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps)
  570. {
  571. if (wil->platform_ops.bus_request) {
  572. wil->bus_request_kbps = kbps;
  573. wil->platform_ops.bus_request(wil->platform_handle, kbps);
  574. }
  575. }
  576. /**
  577. * wil6210_disconnect - disconnect one connection
  578. * @vif: virtual interface context
  579. * @bssid: peer to disconnect, NULL to disconnect all
  580. * @reason_code: Reason code for the Disassociation frame
  581. * @from_event: whether is invoked from FW event handler
  582. *
  583. * Disconnect and release associated resources. If invoked not from the
  584. * FW event handler, issue WMI command(s) to trigger MAC disconnect.
  585. */
  586. void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid,
  587. u16 reason_code, bool from_event)
  588. {
  589. struct wil6210_priv *wil = vif_to_wil(vif);
  590. wil_dbg_misc(wil, "disconnect\n");
  591. del_timer_sync(&vif->connect_timer);
  592. _wil6210_disconnect(vif, bssid, reason_code, from_event);
  593. }
  594. void wil_priv_deinit(struct wil6210_priv *wil)
  595. {
  596. wil_dbg_misc(wil, "priv_deinit\n");
  597. wil_set_recovery_state(wil, fw_recovery_idle);
  598. cancel_work_sync(&wil->fw_error_worker);
  599. wmi_event_flush(wil);
  600. destroy_workqueue(wil->wq_service);
  601. destroy_workqueue(wil->wmi_wq);
  602. }
  603. static void wil_shutdown_bl(struct wil6210_priv *wil)
  604. {
  605. u32 val;
  606. wil_s(wil, RGF_USER_BL +
  607. offsetof(struct bl_dedicated_registers_v1,
  608. bl_shutdown_handshake), BL_SHUTDOWN_HS_GRTD);
  609. usleep_range(100, 150);
  610. val = wil_r(wil, RGF_USER_BL +
  611. offsetof(struct bl_dedicated_registers_v1,
  612. bl_shutdown_handshake));
  613. if (val & BL_SHUTDOWN_HS_RTD) {
  614. wil_dbg_misc(wil, "BL is ready for halt\n");
  615. return;
  616. }
  617. wil_err(wil, "BL did not report ready for halt\n");
  618. }
  619. /* this format is used by ARC embedded CPU for instruction memory */
  620. static inline u32 ARC_me_imm32(u32 d)
  621. {
  622. return ((d & 0xffff0000) >> 16) | ((d & 0x0000ffff) << 16);
  623. }
  624. /* defines access to interrupt vectors for wil_freeze_bl */
  625. #define ARC_IRQ_VECTOR_OFFSET(N) ((N) * 8)
  626. /* ARC long jump instruction */
  627. #define ARC_JAL_INST (0x20200f80)
  628. static void wil_freeze_bl(struct wil6210_priv *wil)
  629. {
  630. u32 jal, upc, saved;
  631. u32 ivt3 = ARC_IRQ_VECTOR_OFFSET(3);
  632. jal = wil_r(wil, wil->iccm_base + ivt3);
  633. if (jal != ARC_me_imm32(ARC_JAL_INST)) {
  634. wil_dbg_misc(wil, "invalid IVT entry found, skipping\n");
  635. return;
  636. }
  637. /* prevent the target from entering deep sleep
  638. * and disabling memory access
  639. */
  640. saved = wil_r(wil, RGF_USER_USAGE_8);
  641. wil_w(wil, RGF_USER_USAGE_8, saved | BIT_USER_PREVENT_DEEP_SLEEP);
  642. usleep_range(20, 25); /* let the BL process the bit */
  643. /* redirect to endless loop in the INT_L1 context and let it trap */
  644. wil_w(wil, wil->iccm_base + ivt3 + 4, ARC_me_imm32(ivt3));
  645. usleep_range(20, 25); /* let the BL get into the trap */
  646. /* verify the BL is frozen */
  647. upc = wil_r(wil, RGF_USER_CPU_PC);
  648. if (upc < ivt3 || (upc > (ivt3 + 8)))
  649. wil_dbg_misc(wil, "BL freeze failed, PC=0x%08X\n", upc);
  650. wil_w(wil, RGF_USER_USAGE_8, saved);
  651. }
  652. static void wil_bl_prepare_halt(struct wil6210_priv *wil)
  653. {
  654. u32 tmp, ver;
  655. /* before halting device CPU driver must make sure BL is not accessing
  656. * host memory. This is done differently depending on BL version:
  657. * 1. For very old BL versions the procedure is skipped
  658. * (not supported).
  659. * 2. For old BL version we use a special trick to freeze the BL
  660. * 3. For new BL versions we shutdown the BL using handshake procedure.
  661. */
  662. tmp = wil_r(wil, RGF_USER_BL +
  663. offsetof(struct bl_dedicated_registers_v0,
  664. boot_loader_struct_version));
  665. if (!tmp) {
  666. wil_dbg_misc(wil, "old BL, skipping halt preparation\n");
  667. return;
  668. }
  669. tmp = wil_r(wil, RGF_USER_BL +
  670. offsetof(struct bl_dedicated_registers_v1,
  671. bl_shutdown_handshake));
  672. ver = BL_SHUTDOWN_HS_PROT_VER(tmp);
  673. if (ver > 0)
  674. wil_shutdown_bl(wil);
  675. else
  676. wil_freeze_bl(wil);
  677. }
  678. static inline void wil_halt_cpu(struct wil6210_priv *wil)
  679. {
  680. if (wil->hw_version >= HW_VER_TALYN_MB) {
  681. wil_w(wil, RGF_USER_USER_CPU_0_TALYN_MB,
  682. BIT_USER_USER_CPU_MAN_RST);
  683. wil_w(wil, RGF_USER_MAC_CPU_0_TALYN_MB,
  684. BIT_USER_MAC_CPU_MAN_RST);
  685. } else {
  686. wil_w(wil, RGF_USER_USER_CPU_0, BIT_USER_USER_CPU_MAN_RST);
  687. wil_w(wil, RGF_USER_MAC_CPU_0, BIT_USER_MAC_CPU_MAN_RST);
  688. }
  689. }
  690. static inline void wil_release_cpu(struct wil6210_priv *wil)
  691. {
  692. /* Start CPU */
  693. if (wil->hw_version >= HW_VER_TALYN_MB)
  694. wil_w(wil, RGF_USER_USER_CPU_0_TALYN_MB, 1);
  695. else
  696. wil_w(wil, RGF_USER_USER_CPU_0, 1);
  697. }
  698. static void wil_set_oob_mode(struct wil6210_priv *wil, u8 mode)
  699. {
  700. wil_info(wil, "oob_mode to %d\n", mode);
  701. switch (mode) {
  702. case 0:
  703. wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE |
  704. BIT_USER_OOB_R2_MODE);
  705. break;
  706. case 1:
  707. wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE);
  708. wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
  709. break;
  710. case 2:
  711. wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
  712. wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE);
  713. break;
  714. default:
  715. wil_err(wil, "invalid oob_mode: %d\n", mode);
  716. }
  717. }
  718. static int wil_wait_device_ready(struct wil6210_priv *wil, int no_flash)
  719. {
  720. int delay = 0;
  721. u32 x, x1 = 0;
  722. /* wait until device ready. */
  723. if (no_flash) {
  724. msleep(PMU_READY_DELAY_MS);
  725. wil_dbg_misc(wil, "Reset completed\n");
  726. } else {
  727. do {
  728. msleep(RST_DELAY);
  729. x = wil_r(wil, RGF_USER_BL +
  730. offsetof(struct bl_dedicated_registers_v0,
  731. boot_loader_ready));
  732. if (x1 != x) {
  733. wil_dbg_misc(wil, "BL.ready 0x%08x => 0x%08x\n",
  734. x1, x);
  735. x1 = x;
  736. }
  737. if (delay++ > RST_COUNT) {
  738. wil_err(wil, "Reset not completed, bl.ready 0x%08x\n",
  739. x);
  740. return -ETIME;
  741. }
  742. } while (x != BL_READY);
  743. wil_dbg_misc(wil, "Reset completed in %d ms\n",
  744. delay * RST_DELAY);
  745. }
  746. return 0;
  747. }
  748. static int wil_wait_device_ready_talyn_mb(struct wil6210_priv *wil)
  749. {
  750. u32 otp_hw;
  751. u8 signature_status;
  752. bool otp_signature_err;
  753. bool hw_section_done;
  754. u32 otp_qc_secured;
  755. int delay = 0;
  756. /* Wait for OTP signature test to complete */
  757. usleep_range(2000, 2200);
  758. wil->boot_config = WIL_BOOT_ERR;
  759. /* Poll until OTP signature status is valid.
  760. * In vanilla and development modes, when signature test is complete
  761. * HW sets BIT_OTP_SIGNATURE_ERR_TALYN_MB.
  762. * In production mode BIT_OTP_SIGNATURE_ERR_TALYN_MB remains 0, poll
  763. * for signature status change to 2 or 3.
  764. */
  765. do {
  766. otp_hw = wil_r(wil, RGF_USER_OTP_HW_RD_MACHINE_1);
  767. signature_status = WIL_GET_BITS(otp_hw, 8, 9);
  768. otp_signature_err = otp_hw & BIT_OTP_SIGNATURE_ERR_TALYN_MB;
  769. if (otp_signature_err &&
  770. signature_status == WIL_SIG_STATUS_VANILLA) {
  771. wil->boot_config = WIL_BOOT_VANILLA;
  772. break;
  773. }
  774. if (otp_signature_err &&
  775. signature_status == WIL_SIG_STATUS_DEVELOPMENT) {
  776. wil->boot_config = WIL_BOOT_DEVELOPMENT;
  777. break;
  778. }
  779. if (!otp_signature_err &&
  780. signature_status == WIL_SIG_STATUS_PRODUCTION) {
  781. wil->boot_config = WIL_BOOT_PRODUCTION;
  782. break;
  783. }
  784. if (!otp_signature_err &&
  785. signature_status ==
  786. WIL_SIG_STATUS_CORRUPTED_PRODUCTION) {
  787. /* Unrecognized OTP signature found. Possibly a
  788. * corrupted production signature, access control
  789. * is applied as in production mode, therefore
  790. * do not fail
  791. */
  792. wil->boot_config = WIL_BOOT_PRODUCTION;
  793. break;
  794. }
  795. if (delay++ > OTP_HW_COUNT)
  796. break;
  797. usleep_range(OTP_HW_DELAY, OTP_HW_DELAY + 10);
  798. } while (!otp_signature_err && signature_status == 0);
  799. if (wil->boot_config == WIL_BOOT_ERR) {
  800. wil_err(wil,
  801. "invalid boot config, signature_status %d otp_signature_err %d\n",
  802. signature_status, otp_signature_err);
  803. return -ETIME;
  804. }
  805. wil_dbg_misc(wil,
  806. "signature test done in %d usec, otp_hw 0x%x, boot_config %d\n",
  807. delay * OTP_HW_DELAY, otp_hw, wil->boot_config);
  808. if (wil->boot_config == WIL_BOOT_VANILLA)
  809. /* Assuming not SPI boot (currently not supported) */
  810. goto out;
  811. hw_section_done = otp_hw & BIT_OTP_HW_SECTION_DONE_TALYN_MB;
  812. delay = 0;
  813. while (!hw_section_done) {
  814. msleep(RST_DELAY);
  815. otp_hw = wil_r(wil, RGF_USER_OTP_HW_RD_MACHINE_1);
  816. hw_section_done = otp_hw & BIT_OTP_HW_SECTION_DONE_TALYN_MB;
  817. if (delay++ > RST_COUNT) {
  818. wil_err(wil, "TO waiting for hw_section_done\n");
  819. return -ETIME;
  820. }
  821. }
  822. wil_dbg_misc(wil, "HW section done in %d ms\n", delay * RST_DELAY);
  823. otp_qc_secured = wil_r(wil, RGF_OTP_QC_SECURED);
  824. wil->secured_boot = otp_qc_secured & BIT_BOOT_FROM_ROM ? 1 : 0;
  825. wil_dbg_misc(wil, "secured boot is %sabled\n",
  826. wil->secured_boot ? "en" : "dis");
  827. out:
  828. wil_dbg_misc(wil, "Reset completed\n");
  829. return 0;
  830. }
  831. static int wil_target_reset(struct wil6210_priv *wil, int no_flash)
  832. {
  833. u32 x;
  834. int rc;
  835. wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->hw_name);
  836. if (wil->hw_version < HW_VER_TALYN) {
  837. /* Clear MAC link up */
  838. wil_s(wil, RGF_HP_CTRL, BIT(15));
  839. wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0,
  840. BIT_HPAL_PERST_FROM_PAD);
  841. wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_CAR_PERST_RST);
  842. }
  843. wil_halt_cpu(wil);
  844. if (!no_flash) {
  845. /* clear all boot loader "ready" bits */
  846. wil_w(wil, RGF_USER_BL +
  847. offsetof(struct bl_dedicated_registers_v0,
  848. boot_loader_ready), 0);
  849. /* this should be safe to write even with old BLs */
  850. wil_w(wil, RGF_USER_BL +
  851. offsetof(struct bl_dedicated_registers_v1,
  852. bl_shutdown_handshake), 0);
  853. }
  854. /* Clear Fw Download notification */
  855. wil_c(wil, RGF_USER_USAGE_6, BIT(0));
  856. wil_s(wil, RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN);
  857. /* XTAL stabilization should take about 3ms */
  858. usleep_range(5000, 7000);
  859. x = wil_r(wil, RGF_CAF_PLL_LOCK_STATUS);
  860. if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) {
  861. wil_err(wil, "Xtal stabilization timeout\n"
  862. "RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x);
  863. return -ETIME;
  864. }
  865. /* switch 10k to XTAL*/
  866. wil_c(wil, RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF);
  867. /* 40 MHz */
  868. wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL);
  869. wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
  870. wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf);
  871. if (wil->hw_version >= HW_VER_TALYN_MB) {
  872. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x7e000000);
  873. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003f);
  874. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0xc00000f0);
  875. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xffe7fe00);
  876. } else {
  877. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xfe000000);
  878. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003f);
  879. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0);
  880. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xffe7fe00);
  881. }
  882. wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
  883. wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0);
  884. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
  885. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
  886. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
  887. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
  888. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
  889. /* reset A2 PCIE AHB */
  890. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
  891. wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
  892. if (wil->hw_version == HW_VER_TALYN_MB)
  893. rc = wil_wait_device_ready_talyn_mb(wil);
  894. else
  895. rc = wil_wait_device_ready(wil, no_flash);
  896. if (rc)
  897. return rc;
  898. wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
  899. /* enable fix for HW bug related to the SA/DA swap in AP Rx */
  900. wil_s(wil, RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN |
  901. BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC);
  902. if (wil->hw_version < HW_VER_TALYN_MB && no_flash) {
  903. /* Reset OTP HW vectors to fit 40MHz */
  904. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME1, 0x60001);
  905. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME2, 0x20027);
  906. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME3, 0x1);
  907. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME4, 0x20027);
  908. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME5, 0x30003);
  909. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME6, 0x20002);
  910. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME7, 0x60001);
  911. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME8, 0x60001);
  912. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME9, 0x60001);
  913. wil_w(wil, RGF_USER_XPM_IFC_RD_TIME10, 0x60001);
  914. wil_w(wil, RGF_USER_XPM_RD_DOUT_SAMPLE_TIME, 0x57);
  915. }
  916. return 0;
  917. }
  918. static void wil_collect_fw_info(struct wil6210_priv *wil)
  919. {
  920. struct wiphy *wiphy = wil_to_wiphy(wil);
  921. u8 retry_short;
  922. int rc;
  923. wil_refresh_fw_capabilities(wil);
  924. rc = wmi_get_mgmt_retry(wil, &retry_short);
  925. if (!rc) {
  926. wiphy->retry_short = retry_short;
  927. wil_dbg_misc(wil, "FW retry_short: %d\n", retry_short);
  928. }
  929. }
  930. void wil_refresh_fw_capabilities(struct wil6210_priv *wil)
  931. {
  932. struct wiphy *wiphy = wil_to_wiphy(wil);
  933. int features;
  934. wil->keep_radio_on_during_sleep =
  935. test_bit(WIL_PLATFORM_CAPA_RADIO_ON_IN_SUSPEND,
  936. wil->platform_capa) &&
  937. test_bit(WMI_FW_CAPABILITY_D3_SUSPEND, wil->fw_capabilities);
  938. wil_info(wil, "keep_radio_on_during_sleep (%d)\n",
  939. wil->keep_radio_on_during_sleep);
  940. if (test_bit(WMI_FW_CAPABILITY_RSSI_REPORTING, wil->fw_capabilities))
  941. wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
  942. else
  943. wiphy->signal_type = CFG80211_SIGNAL_TYPE_UNSPEC;
  944. if (test_bit(WMI_FW_CAPABILITY_PNO, wil->fw_capabilities)) {
  945. wiphy->max_sched_scan_reqs = 1;
  946. wiphy->max_sched_scan_ssids = WMI_MAX_PNO_SSID_NUM;
  947. wiphy->max_match_sets = WMI_MAX_PNO_SSID_NUM;
  948. wiphy->max_sched_scan_ie_len = WMI_MAX_IE_LEN;
  949. wiphy->max_sched_scan_plans = WMI_MAX_PLANS_NUM;
  950. }
  951. if (test_bit(WMI_FW_CAPABILITY_TX_REQ_EXT, wil->fw_capabilities))
  952. wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX;
  953. if (wil->platform_ops.set_features) {
  954. features = (test_bit(WMI_FW_CAPABILITY_REF_CLOCK_CONTROL,
  955. wil->fw_capabilities) &&
  956. test_bit(WIL_PLATFORM_CAPA_EXT_CLK,
  957. wil->platform_capa)) ?
  958. BIT(WIL_PLATFORM_FEATURE_FW_EXT_CLK_CONTROL) : 0;
  959. if (wil->n_msi == 3)
  960. features |= BIT(WIL_PLATFORM_FEATURE_TRIPLE_MSI);
  961. wil->platform_ops.set_features(wil->platform_handle, features);
  962. }
  963. if (test_bit(WMI_FW_CAPABILITY_BACK_WIN_SIZE_64,
  964. wil->fw_capabilities)) {
  965. wil->max_agg_wsize = WIL_MAX_AGG_WSIZE_64;
  966. wil->max_ampdu_size = WIL_MAX_AMPDU_SIZE_128;
  967. } else {
  968. wil->max_agg_wsize = WIL_MAX_AGG_WSIZE;
  969. wil->max_ampdu_size = WIL_MAX_AMPDU_SIZE;
  970. }
  971. }
  972. void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r)
  973. {
  974. le32_to_cpus(&r->base);
  975. le16_to_cpus(&r->entry_size);
  976. le16_to_cpus(&r->size);
  977. le32_to_cpus(&r->tail);
  978. le32_to_cpus(&r->head);
  979. }
  980. /* construct actual board file name to use */
  981. void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len)
  982. {
  983. const char *board_file;
  984. const char *wil_talyn_fw_name = ftm_mode ? WIL_FW_NAME_FTM_TALYN :
  985. WIL_FW_NAME_TALYN;
  986. if (wil->board_file) {
  987. board_file = wil->board_file;
  988. } else {
  989. /* If specific FW file is used for Talyn,
  990. * use specific board file
  991. */
  992. if (strcmp(wil->wil_fw_name, wil_talyn_fw_name) == 0)
  993. board_file = WIL_BRD_NAME_TALYN;
  994. else
  995. board_file = WIL_BOARD_FILE_NAME;
  996. }
  997. strlcpy(buf, board_file, len);
  998. }
  999. static int wil_get_bl_info(struct wil6210_priv *wil)
  1000. {
  1001. struct net_device *ndev = wil->main_ndev;
  1002. struct wiphy *wiphy = wil_to_wiphy(wil);
  1003. union {
  1004. struct bl_dedicated_registers_v0 bl0;
  1005. struct bl_dedicated_registers_v1 bl1;
  1006. } bl;
  1007. u32 bl_ver;
  1008. u8 *mac;
  1009. u16 rf_status;
  1010. wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL),
  1011. sizeof(bl));
  1012. bl_ver = le32_to_cpu(bl.bl0.boot_loader_struct_version);
  1013. mac = bl.bl0.mac_address;
  1014. if (bl_ver == 0) {
  1015. le32_to_cpus(&bl.bl0.rf_type);
  1016. le32_to_cpus(&bl.bl0.baseband_type);
  1017. rf_status = 0; /* actually, unknown */
  1018. wil_info(wil,
  1019. "Boot Loader struct v%d: MAC = %pM RF = 0x%08x bband = 0x%08x\n",
  1020. bl_ver, mac,
  1021. bl.bl0.rf_type, bl.bl0.baseband_type);
  1022. wil_info(wil, "Boot Loader build unknown for struct v0\n");
  1023. } else {
  1024. le16_to_cpus(&bl.bl1.rf_type);
  1025. rf_status = le16_to_cpu(bl.bl1.rf_status);
  1026. le32_to_cpus(&bl.bl1.baseband_type);
  1027. le16_to_cpus(&bl.bl1.bl_version_subminor);
  1028. le16_to_cpus(&bl.bl1.bl_version_build);
  1029. wil_info(wil,
  1030. "Boot Loader struct v%d: MAC = %pM RF = 0x%04x (status 0x%04x) bband = 0x%08x\n",
  1031. bl_ver, mac,
  1032. bl.bl1.rf_type, rf_status,
  1033. bl.bl1.baseband_type);
  1034. wil_info(wil, "Boot Loader build %d.%d.%d.%d\n",
  1035. bl.bl1.bl_version_major, bl.bl1.bl_version_minor,
  1036. bl.bl1.bl_version_subminor, bl.bl1.bl_version_build);
  1037. }
  1038. if (!is_valid_ether_addr(mac)) {
  1039. wil_err(wil, "BL: Invalid MAC %pM\n", mac);
  1040. return -EINVAL;
  1041. }
  1042. ether_addr_copy(ndev->perm_addr, mac);
  1043. ether_addr_copy(wiphy->perm_addr, mac);
  1044. if (!is_valid_ether_addr(ndev->dev_addr))
  1045. ether_addr_copy(ndev->dev_addr, mac);
  1046. if (rf_status) {/* bad RF cable? */
  1047. wil_err(wil, "RF communication error 0x%04x",
  1048. rf_status);
  1049. return -EAGAIN;
  1050. }
  1051. return 0;
  1052. }
  1053. static void wil_bl_crash_info(struct wil6210_priv *wil, bool is_err)
  1054. {
  1055. u32 bl_assert_code, bl_assert_blink, bl_magic_number;
  1056. u32 bl_ver = wil_r(wil, RGF_USER_BL +
  1057. offsetof(struct bl_dedicated_registers_v0,
  1058. boot_loader_struct_version));
  1059. if (bl_ver < 2)
  1060. return;
  1061. bl_assert_code = wil_r(wil, RGF_USER_BL +
  1062. offsetof(struct bl_dedicated_registers_v1,
  1063. bl_assert_code));
  1064. bl_assert_blink = wil_r(wil, RGF_USER_BL +
  1065. offsetof(struct bl_dedicated_registers_v1,
  1066. bl_assert_blink));
  1067. bl_magic_number = wil_r(wil, RGF_USER_BL +
  1068. offsetof(struct bl_dedicated_registers_v1,
  1069. bl_magic_number));
  1070. if (is_err) {
  1071. wil_err(wil,
  1072. "BL assert code 0x%08x blink 0x%08x magic 0x%08x\n",
  1073. bl_assert_code, bl_assert_blink, bl_magic_number);
  1074. } else {
  1075. wil_dbg_misc(wil,
  1076. "BL assert code 0x%08x blink 0x%08x magic 0x%08x\n",
  1077. bl_assert_code, bl_assert_blink, bl_magic_number);
  1078. }
  1079. }
  1080. static int wil_get_otp_info(struct wil6210_priv *wil)
  1081. {
  1082. struct net_device *ndev = wil->main_ndev;
  1083. struct wiphy *wiphy = wil_to_wiphy(wil);
  1084. u8 mac[8];
  1085. int mac_addr;
  1086. if (wil->hw_version >= HW_VER_TALYN_MB)
  1087. mac_addr = RGF_OTP_MAC_TALYN_MB;
  1088. else
  1089. mac_addr = RGF_OTP_MAC;
  1090. wil_memcpy_fromio_32(mac, wil->csr + HOSTADDR(mac_addr),
  1091. sizeof(mac));
  1092. if (!is_valid_ether_addr(mac)) {
  1093. wil_err(wil, "Invalid MAC %pM\n", mac);
  1094. return -EINVAL;
  1095. }
  1096. ether_addr_copy(ndev->perm_addr, mac);
  1097. ether_addr_copy(wiphy->perm_addr, mac);
  1098. if (!is_valid_ether_addr(ndev->dev_addr))
  1099. ether_addr_copy(ndev->dev_addr, mac);
  1100. return 0;
  1101. }
  1102. static int wil_wait_for_fw_ready(struct wil6210_priv *wil)
  1103. {
  1104. ulong to = msecs_to_jiffies(2000);
  1105. ulong left = wait_for_completion_timeout(&wil->wmi_ready, to);
  1106. if (0 == left) {
  1107. wil_err(wil, "Firmware not ready\n");
  1108. return -ETIME;
  1109. } else {
  1110. wil_info(wil, "FW ready after %d ms. HW version 0x%08x\n",
  1111. jiffies_to_msecs(to-left), wil->hw_version);
  1112. }
  1113. return 0;
  1114. }
  1115. void wil_abort_scan(struct wil6210_vif *vif, bool sync)
  1116. {
  1117. struct wil6210_priv *wil = vif_to_wil(vif);
  1118. int rc;
  1119. struct cfg80211_scan_info info = {
  1120. .aborted = true,
  1121. };
  1122. lockdep_assert_held(&wil->vif_mutex);
  1123. if (!vif->scan_request)
  1124. return;
  1125. wil_dbg_misc(wil, "Abort scan_request 0x%p\n", vif->scan_request);
  1126. del_timer_sync(&vif->scan_timer);
  1127. mutex_unlock(&wil->vif_mutex);
  1128. rc = wmi_abort_scan(vif);
  1129. if (!rc && sync)
  1130. wait_event_interruptible_timeout(wil->wq, !vif->scan_request,
  1131. msecs_to_jiffies(
  1132. WAIT_FOR_SCAN_ABORT_MS));
  1133. mutex_lock(&wil->vif_mutex);
  1134. if (vif->scan_request) {
  1135. cfg80211_scan_done(vif->scan_request, &info);
  1136. vif->scan_request = NULL;
  1137. }
  1138. }
  1139. void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync)
  1140. {
  1141. int i;
  1142. lockdep_assert_held(&wil->vif_mutex);
  1143. for (i = 0; i < wil->max_vifs; i++) {
  1144. struct wil6210_vif *vif = wil->vifs[i];
  1145. if (vif)
  1146. wil_abort_scan(vif, sync);
  1147. }
  1148. }
  1149. int wil_ps_update(struct wil6210_priv *wil, enum wmi_ps_profile_type ps_profile)
  1150. {
  1151. int rc;
  1152. if (!test_bit(WMI_FW_CAPABILITY_PS_CONFIG, wil->fw_capabilities)) {
  1153. wil_err(wil, "set_power_mgmt not supported\n");
  1154. return -EOPNOTSUPP;
  1155. }
  1156. rc = wmi_ps_dev_profile_cfg(wil, ps_profile);
  1157. if (rc)
  1158. wil_err(wil, "wmi_ps_dev_profile_cfg failed (%d)\n", rc);
  1159. else
  1160. wil->ps_profile = ps_profile;
  1161. return rc;
  1162. }
  1163. static void wil_pre_fw_config(struct wil6210_priv *wil)
  1164. {
  1165. /* Mark FW as loaded from host */
  1166. wil_s(wil, RGF_USER_USAGE_6, 1);
  1167. /* clear any interrupts which on-card-firmware
  1168. * may have set
  1169. */
  1170. wil6210_clear_irq(wil);
  1171. /* CAF_ICR - clear and mask */
  1172. /* it is W1C, clear by writing back same value */
  1173. if (wil->hw_version < HW_VER_TALYN_MB) {
  1174. wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0);
  1175. wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0);
  1176. } else {
  1177. wil_s(wil,
  1178. RGF_CAF_ICR_TALYN_MB + offsetof(struct RGF_ICR, ICR), 0);
  1179. wil_w(wil, RGF_CAF_ICR_TALYN_MB +
  1180. offsetof(struct RGF_ICR, IMV), ~0);
  1181. }
  1182. /* clear PAL_UNIT_ICR (potential D0->D3 leftover)
  1183. * In Talyn-MB host cannot access this register due to
  1184. * access control, hence PAL_UNIT_ICR is cleared by the FW
  1185. */
  1186. if (wil->hw_version < HW_VER_TALYN_MB)
  1187. wil_s(wil, RGF_PAL_UNIT_ICR + offsetof(struct RGF_ICR, ICR),
  1188. 0);
  1189. if (wil->fw_calib_result > 0) {
  1190. __le32 val = cpu_to_le32(wil->fw_calib_result |
  1191. (CALIB_RESULT_SIGNATURE << 8));
  1192. wil_w(wil, RGF_USER_FW_CALIB_RESULT, (u32 __force)val);
  1193. }
  1194. }
  1195. static int wil_restore_vifs(struct wil6210_priv *wil)
  1196. {
  1197. struct wil6210_vif *vif;
  1198. struct net_device *ndev;
  1199. struct wireless_dev *wdev;
  1200. int i, rc;
  1201. for (i = 0; i < wil->max_vifs; i++) {
  1202. vif = wil->vifs[i];
  1203. if (!vif)
  1204. continue;
  1205. vif->ap_isolate = 0;
  1206. if (vif->mid) {
  1207. ndev = vif_to_ndev(vif);
  1208. wdev = vif_to_wdev(vif);
  1209. rc = wmi_port_allocate(wil, vif->mid, ndev->dev_addr,
  1210. wdev->iftype);
  1211. if (rc) {
  1212. wil_err(wil, "fail to restore VIF %d type %d, rc %d\n",
  1213. i, wdev->iftype, rc);
  1214. return rc;
  1215. }
  1216. }
  1217. }
  1218. return 0;
  1219. }
  1220. /*
  1221. * We reset all the structures, and we reset the UMAC.
  1222. * After calling this routine, you're expected to reload
  1223. * the firmware.
  1224. */
  1225. int wil_reset(struct wil6210_priv *wil, bool load_fw)
  1226. {
  1227. int rc, i;
  1228. unsigned long status_flags = BIT(wil_status_resetting);
  1229. int no_flash;
  1230. struct wil6210_vif *vif;
  1231. wil_dbg_misc(wil, "reset\n");
  1232. WARN_ON(!mutex_is_locked(&wil->mutex));
  1233. WARN_ON(test_bit(wil_status_napi_en, wil->status));
  1234. if (debug_fw) {
  1235. static const u8 mac[ETH_ALEN] = {
  1236. 0x00, 0xde, 0xad, 0x12, 0x34, 0x56,
  1237. };
  1238. struct net_device *ndev = wil->main_ndev;
  1239. ether_addr_copy(ndev->perm_addr, mac);
  1240. ether_addr_copy(ndev->dev_addr, ndev->perm_addr);
  1241. return 0;
  1242. }
  1243. if (wil->hw_version == HW_VER_UNKNOWN)
  1244. return -ENODEV;
  1245. if (test_bit(WIL_PLATFORM_CAPA_T_PWR_ON_0, wil->platform_capa)) {
  1246. wil_dbg_misc(wil, "Notify FW to set T_POWER_ON=0\n");
  1247. wil_s(wil, RGF_USER_USAGE_8, BIT_USER_SUPPORT_T_POWER_ON_0);
  1248. }
  1249. if (test_bit(WIL_PLATFORM_CAPA_EXT_CLK, wil->platform_capa)) {
  1250. wil_dbg_misc(wil, "Notify FW on ext clock configuration\n");
  1251. wil_s(wil, RGF_USER_USAGE_8, BIT_USER_EXT_CLK);
  1252. }
  1253. if (wil->platform_ops.notify) {
  1254. rc = wil->platform_ops.notify(wil->platform_handle,
  1255. WIL_PLATFORM_EVT_PRE_RESET);
  1256. if (rc)
  1257. wil_err(wil, "PRE_RESET platform notify failed, rc %d\n",
  1258. rc);
  1259. }
  1260. set_bit(wil_status_resetting, wil->status);
  1261. if (test_bit(wil_status_collecting_dumps, wil->status)) {
  1262. /* Device collects crash dump, cancel the reset.
  1263. * following crash dump collection, reset would take place.
  1264. */
  1265. wil_dbg_misc(wil, "reject reset while collecting crash dump\n");
  1266. rc = -EBUSY;
  1267. goto out;
  1268. }
  1269. mutex_lock(&wil->vif_mutex);
  1270. wil_abort_scan_all_vifs(wil, false);
  1271. mutex_unlock(&wil->vif_mutex);
  1272. for (i = 0; i < wil->max_vifs; i++) {
  1273. vif = wil->vifs[i];
  1274. if (vif) {
  1275. cancel_work_sync(&vif->disconnect_worker);
  1276. wil6210_disconnect(vif, NULL,
  1277. WLAN_REASON_DEAUTH_LEAVING, false);
  1278. }
  1279. }
  1280. wil_bcast_fini_all(wil);
  1281. /* Disable device led before reset*/
  1282. wmi_led_cfg(wil, false);
  1283. /* prevent NAPI from being scheduled and prevent wmi commands */
  1284. mutex_lock(&wil->wmi_mutex);
  1285. if (test_bit(wil_status_suspending, wil->status))
  1286. status_flags |= BIT(wil_status_suspending);
  1287. bitmap_and(wil->status, wil->status, &status_flags,
  1288. wil_status_last);
  1289. wil_dbg_misc(wil, "wil->status (0x%lx)\n", *wil->status);
  1290. mutex_unlock(&wil->wmi_mutex);
  1291. wil_mask_irq(wil);
  1292. wmi_event_flush(wil);
  1293. flush_workqueue(wil->wq_service);
  1294. flush_workqueue(wil->wmi_wq);
  1295. no_flash = test_bit(hw_capa_no_flash, wil->hw_capa);
  1296. if (!no_flash)
  1297. wil_bl_crash_info(wil, false);
  1298. wil_disable_irq(wil);
  1299. rc = wil_target_reset(wil, no_flash);
  1300. wil6210_clear_irq(wil);
  1301. wil_enable_irq(wil);
  1302. wil->txrx_ops.rx_fini(wil);
  1303. wil->txrx_ops.tx_fini(wil);
  1304. if (rc) {
  1305. if (!no_flash)
  1306. wil_bl_crash_info(wil, true);
  1307. goto out;
  1308. }
  1309. if (no_flash) {
  1310. rc = wil_get_otp_info(wil);
  1311. } else {
  1312. rc = wil_get_bl_info(wil);
  1313. if (rc == -EAGAIN && !load_fw)
  1314. /* ignore RF error if not going up */
  1315. rc = 0;
  1316. }
  1317. if (rc)
  1318. goto out;
  1319. wil_set_oob_mode(wil, oob_mode);
  1320. if (load_fw) {
  1321. char board_file[WIL_BOARD_FILE_MAX_NAMELEN];
  1322. if (wil->secured_boot) {
  1323. wil_err(wil, "secured boot is not supported\n");
  1324. return -ENOTSUPP;
  1325. }
  1326. board_file[0] = '\0';
  1327. wil_get_board_file(wil, board_file, sizeof(board_file));
  1328. wil_info(wil, "Use firmware <%s> + board <%s>\n",
  1329. wil->wil_fw_name, board_file);
  1330. if (!no_flash)
  1331. wil_bl_prepare_halt(wil);
  1332. wil_halt_cpu(wil);
  1333. memset(wil->fw_version, 0, sizeof(wil->fw_version));
  1334. /* Loading f/w from the file */
  1335. rc = wil_request_firmware(wil, wil->wil_fw_name, true);
  1336. if (rc)
  1337. goto out;
  1338. if (wil->brd_file_addr)
  1339. rc = wil_request_board(wil, board_file);
  1340. else
  1341. rc = wil_request_firmware(wil, board_file, true);
  1342. if (rc)
  1343. goto out;
  1344. wil_pre_fw_config(wil);
  1345. wil_release_cpu(wil);
  1346. }
  1347. /* init after reset */
  1348. reinit_completion(&wil->wmi_ready);
  1349. reinit_completion(&wil->wmi_call);
  1350. reinit_completion(&wil->halp.comp);
  1351. clear_bit(wil_status_resetting, wil->status);
  1352. if (load_fw) {
  1353. wil_unmask_irq(wil);
  1354. /* we just started MAC, wait for FW ready */
  1355. rc = wil_wait_for_fw_ready(wil);
  1356. if (rc)
  1357. return rc;
  1358. /* check FW is responsive */
  1359. rc = wmi_echo(wil);
  1360. if (rc) {
  1361. wil_err(wil, "wmi_echo failed, rc %d\n", rc);
  1362. return rc;
  1363. }
  1364. wil->txrx_ops.configure_interrupt_moderation(wil);
  1365. /* Enable OFU rdy valid bug fix, to prevent hang in oful34_rx
  1366. * while there is back-pressure from Host during RX
  1367. */
  1368. if (wil->hw_version >= HW_VER_TALYN_MB)
  1369. wil_s(wil, RGF_DMA_MISC_CTL,
  1370. BIT_OFUL34_RDY_VALID_BUG_FIX_EN);
  1371. rc = wil_restore_vifs(wil);
  1372. if (rc) {
  1373. wil_err(wil, "failed to restore vifs, rc %d\n", rc);
  1374. return rc;
  1375. }
  1376. wil_collect_fw_info(wil);
  1377. if (wil->ps_profile != WMI_PS_PROFILE_TYPE_DEFAULT)
  1378. wil_ps_update(wil, wil->ps_profile);
  1379. if (wil->platform_ops.notify) {
  1380. rc = wil->platform_ops.notify(wil->platform_handle,
  1381. WIL_PLATFORM_EVT_FW_RDY);
  1382. if (rc) {
  1383. wil_err(wil, "FW_RDY notify failed, rc %d\n",
  1384. rc);
  1385. rc = 0;
  1386. }
  1387. }
  1388. }
  1389. return rc;
  1390. out:
  1391. clear_bit(wil_status_resetting, wil->status);
  1392. return rc;
  1393. }
  1394. void wil_fw_error_recovery(struct wil6210_priv *wil)
  1395. {
  1396. wil_dbg_misc(wil, "starting fw error recovery\n");
  1397. if (test_bit(wil_status_resetting, wil->status)) {
  1398. wil_info(wil, "Reset already in progress\n");
  1399. return;
  1400. }
  1401. wil->recovery_state = fw_recovery_pending;
  1402. schedule_work(&wil->fw_error_worker);
  1403. }
  1404. int __wil_up(struct wil6210_priv *wil)
  1405. {
  1406. struct net_device *ndev = wil->main_ndev;
  1407. struct wireless_dev *wdev = ndev->ieee80211_ptr;
  1408. int rc;
  1409. WARN_ON(!mutex_is_locked(&wil->mutex));
  1410. rc = wil_reset(wil, true);
  1411. if (rc)
  1412. return rc;
  1413. /* Rx RING. After MAC and beacon */
  1414. rc = wil->txrx_ops.rx_init(wil, rx_ring_order);
  1415. if (rc)
  1416. return rc;
  1417. rc = wil->txrx_ops.tx_init(wil);
  1418. if (rc)
  1419. return rc;
  1420. switch (wdev->iftype) {
  1421. case NL80211_IFTYPE_STATION:
  1422. wil_dbg_misc(wil, "type: STATION\n");
  1423. ndev->type = ARPHRD_ETHER;
  1424. break;
  1425. case NL80211_IFTYPE_AP:
  1426. wil_dbg_misc(wil, "type: AP\n");
  1427. ndev->type = ARPHRD_ETHER;
  1428. break;
  1429. case NL80211_IFTYPE_P2P_CLIENT:
  1430. wil_dbg_misc(wil, "type: P2P_CLIENT\n");
  1431. ndev->type = ARPHRD_ETHER;
  1432. break;
  1433. case NL80211_IFTYPE_P2P_GO:
  1434. wil_dbg_misc(wil, "type: P2P_GO\n");
  1435. ndev->type = ARPHRD_ETHER;
  1436. break;
  1437. case NL80211_IFTYPE_MONITOR:
  1438. wil_dbg_misc(wil, "type: Monitor\n");
  1439. ndev->type = ARPHRD_IEEE80211_RADIOTAP;
  1440. /* ARPHRD_IEEE80211 or ARPHRD_IEEE80211_RADIOTAP ? */
  1441. break;
  1442. default:
  1443. return -EOPNOTSUPP;
  1444. }
  1445. /* MAC address - pre-requisite for other commands */
  1446. wmi_set_mac_address(wil, ndev->dev_addr);
  1447. wil_dbg_misc(wil, "NAPI enable\n");
  1448. napi_enable(&wil->napi_rx);
  1449. napi_enable(&wil->napi_tx);
  1450. set_bit(wil_status_napi_en, wil->status);
  1451. wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
  1452. return 0;
  1453. }
  1454. int wil_up(struct wil6210_priv *wil)
  1455. {
  1456. int rc;
  1457. wil_dbg_misc(wil, "up\n");
  1458. mutex_lock(&wil->mutex);
  1459. rc = __wil_up(wil);
  1460. mutex_unlock(&wil->mutex);
  1461. return rc;
  1462. }
  1463. int __wil_down(struct wil6210_priv *wil)
  1464. {
  1465. WARN_ON(!mutex_is_locked(&wil->mutex));
  1466. set_bit(wil_status_resetting, wil->status);
  1467. wil6210_bus_request(wil, 0);
  1468. wil_disable_irq(wil);
  1469. if (test_and_clear_bit(wil_status_napi_en, wil->status)) {
  1470. napi_disable(&wil->napi_rx);
  1471. napi_disable(&wil->napi_tx);
  1472. wil_dbg_misc(wil, "NAPI disable\n");
  1473. }
  1474. wil_enable_irq(wil);
  1475. mutex_lock(&wil->vif_mutex);
  1476. wil_p2p_stop_radio_operations(wil);
  1477. wil_abort_scan_all_vifs(wil, false);
  1478. mutex_unlock(&wil->vif_mutex);
  1479. return wil_reset(wil, false);
  1480. }
  1481. int wil_down(struct wil6210_priv *wil)
  1482. {
  1483. int rc;
  1484. wil_dbg_misc(wil, "down\n");
  1485. wil_set_recovery_state(wil, fw_recovery_idle);
  1486. mutex_lock(&wil->mutex);
  1487. rc = __wil_down(wil);
  1488. mutex_unlock(&wil->mutex);
  1489. return rc;
  1490. }
  1491. int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac)
  1492. {
  1493. int i;
  1494. int rc = -ENOENT;
  1495. for (i = 0; i < ARRAY_SIZE(wil->sta); i++) {
  1496. if (wil->sta[i].mid == mid &&
  1497. wil->sta[i].status != wil_sta_unused &&
  1498. ether_addr_equal(wil->sta[i].addr, mac)) {
  1499. rc = i;
  1500. break;
  1501. }
  1502. }
  1503. return rc;
  1504. }
  1505. void wil_halp_vote(struct wil6210_priv *wil)
  1506. {
  1507. unsigned long rc;
  1508. unsigned long to_jiffies = msecs_to_jiffies(WAIT_FOR_HALP_VOTE_MS);
  1509. mutex_lock(&wil->halp.lock);
  1510. wil_dbg_irq(wil, "halp_vote: start, HALP ref_cnt (%d)\n",
  1511. wil->halp.ref_cnt);
  1512. if (++wil->halp.ref_cnt == 1) {
  1513. reinit_completion(&wil->halp.comp);
  1514. /* mark to IRQ context to handle HALP ICR */
  1515. wil->halp.handle_icr = true;
  1516. wil6210_set_halp(wil);
  1517. rc = wait_for_completion_timeout(&wil->halp.comp, to_jiffies);
  1518. if (!rc) {
  1519. wil_err(wil, "HALP vote timed out\n");
  1520. /* Mask HALP as done in case the interrupt is raised */
  1521. wil->halp.handle_icr = false;
  1522. wil6210_mask_halp(wil);
  1523. } else {
  1524. wil_dbg_irq(wil,
  1525. "halp_vote: HALP vote completed after %d ms\n",
  1526. jiffies_to_msecs(to_jiffies - rc));
  1527. }
  1528. }
  1529. wil_dbg_irq(wil, "halp_vote: end, HALP ref_cnt (%d)\n",
  1530. wil->halp.ref_cnt);
  1531. mutex_unlock(&wil->halp.lock);
  1532. }
  1533. void wil_halp_unvote(struct wil6210_priv *wil)
  1534. {
  1535. WARN_ON(wil->halp.ref_cnt == 0);
  1536. mutex_lock(&wil->halp.lock);
  1537. wil_dbg_irq(wil, "halp_unvote: start, HALP ref_cnt (%d)\n",
  1538. wil->halp.ref_cnt);
  1539. if (--wil->halp.ref_cnt == 0) {
  1540. wil6210_clear_halp(wil);
  1541. wil_dbg_irq(wil, "HALP unvote\n");
  1542. }
  1543. wil_dbg_irq(wil, "halp_unvote:end, HALP ref_cnt (%d)\n",
  1544. wil->halp.ref_cnt);
  1545. mutex_unlock(&wil->halp.lock);
  1546. }
  1547. void wil_init_txrx_ops(struct wil6210_priv *wil)
  1548. {
  1549. if (wil->use_enhanced_dma_hw)
  1550. wil_init_txrx_ops_edma(wil);
  1551. else
  1552. wil_init_txrx_ops_legacy_dma(wil);
  1553. }