rf.c 14 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "reg.h"
  27. #include "def.h"
  28. #include "phy.h"
  29. #include "rf.h"
  30. #include "dm.h"
  31. static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
  32. void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  33. {
  34. struct rtl_priv *rtlpriv = rtl_priv(hw);
  35. struct rtl_phy *rtlphy = &rtlpriv->phy;
  36. switch (bandwidth) {
  37. case HT_CHANNEL_WIDTH_20:
  38. rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  39. 0xfffff3ff) | 0x0400);
  40. rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  41. rtlphy->rfreg_chnlval[0]);
  42. break;
  43. case HT_CHANNEL_WIDTH_20_40:
  44. rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  45. 0xfffff3ff));
  46. rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  47. rtlphy->rfreg_chnlval[0]);
  48. break;
  49. default:
  50. pr_err("unknown bandwidth: %#X\n", bandwidth);
  51. break;
  52. }
  53. }
  54. void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  55. u8 *ppowerlevel)
  56. {
  57. struct rtl_priv *rtlpriv = rtl_priv(hw);
  58. struct rtl_phy *rtlphy = &rtlpriv->phy;
  59. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  60. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  61. u32 tx_agc[2] = {0, 0}, tmpval;
  62. bool turbo_scanoff = false;
  63. u8 idx1, idx2;
  64. u8 *ptr;
  65. if (rtlefuse->eeprom_regulatory != 0)
  66. turbo_scanoff = true;
  67. if (mac->act_scanning == true) {
  68. tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  69. tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  70. if (turbo_scanoff) {
  71. for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B;
  72. idx1++) {
  73. tx_agc[idx1] = ppowerlevel[idx1] |
  74. (ppowerlevel[idx1] << 8) |
  75. (ppowerlevel[idx1] << 16) |
  76. (ppowerlevel[idx1] << 24);
  77. }
  78. }
  79. } else {
  80. for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  81. tx_agc[idx1] = ppowerlevel[idx1] |
  82. (ppowerlevel[idx1] << 8) |
  83. (ppowerlevel[idx1] << 16) |
  84. (ppowerlevel[idx1] << 24);
  85. }
  86. if (rtlefuse->eeprom_regulatory == 0) {
  87. tmpval =
  88. (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
  89. (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
  90. 8);
  91. tx_agc[RF90_PATH_A] += tmpval;
  92. tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
  93. (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
  94. 24);
  95. tx_agc[RF90_PATH_B] += tmpval;
  96. }
  97. }
  98. for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  99. ptr = (u8 *)&tx_agc[idx1];
  100. for (idx2 = 0; idx2 < 4; idx2++) {
  101. if (*ptr > RF6052_MAX_TX_PWR)
  102. *ptr = RF6052_MAX_TX_PWR;
  103. ptr++;
  104. }
  105. }
  106. tmpval = tx_agc[RF90_PATH_A] & 0xff;
  107. rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
  108. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  109. "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
  110. RTXAGC_A_CCK1_MCS32);
  111. tmpval = tx_agc[RF90_PATH_A] >> 8;
  112. tmpval = tmpval & 0xff00ffff;
  113. rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
  114. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  115. "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
  116. RTXAGC_B_CCK11_A_CCK2_11);
  117. tmpval = tx_agc[RF90_PATH_B] >> 24;
  118. rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
  119. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  120. "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
  121. RTXAGC_B_CCK11_A_CCK2_11);
  122. tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
  123. rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
  124. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  125. "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
  126. RTXAGC_B_CCK1_55_MCS32);
  127. }
  128. static void rtl8723e_phy_get_power_base(struct ieee80211_hw *hw,
  129. u8 *ppowerlevel, u8 channel,
  130. u32 *ofdmbase, u32 *mcsbase)
  131. {
  132. struct rtl_priv *rtlpriv = rtl_priv(hw);
  133. struct rtl_phy *rtlphy = &rtlpriv->phy;
  134. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  135. u32 powerbase0, powerbase1;
  136. u8 legacy_pwrdiff, ht20_pwrdiff;
  137. u8 i, powerlevel[2];
  138. for (i = 0; i < 2; i++) {
  139. powerlevel[i] = ppowerlevel[i];
  140. legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
  141. powerbase0 = powerlevel[i] + legacy_pwrdiff;
  142. powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
  143. (powerbase0 << 8) | powerbase0;
  144. *(ofdmbase + i) = powerbase0;
  145. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  146. " [OFDM power base index rf(%c) = 0x%x]\n",
  147. ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
  148. }
  149. for (i = 0; i < 2; i++) {
  150. if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
  151. ht20_pwrdiff =
  152. rtlefuse->txpwr_ht20diff[i][channel - 1];
  153. powerlevel[i] += ht20_pwrdiff;
  154. }
  155. powerbase1 = powerlevel[i];
  156. powerbase1 = (powerbase1 << 24) |
  157. (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
  158. *(mcsbase + i) = powerbase1;
  159. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  160. " [MCS power base index rf(%c) = 0x%x]\n",
  161. ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
  162. }
  163. }
  164. static void get_txpower_writeval_by_reg(struct ieee80211_hw *hw,
  165. u8 channel, u8 index,
  166. u32 *powerbase0,
  167. u32 *powerbase1,
  168. u32 *p_outwriteval)
  169. {
  170. struct rtl_priv *rtlpriv = rtl_priv(hw);
  171. struct rtl_phy *rtlphy = &rtlpriv->phy;
  172. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  173. u8 i, chnlgroup = 0, pwr_diff_limit[4];
  174. u32 writeval, customer_limit, rf;
  175. for (rf = 0; rf < 2; rf++) {
  176. switch (rtlefuse->eeprom_regulatory) {
  177. case 0:
  178. chnlgroup = 0;
  179. writeval =
  180. rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
  181. (rf ? 8 : 0)]
  182. + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
  183. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  184. "RTK better performance, writeval(%c) = 0x%x\n",
  185. ((rf == 0) ? 'A' : 'B'), writeval);
  186. break;
  187. case 1:
  188. if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
  189. writeval = ((index < 2) ? powerbase0[rf] :
  190. powerbase1[rf]);
  191. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  192. "Realtek regulatory, 40MHz, writeval(%c) = 0x%x\n",
  193. ((rf == 0) ? 'A' : 'B'), writeval);
  194. } else {
  195. if (rtlphy->pwrgroup_cnt == 1)
  196. chnlgroup = 0;
  197. if (rtlphy->pwrgroup_cnt >= 3) {
  198. if (channel <= 3)
  199. chnlgroup = 0;
  200. else if (channel >= 4 && channel <= 9)
  201. chnlgroup = 1;
  202. else if (channel > 9)
  203. chnlgroup = 2;
  204. if (rtlphy->current_chan_bw ==
  205. HT_CHANNEL_WIDTH_20)
  206. chnlgroup++;
  207. else
  208. chnlgroup += 4;
  209. }
  210. writeval =
  211. rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
  212. [index + (rf ? 8 : 0)] + ((index < 2) ?
  213. powerbase0[rf] :
  214. powerbase1[rf]);
  215. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  216. "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
  217. ((rf == 0) ? 'A' : 'B'), writeval);
  218. }
  219. break;
  220. case 2:
  221. writeval =
  222. ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
  223. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  224. "Better regulatory, writeval(%c) = 0x%x\n",
  225. ((rf == 0) ? 'A' : 'B'), writeval);
  226. break;
  227. case 3:
  228. chnlgroup = 0;
  229. if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
  230. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  231. "customer's limit, 40MHz rf(%c) = 0x%x\n",
  232. ((rf == 0) ? 'A' : 'B'),
  233. rtlefuse->pwrgroup_ht40[rf][channel -
  234. 1]);
  235. } else {
  236. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  237. "customer's limit, 20MHz rf(%c) = 0x%x\n",
  238. ((rf == 0) ? 'A' : 'B'),
  239. rtlefuse->pwrgroup_ht20[rf][channel -
  240. 1]);
  241. }
  242. for (i = 0; i < 4; i++) {
  243. pwr_diff_limit[i] =
  244. (u8)((rtlphy->mcs_txpwrlevel_origoffset
  245. [chnlgroup][index +
  246. (rf ? 8 : 0)] & (0x7f <<
  247. (i * 8))) >> (i * 8));
  248. if (rtlphy->current_chan_bw ==
  249. HT_CHANNEL_WIDTH_20_40) {
  250. if (pwr_diff_limit[i] >
  251. rtlefuse->
  252. pwrgroup_ht40[rf][channel - 1])
  253. pwr_diff_limit[i] =
  254. rtlefuse->pwrgroup_ht40[rf]
  255. [channel - 1];
  256. } else {
  257. if (pwr_diff_limit[i] >
  258. rtlefuse->
  259. pwrgroup_ht20[rf][channel - 1])
  260. pwr_diff_limit[i] =
  261. rtlefuse->pwrgroup_ht20[rf]
  262. [channel - 1];
  263. }
  264. }
  265. customer_limit = (pwr_diff_limit[3] << 24) |
  266. (pwr_diff_limit[2] << 16) |
  267. (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
  268. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  269. "Customer's limit rf(%c) = 0x%x\n",
  270. ((rf == 0) ? 'A' : 'B'), customer_limit);
  271. writeval = customer_limit +
  272. ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
  273. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  274. "Customer, writeval rf(%c)= 0x%x\n",
  275. ((rf == 0) ? 'A' : 'B'), writeval);
  276. break;
  277. default:
  278. chnlgroup = 0;
  279. writeval =
  280. rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
  281. [index + (rf ? 8 : 0)]
  282. + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
  283. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  284. "RTK better performance, writeval rf(%c) = 0x%x\n",
  285. ((rf == 0) ? 'A' : 'B'), writeval);
  286. break;
  287. }
  288. if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
  289. writeval = writeval - 0x06060606;
  290. else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  291. TXHIGHPWRLEVEL_BT2)
  292. writeval = writeval - 0x0c0c0c0c;
  293. *(p_outwriteval + rf) = writeval;
  294. }
  295. }
  296. static void _rtl8723e_write_ofdm_power_reg(struct ieee80211_hw *hw,
  297. u8 index, u32 *pvalue)
  298. {
  299. struct rtl_priv *rtlpriv = rtl_priv(hw);
  300. struct rtl_phy *rtlphy = &rtlpriv->phy;
  301. u16 regoffset_a[6] = {
  302. RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
  303. RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
  304. RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
  305. };
  306. u16 regoffset_b[6] = {
  307. RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
  308. RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
  309. RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
  310. };
  311. u8 i, rf, pwr_val[4];
  312. u32 writeval;
  313. u16 regoffset;
  314. for (rf = 0; rf < 2; rf++) {
  315. writeval = pvalue[rf];
  316. for (i = 0; i < 4; i++) {
  317. pwr_val[i] = (u8)((writeval & (0x7f <<
  318. (i * 8))) >> (i * 8));
  319. if (pwr_val[i] > RF6052_MAX_TX_PWR)
  320. pwr_val[i] = RF6052_MAX_TX_PWR;
  321. }
  322. writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
  323. (pwr_val[1] << 8) | pwr_val[0];
  324. if (rf == 0)
  325. regoffset = regoffset_a[index];
  326. else
  327. regoffset = regoffset_b[index];
  328. rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
  329. RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
  330. "Set 0x%x = %08x\n", regoffset, writeval);
  331. if (((get_rf_type(rtlphy) == RF_2T2R) &&
  332. (regoffset == RTXAGC_A_MCS15_MCS12 ||
  333. regoffset == RTXAGC_B_MCS15_MCS12)) ||
  334. ((get_rf_type(rtlphy) != RF_2T2R) &&
  335. (regoffset == RTXAGC_A_MCS07_MCS04 ||
  336. regoffset == RTXAGC_B_MCS07_MCS04))) {
  337. writeval = pwr_val[3];
  338. if (regoffset == RTXAGC_A_MCS15_MCS12 ||
  339. regoffset == RTXAGC_A_MCS07_MCS04)
  340. regoffset = 0xc90;
  341. if (regoffset == RTXAGC_B_MCS15_MCS12 ||
  342. regoffset == RTXAGC_B_MCS07_MCS04)
  343. regoffset = 0xc98;
  344. for (i = 0; i < 3; i++) {
  345. writeval = (writeval > 6) ? (writeval - 6) : 0;
  346. rtl_write_byte(rtlpriv, (u32) (regoffset + i),
  347. (u8)writeval);
  348. }
  349. }
  350. }
  351. }
  352. void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
  353. u8 *ppowerlevel, u8 channel)
  354. {
  355. u32 writeval[2], powerbase0[2], powerbase1[2];
  356. u8 index;
  357. rtl8723e_phy_get_power_base(hw, ppowerlevel,
  358. channel, &powerbase0[0], &powerbase1[0]);
  359. for (index = 0; index < 6; index++) {
  360. get_txpower_writeval_by_reg(hw, channel, index, &powerbase0[0],
  361. &powerbase1[0],
  362. &writeval[0]);
  363. _rtl8723e_write_ofdm_power_reg(hw, index, &writeval[0]);
  364. }
  365. }
  366. bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw)
  367. {
  368. struct rtl_priv *rtlpriv = rtl_priv(hw);
  369. struct rtl_phy *rtlphy = &rtlpriv->phy;
  370. if (rtlphy->rf_type == RF_1T1R)
  371. rtlphy->num_total_rfpath = 1;
  372. else
  373. rtlphy->num_total_rfpath = 2;
  374. return _rtl8723e_phy_rf6052_config_parafile(hw);
  375. }
  376. static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
  377. {
  378. struct rtl_priv *rtlpriv = rtl_priv(hw);
  379. struct rtl_phy *rtlphy = &rtlpriv->phy;
  380. u32 u4_regvalue = 0;
  381. u8 rfpath;
  382. bool rtstatus = true;
  383. struct bb_reg_def *pphyreg;
  384. for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
  385. pphyreg = &rtlphy->phyreg_def[rfpath];
  386. switch (rfpath) {
  387. case RF90_PATH_A:
  388. case RF90_PATH_C:
  389. u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
  390. BRFSI_RFENV);
  391. break;
  392. case RF90_PATH_B:
  393. case RF90_PATH_D:
  394. u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
  395. BRFSI_RFENV << 16);
  396. break;
  397. }
  398. rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
  399. udelay(1);
  400. rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
  401. udelay(1);
  402. rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
  403. B3WIREADDREAALENGTH, 0x0);
  404. udelay(1);
  405. rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
  406. udelay(1);
  407. switch (rfpath) {
  408. case RF90_PATH_A:
  409. rtstatus = rtl8723e_phy_config_rf_with_headerfile(hw,
  410. (enum radio_path)rfpath);
  411. break;
  412. case RF90_PATH_B:
  413. rtstatus =
  414. rtl8723e_phy_config_rf_with_headerfile(hw,
  415. (enum radio_path)rfpath);
  416. break;
  417. case RF90_PATH_C:
  418. break;
  419. case RF90_PATH_D:
  420. break;
  421. }
  422. switch (rfpath) {
  423. case RF90_PATH_A:
  424. case RF90_PATH_C:
  425. rtl_set_bbreg(hw, pphyreg->rfintfs,
  426. BRFSI_RFENV, u4_regvalue);
  427. break;
  428. case RF90_PATH_B:
  429. case RF90_PATH_D:
  430. rtl_set_bbreg(hw, pphyreg->rfintfs,
  431. BRFSI_RFENV << 16, u4_regvalue);
  432. break;
  433. }
  434. if (rtstatus != true) {
  435. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  436. "Radio[%d] Fail!!\n", rfpath);
  437. return false;
  438. }
  439. }
  440. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
  441. return rtstatus;
  442. }