hw.c 75 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../efuse.h"
  27. #include "../base.h"
  28. #include "../regd.h"
  29. #include "../cam.h"
  30. #include "../ps.h"
  31. #include "../pci.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "phy.h"
  35. #include "../rtl8723com/phy_common.h"
  36. #include "dm.h"
  37. #include "../rtl8723com/dm_common.h"
  38. #include "fw.h"
  39. #include "../rtl8723com/fw_common.h"
  40. #include "led.h"
  41. #include "hw.h"
  42. #include "../pwrseqcmd.h"
  43. #include "pwrseq.h"
  44. #include "../btcoexist/rtl_btc.h"
  45. #include <linux/kernel.h>
  46. #define LLT_CONFIG 5
  47. static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
  48. {
  49. struct rtl_priv *rtlpriv = rtl_priv(hw);
  50. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  52. unsigned long flags;
  53. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54. while (skb_queue_len(&ring->queue)) {
  55. struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56. struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57. pci_unmap_single(rtlpci->pdev,
  58. rtlpriv->cfg->ops->get_desc(
  59. hw,
  60. (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  61. skb->len, PCI_DMA_TODEVICE);
  62. kfree_skb(skb);
  63. ring->idx = (ring->idx + 1) % ring->entries;
  64. }
  65. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  66. }
  67. static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  68. u8 set_bits, u8 clear_bits)
  69. {
  70. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  71. struct rtl_priv *rtlpriv = rtl_priv(hw);
  72. rtlpci->reg_bcn_ctrl_val |= set_bits;
  73. rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  74. rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  75. }
  76. static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
  77. {
  78. struct rtl_priv *rtlpriv = rtl_priv(hw);
  79. u8 tmp1byte;
  80. tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  81. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  82. rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  83. tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  84. tmp1byte &= ~(BIT(0));
  85. rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  86. }
  87. static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
  88. {
  89. struct rtl_priv *rtlpriv = rtl_priv(hw);
  90. u8 tmp1byte;
  91. tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  92. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  93. rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  94. tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  95. tmp1byte |= BIT(1);
  96. rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  97. }
  98. static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
  99. {
  100. _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
  101. }
  102. static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
  103. {
  104. _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
  105. }
  106. static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
  107. bool b_need_turn_off_ckk)
  108. {
  109. struct rtl_priv *rtlpriv = rtl_priv(hw);
  110. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  111. bool b_support_remote_wake_up;
  112. u32 count = 0, isr_regaddr, content;
  113. bool b_schedule_timer = b_need_turn_off_ckk;
  114. rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
  115. (u8 *)(&b_support_remote_wake_up));
  116. if (!rtlhal->fw_ready)
  117. return;
  118. if (!rtlpriv->psc.fw_current_inpsmode)
  119. return;
  120. while (1) {
  121. spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
  122. if (rtlhal->fw_clk_change_in_progress) {
  123. while (rtlhal->fw_clk_change_in_progress) {
  124. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  125. count++;
  126. udelay(100);
  127. if (count > 1000)
  128. return;
  129. spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
  130. }
  131. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  132. } else {
  133. rtlhal->fw_clk_change_in_progress = false;
  134. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  135. break;
  136. }
  137. }
  138. if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
  139. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
  140. (u8 *)(&rpwm_val));
  141. if (FW_PS_IS_ACK(rpwm_val)) {
  142. isr_regaddr = REG_HISR;
  143. content = rtl_read_dword(rtlpriv, isr_regaddr);
  144. while (!(content & IMR_CPWM) && (count < 500)) {
  145. udelay(50);
  146. count++;
  147. content = rtl_read_dword(rtlpriv, isr_regaddr);
  148. }
  149. if (content & IMR_CPWM) {
  150. rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
  151. rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
  152. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  153. "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
  154. rtlhal->fw_ps_state);
  155. }
  156. }
  157. spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
  158. rtlhal->fw_clk_change_in_progress = false;
  159. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  160. if (b_schedule_timer)
  161. mod_timer(&rtlpriv->works.fw_clockoff_timer,
  162. jiffies + MSECS(10));
  163. } else {
  164. spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
  165. rtlhal->fw_clk_change_in_progress = false;
  166. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  167. }
  168. }
  169. static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
  170. {
  171. struct rtl_priv *rtlpriv = rtl_priv(hw);
  172. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  173. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  174. struct rtl8192_tx_ring *ring;
  175. enum rf_pwrstate rtstate;
  176. bool b_schedule_timer = false;
  177. u8 queue;
  178. if (!rtlhal->fw_ready)
  179. return;
  180. if (!rtlpriv->psc.fw_current_inpsmode)
  181. return;
  182. if (!rtlhal->allow_sw_to_change_hwclc)
  183. return;
  184. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
  185. if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
  186. return;
  187. for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
  188. ring = &rtlpci->tx_ring[queue];
  189. if (skb_queue_len(&ring->queue)) {
  190. b_schedule_timer = true;
  191. break;
  192. }
  193. }
  194. if (b_schedule_timer) {
  195. mod_timer(&rtlpriv->works.fw_clockoff_timer,
  196. jiffies + MSECS(10));
  197. return;
  198. }
  199. if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
  200. spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
  201. if (!rtlhal->fw_clk_change_in_progress) {
  202. rtlhal->fw_clk_change_in_progress = true;
  203. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  204. rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
  205. rtl_write_word(rtlpriv, REG_HISR, 0x0100);
  206. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
  207. (u8 *)(&rpwm_val));
  208. spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
  209. rtlhal->fw_clk_change_in_progress = false;
  210. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  211. } else {
  212. spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
  213. mod_timer(&rtlpriv->works.fw_clockoff_timer,
  214. jiffies + MSECS(10));
  215. }
  216. }
  217. }
  218. static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
  219. {
  220. u8 rpwm_val = 0;
  221. rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
  222. _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
  223. }
  224. static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
  225. {
  226. struct rtl_priv *rtlpriv = rtl_priv(hw);
  227. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  228. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  229. bool fw_current_inps = false;
  230. u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
  231. if (ppsc->low_power_enable) {
  232. rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
  233. _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
  234. rtlhal->allow_sw_to_change_hwclc = false;
  235. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
  236. (u8 *)(&fw_pwrmode));
  237. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  238. (u8 *)(&fw_current_inps));
  239. } else {
  240. rpwm_val = FW_PS_STATE_ALL_ON; /* RF on */
  241. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
  242. (u8 *)(&rpwm_val));
  243. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
  244. (u8 *)(&fw_pwrmode));
  245. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  246. (u8 *)(&fw_current_inps));
  247. }
  248. }
  249. static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
  250. {
  251. struct rtl_priv *rtlpriv = rtl_priv(hw);
  252. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  253. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  254. bool fw_current_inps = true;
  255. u8 rpwm_val;
  256. if (ppsc->low_power_enable) {
  257. rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
  258. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  259. (u8 *)(&fw_current_inps));
  260. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
  261. (u8 *)(&ppsc->fwctrl_psmode));
  262. rtlhal->allow_sw_to_change_hwclc = true;
  263. _rtl8723be_set_fw_clock_off(hw, rpwm_val);
  264. } else {
  265. rpwm_val = FW_PS_STATE_RF_OFF; /* RF off */
  266. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  267. (u8 *)(&fw_current_inps));
  268. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
  269. (u8 *)(&ppsc->fwctrl_psmode));
  270. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
  271. (u8 *)(&rpwm_val));
  272. }
  273. }
  274. void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  275. {
  276. struct rtl_priv *rtlpriv = rtl_priv(hw);
  277. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  278. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  279. switch (variable) {
  280. case HW_VAR_RCR:
  281. *((u32 *)(val)) = rtlpci->receive_config;
  282. break;
  283. case HW_VAR_RF_STATE:
  284. *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  285. break;
  286. case HW_VAR_FWLPS_RF_ON:{
  287. enum rf_pwrstate rfState;
  288. u32 val_rcr;
  289. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
  290. (u8 *)(&rfState));
  291. if (rfState == ERFOFF) {
  292. *((bool *)(val)) = true;
  293. } else {
  294. val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
  295. val_rcr &= 0x00070000;
  296. if (val_rcr)
  297. *((bool *)(val)) = false;
  298. else
  299. *((bool *)(val)) = true;
  300. }
  301. }
  302. break;
  303. case HW_VAR_FW_PSMODE_STATUS:
  304. *((bool *)(val)) = ppsc->fw_current_inpsmode;
  305. break;
  306. case HW_VAR_CORRECT_TSF:{
  307. u64 tsf;
  308. u32 *ptsf_low = (u32 *)&tsf;
  309. u32 *ptsf_high = ((u32 *)&tsf) + 1;
  310. *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
  311. *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  312. *((u64 *)(val)) = tsf;
  313. }
  314. break;
  315. case HAL_DEF_WOWLAN:
  316. break;
  317. default:
  318. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  319. "switch case %#x not processed\n", variable);
  320. break;
  321. }
  322. }
  323. static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
  324. {
  325. struct rtl_priv *rtlpriv = rtl_priv(hw);
  326. u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
  327. u8 count = 0, dlbcn_count = 0;
  328. bool b_recover = false;
  329. tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
  330. rtl_write_byte(rtlpriv, REG_CR + 1,
  331. (tmp_regcr | BIT(0)));
  332. _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
  333. _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
  334. tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  335. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
  336. if (tmp_reg422 & BIT(6))
  337. b_recover = true;
  338. do {
  339. bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
  340. rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
  341. (bcnvalid_reg | BIT(0)));
  342. _rtl8723be_return_beacon_queue_skb(hw);
  343. rtl8723be_set_fw_rsvdpagepkt(hw, 0);
  344. bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
  345. count = 0;
  346. while (!(bcnvalid_reg & BIT(0)) && count < 20) {
  347. count++;
  348. udelay(10);
  349. bcnvalid_reg = rtl_read_byte(rtlpriv,
  350. REG_TDECTRL + 2);
  351. }
  352. dlbcn_count++;
  353. } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
  354. if (bcnvalid_reg & BIT(0))
  355. rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
  356. _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
  357. _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
  358. if (b_recover)
  359. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
  360. tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
  361. rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
  362. }
  363. void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  364. {
  365. struct rtl_priv *rtlpriv = rtl_priv(hw);
  366. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  367. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  368. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  369. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  370. u8 idx;
  371. switch (variable) {
  372. case HW_VAR_ETHER_ADDR:
  373. for (idx = 0; idx < ETH_ALEN; idx++)
  374. rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
  375. break;
  376. case HW_VAR_BASIC_RATE:{
  377. u16 b_rate_cfg = ((u16 *)val)[0];
  378. u8 rate_index = 0;
  379. b_rate_cfg = b_rate_cfg & 0x15f;
  380. b_rate_cfg |= 0x01;
  381. rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
  382. rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
  383. while (b_rate_cfg > 0x1) {
  384. b_rate_cfg = (b_rate_cfg >> 1);
  385. rate_index++;
  386. }
  387. rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
  388. }
  389. break;
  390. case HW_VAR_BSSID:
  391. for (idx = 0; idx < ETH_ALEN; idx++)
  392. rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
  393. break;
  394. case HW_VAR_SIFS:
  395. rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
  396. rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
  397. rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
  398. rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
  399. if (!mac->ht_enable)
  400. rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
  401. else
  402. rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
  403. *((u16 *)val));
  404. break;
  405. case HW_VAR_SLOT_TIME:{
  406. u8 e_aci;
  407. RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
  408. "HW_VAR_SLOT_TIME %x\n", val[0]);
  409. rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
  410. for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
  411. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  412. (u8 *)(&e_aci));
  413. }
  414. }
  415. break;
  416. case HW_VAR_ACK_PREAMBLE:{
  417. u8 reg_tmp;
  418. u8 short_preamble = (bool)(*(u8 *)val);
  419. reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
  420. if (short_preamble) {
  421. reg_tmp |= 0x02;
  422. rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
  423. } else {
  424. reg_tmp &= 0xFD;
  425. rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
  426. }
  427. }
  428. break;
  429. case HW_VAR_WPA_CONFIG:
  430. rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
  431. break;
  432. case HW_VAR_AMPDU_MIN_SPACE:{
  433. u8 min_spacing_to_set;
  434. u8 sec_min_space;
  435. min_spacing_to_set = *((u8 *)val);
  436. if (min_spacing_to_set <= 7) {
  437. sec_min_space = 0;
  438. if (min_spacing_to_set < sec_min_space)
  439. min_spacing_to_set = sec_min_space;
  440. mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
  441. min_spacing_to_set);
  442. *val = min_spacing_to_set;
  443. RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
  444. "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
  445. mac->min_space_cfg);
  446. rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
  447. mac->min_space_cfg);
  448. }
  449. }
  450. break;
  451. case HW_VAR_SHORTGI_DENSITY:{
  452. u8 density_to_set;
  453. density_to_set = *((u8 *)val);
  454. mac->min_space_cfg |= (density_to_set << 3);
  455. RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
  456. "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
  457. mac->min_space_cfg);
  458. rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
  459. mac->min_space_cfg);
  460. }
  461. break;
  462. case HW_VAR_AMPDU_FACTOR:{
  463. u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
  464. u8 factor_toset;
  465. u8 *p_regtoset = NULL;
  466. u8 index = 0;
  467. p_regtoset = regtoset_normal;
  468. factor_toset = *((u8 *)val);
  469. if (factor_toset <= 3) {
  470. factor_toset = (1 << (factor_toset + 2));
  471. if (factor_toset > 0xf)
  472. factor_toset = 0xf;
  473. for (index = 0; index < 4; index++) {
  474. if ((p_regtoset[index] & 0xf0) >
  475. (factor_toset << 4))
  476. p_regtoset[index] =
  477. (p_regtoset[index] & 0x0f) |
  478. (factor_toset << 4);
  479. if ((p_regtoset[index] & 0x0f) > factor_toset)
  480. p_regtoset[index] =
  481. (p_regtoset[index] & 0xf0) |
  482. (factor_toset);
  483. rtl_write_byte(rtlpriv,
  484. (REG_AGGLEN_LMT + index),
  485. p_regtoset[index]);
  486. }
  487. RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
  488. "Set HW_VAR_AMPDU_FACTOR: %#x\n",
  489. factor_toset);
  490. }
  491. }
  492. break;
  493. case HW_VAR_AC_PARAM:{
  494. u8 e_aci = *((u8 *)val);
  495. rtl8723_dm_init_edca_turbo(hw);
  496. if (rtlpci->acm_method != EACMWAY2_SW)
  497. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
  498. (u8 *)(&e_aci));
  499. }
  500. break;
  501. case HW_VAR_ACM_CTRL:{
  502. u8 e_aci = *((u8 *)val);
  503. union aci_aifsn *p_aci_aifsn =
  504. (union aci_aifsn *)(&(mac->ac[0].aifs));
  505. u8 acm = p_aci_aifsn->f.acm;
  506. u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
  507. acm_ctrl =
  508. acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
  509. if (acm) {
  510. switch (e_aci) {
  511. case AC0_BE:
  512. acm_ctrl |= ACMHW_BEQEN;
  513. break;
  514. case AC2_VI:
  515. acm_ctrl |= ACMHW_VIQEN;
  516. break;
  517. case AC3_VO:
  518. acm_ctrl |= ACMHW_VOQEN;
  519. break;
  520. default:
  521. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  522. "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
  523. acm);
  524. break;
  525. }
  526. } else {
  527. switch (e_aci) {
  528. case AC0_BE:
  529. acm_ctrl &= (~ACMHW_BEQEN);
  530. break;
  531. case AC2_VI:
  532. acm_ctrl &= (~ACMHW_VIQEN);
  533. break;
  534. case AC3_VO:
  535. acm_ctrl &= (~ACMHW_VOQEN);
  536. break;
  537. default:
  538. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  539. "switch case %#x not processed\n",
  540. e_aci);
  541. break;
  542. }
  543. }
  544. RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
  545. "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
  546. acm_ctrl);
  547. rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
  548. }
  549. break;
  550. case HW_VAR_RCR:
  551. rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
  552. rtlpci->receive_config = ((u32 *)(val))[0];
  553. break;
  554. case HW_VAR_RETRY_LIMIT:{
  555. u8 retry_limit = ((u8 *)(val))[0];
  556. rtl_write_word(rtlpriv, REG_RL,
  557. retry_limit << RETRY_LIMIT_SHORT_SHIFT |
  558. retry_limit << RETRY_LIMIT_LONG_SHIFT);
  559. }
  560. break;
  561. case HW_VAR_DUAL_TSF_RST:
  562. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
  563. break;
  564. case HW_VAR_EFUSE_BYTES:
  565. rtlefuse->efuse_usedbytes = *((u16 *)val);
  566. break;
  567. case HW_VAR_EFUSE_USAGE:
  568. rtlefuse->efuse_usedpercentage = *((u8 *)val);
  569. break;
  570. case HW_VAR_IO_CMD:
  571. rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
  572. break;
  573. case HW_VAR_SET_RPWM:{
  574. u8 rpwm_val;
  575. rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
  576. udelay(1);
  577. if (rpwm_val & BIT(7)) {
  578. rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
  579. } else {
  580. rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
  581. ((*(u8 *)val) | BIT(7)));
  582. }
  583. }
  584. break;
  585. case HW_VAR_H2C_FW_PWRMODE:
  586. rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
  587. break;
  588. case HW_VAR_FW_PSMODE_STATUS:
  589. ppsc->fw_current_inpsmode = *((bool *)val);
  590. break;
  591. case HW_VAR_RESUME_CLK_ON:
  592. _rtl8723be_set_fw_ps_rf_on(hw);
  593. break;
  594. case HW_VAR_FW_LPS_ACTION:{
  595. bool b_enter_fwlps = *((bool *)val);
  596. if (b_enter_fwlps)
  597. _rtl8723be_fwlps_enter(hw);
  598. else
  599. _rtl8723be_fwlps_leave(hw);
  600. }
  601. break;
  602. case HW_VAR_H2C_FW_JOINBSSRPT:{
  603. u8 mstatus = (*(u8 *)val);
  604. if (mstatus == RT_MEDIA_CONNECT) {
  605. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
  606. _rtl8723be_download_rsvd_page(hw);
  607. }
  608. rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
  609. }
  610. break;
  611. case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
  612. rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
  613. break;
  614. case HW_VAR_AID:{
  615. u16 u2btmp;
  616. u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
  617. u2btmp &= 0xC000;
  618. rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
  619. (u2btmp | mac->assoc_id));
  620. }
  621. break;
  622. case HW_VAR_CORRECT_TSF:{
  623. u8 btype_ibss = ((u8 *)(val))[0];
  624. if (btype_ibss)
  625. _rtl8723be_stop_tx_beacon(hw);
  626. _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
  627. rtl_write_dword(rtlpriv, REG_TSFTR,
  628. (u32) (mac->tsf & 0xffffffff));
  629. rtl_write_dword(rtlpriv, REG_TSFTR + 4,
  630. (u32) ((mac->tsf >> 32) & 0xffffffff));
  631. _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
  632. if (btype_ibss)
  633. _rtl8723be_resume_tx_beacon(hw);
  634. }
  635. break;
  636. case HW_VAR_KEEP_ALIVE:{
  637. u8 array[2];
  638. array[0] = 0xff;
  639. array[1] = *((u8 *)val);
  640. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
  641. }
  642. break;
  643. default:
  644. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  645. "switch case %#x not processed\n", variable);
  646. break;
  647. }
  648. }
  649. static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
  650. {
  651. struct rtl_priv *rtlpriv = rtl_priv(hw);
  652. bool status = true;
  653. long count = 0;
  654. u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
  655. _LLT_OP(_LLT_WRITE_ACCESS);
  656. rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
  657. do {
  658. value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
  659. if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
  660. break;
  661. if (count > POLLING_LLT_THRESHOLD) {
  662. pr_err("Failed to polling write LLT done at address %d!\n",
  663. address);
  664. status = false;
  665. break;
  666. }
  667. } while (++count);
  668. return status;
  669. }
  670. static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
  671. {
  672. struct rtl_priv *rtlpriv = rtl_priv(hw);
  673. unsigned short i;
  674. u8 txpktbuf_bndy;
  675. u8 maxPage;
  676. bool status;
  677. maxPage = 255;
  678. txpktbuf_bndy = 245;
  679. rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
  680. (0x27FF0000 | txpktbuf_bndy));
  681. rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
  682. rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
  683. rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
  684. rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
  685. rtl_write_byte(rtlpriv, REG_PBP, 0x31);
  686. rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
  687. for (i = 0; i < (txpktbuf_bndy - 1); i++) {
  688. status = _rtl8723be_llt_write(hw, i, i + 1);
  689. if (!status)
  690. return status;
  691. }
  692. status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
  693. if (!status)
  694. return status;
  695. for (i = txpktbuf_bndy; i < maxPage; i++) {
  696. status = _rtl8723be_llt_write(hw, i, (i + 1));
  697. if (!status)
  698. return status;
  699. }
  700. status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
  701. if (!status)
  702. return status;
  703. rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
  704. rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
  705. return true;
  706. }
  707. static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
  708. {
  709. struct rtl_priv *rtlpriv = rtl_priv(hw);
  710. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  711. struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
  712. if (rtlpriv->rtlhal.up_first_time)
  713. return;
  714. if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
  715. rtl8723be_sw_led_on(hw, pled0);
  716. else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
  717. rtl8723be_sw_led_on(hw, pled0);
  718. else
  719. rtl8723be_sw_led_off(hw, pled0);
  720. }
  721. static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
  722. {
  723. struct rtl_priv *rtlpriv = rtl_priv(hw);
  724. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  725. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  726. unsigned char bytetmp;
  727. unsigned short wordtmp;
  728. rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
  729. /*Auto Power Down to CHIP-off State*/
  730. bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
  731. rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
  732. /* HW Power on sequence */
  733. if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
  734. PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
  735. RTL8723_NIC_ENABLE_FLOW)) {
  736. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  737. "init MAC Fail as power on failure\n");
  738. return false;
  739. }
  740. if (rtlpriv->cfg->ops->get_btc_status())
  741. rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
  742. bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
  743. rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
  744. bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
  745. rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
  746. bytetmp = rtl_read_byte(rtlpriv, REG_CR);
  747. bytetmp = 0xff;
  748. rtl_write_byte(rtlpriv, REG_CR, bytetmp);
  749. mdelay(2);
  750. bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
  751. bytetmp |= 0x7f;
  752. rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
  753. mdelay(2);
  754. bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
  755. if (bytetmp & BIT(0)) {
  756. bytetmp = rtl_read_byte(rtlpriv, 0x7c);
  757. rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
  758. }
  759. bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
  760. rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
  761. bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
  762. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
  763. rtl_write_word(rtlpriv, REG_CR, 0x2ff);
  764. if (!rtlhal->mac_func_enable) {
  765. if (_rtl8723be_llt_table_init(hw) == false)
  766. return false;
  767. }
  768. rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
  769. rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
  770. /* Enable FW Beamformer Interrupt */
  771. bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
  772. rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
  773. wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
  774. wordtmp &= 0xf;
  775. wordtmp |= 0xF5B1;
  776. rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
  777. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
  778. rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
  779. rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
  780. rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
  781. rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
  782. ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
  783. DMA_BIT_MASK(32));
  784. rtl_write_dword(rtlpriv, REG_MGQ_DESA,
  785. (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
  786. DMA_BIT_MASK(32));
  787. rtl_write_dword(rtlpriv, REG_VOQ_DESA,
  788. (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
  789. rtl_write_dword(rtlpriv, REG_VIQ_DESA,
  790. (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
  791. rtl_write_dword(rtlpriv, REG_BEQ_DESA,
  792. (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
  793. rtl_write_dword(rtlpriv, REG_BKQ_DESA,
  794. (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
  795. rtl_write_dword(rtlpriv, REG_HQ_DESA,
  796. (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
  797. DMA_BIT_MASK(32));
  798. rtl_write_dword(rtlpriv, REG_RX_DESA,
  799. (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
  800. DMA_BIT_MASK(32));
  801. bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
  802. rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
  803. rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
  804. rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
  805. rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
  806. /* <20130114, Kordan> The following setting is
  807. * only for DPDT and Fixed board type.
  808. * TODO: A better solution is configure it
  809. * according EFUSE during the run-time.
  810. */
  811. rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
  812. rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
  813. rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
  814. rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
  815. rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
  816. rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
  817. rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
  818. rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
  819. bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
  820. rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
  821. _rtl8723be_gen_refresh_led_state(hw);
  822. return true;
  823. }
  824. static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
  825. {
  826. struct rtl_priv *rtlpriv = rtl_priv(hw);
  827. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  828. u32 reg_rrsr;
  829. reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
  830. /* Init value for RRSR. */
  831. rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
  832. /* ARFB table 9 for 11ac 5G 2SS */
  833. rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
  834. /* ARFB table 10 for 11ac 5G 1SS */
  835. rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
  836. /* CF-End setting. */
  837. rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
  838. /* 0x456 = 0x70, sugguested by Zhilin */
  839. rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
  840. /* Set retry limit */
  841. rtl_write_word(rtlpriv, REG_RL, 0x0707);
  842. /* Set Data / Response auto rate fallack retry count */
  843. rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
  844. rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
  845. rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
  846. rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
  847. rtlpci->reg_bcn_ctrl_val = 0x1d;
  848. rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
  849. /* TBTT prohibit hold time. Suggested by designer TimChen. */
  850. rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
  851. rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
  852. /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
  853. rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
  854. rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
  855. rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
  856. rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
  857. }
  858. static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
  859. {
  860. u16 read_addr = addr & 0xfffc;
  861. u8 ret = 0, tmp = 0, count = 0;
  862. rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
  863. rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
  864. tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
  865. count = 0;
  866. while (tmp && count < 20) {
  867. udelay(10);
  868. tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
  869. count++;
  870. }
  871. if (0 == tmp) {
  872. read_addr = REG_DBI_RDATA + addr % 4;
  873. ret = rtl_read_byte(rtlpriv, read_addr);
  874. }
  875. return ret;
  876. }
  877. static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
  878. {
  879. u8 tmp = 0, count = 0;
  880. u16 write_addr = 0, remainder = addr % 4;
  881. /* Write DBI 1Byte Data */
  882. write_addr = REG_DBI_WDATA + remainder;
  883. rtl_write_byte(rtlpriv, write_addr, data);
  884. /* Write DBI 2Byte Address & Write Enable */
  885. write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
  886. rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
  887. /* Write DBI Write Flag */
  888. rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
  889. tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
  890. count = 0;
  891. while (tmp && count < 20) {
  892. udelay(10);
  893. tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
  894. count++;
  895. }
  896. }
  897. static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
  898. {
  899. u16 ret = 0;
  900. u8 tmp = 0, count = 0;
  901. rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
  902. tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
  903. count = 0;
  904. while (tmp && count < 20) {
  905. udelay(10);
  906. tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
  907. count++;
  908. }
  909. if (0 == tmp)
  910. ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
  911. return ret;
  912. }
  913. static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
  914. {
  915. u8 tmp = 0, count = 0;
  916. rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
  917. rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
  918. tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
  919. count = 0;
  920. while (tmp && count < 20) {
  921. udelay(10);
  922. tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
  923. count++;
  924. }
  925. }
  926. static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
  927. {
  928. struct rtl_priv *rtlpriv = rtl_priv(hw);
  929. u8 tmp8 = 0;
  930. u16 tmp16 = 0;
  931. /* <Roger_Notes> Overwrite following ePHY parameter for
  932. * some platform compatibility issue,
  933. * especially when CLKReq is enabled, 2012.11.09.
  934. */
  935. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
  936. if (tmp16 != 0x0663)
  937. _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
  938. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
  939. if (tmp16 != 0x7544)
  940. _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
  941. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
  942. if (tmp16 != 0xB880)
  943. _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
  944. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
  945. if (tmp16 != 0x4000)
  946. _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
  947. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
  948. if (tmp16 != 0x9003)
  949. _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
  950. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
  951. if (tmp16 != 0x0D03)
  952. _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
  953. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
  954. if (tmp16 != 0x4037)
  955. _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
  956. tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
  957. if (tmp16 != 0x0070)
  958. _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
  959. /* Configuration Space offset 0x70f BIT7 is used to control L0S */
  960. tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
  961. _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
  962. ASPM_L1_LATENCY << 3);
  963. /* Configuration Space offset 0x719 Bit3 is for L1
  964. * BIT4 is for clock request
  965. */
  966. tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
  967. _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
  968. }
  969. void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
  970. {
  971. struct rtl_priv *rtlpriv = rtl_priv(hw);
  972. u8 sec_reg_value;
  973. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  974. "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
  975. rtlpriv->sec.pairwise_enc_algorithm,
  976. rtlpriv->sec.group_enc_algorithm);
  977. if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
  978. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  979. "not open hw encryption\n");
  980. return;
  981. }
  982. sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
  983. if (rtlpriv->sec.use_defaultkey) {
  984. sec_reg_value |= SCR_TXUSEDK;
  985. sec_reg_value |= SCR_RXUSEDK;
  986. }
  987. sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
  988. rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
  989. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  990. "The SECR-value %x\n", sec_reg_value);
  991. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
  992. }
  993. static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
  994. {
  995. struct rtl_priv *rtlpriv = rtl_priv(hw);
  996. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  997. u8 u1b_tmp;
  998. rtlhal->mac_func_enable = false;
  999. /* Combo (PCIe + USB) Card and PCIe-MF Card */
  1000. /* 1. Run LPS WL RFOFF flow */
  1001. rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
  1002. PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
  1003. /* 2. 0x1F[7:0] = 0 */
  1004. /* turn off RF */
  1005. /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
  1006. if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
  1007. rtlhal->fw_ready) {
  1008. rtl8723be_firmware_selfreset(hw);
  1009. }
  1010. /* Reset MCU. Suggested by Filen. */
  1011. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  1012. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
  1013. /* g. MCUFWDL 0x80[1:0]=0 */
  1014. /* reset MCU ready status */
  1015. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
  1016. /* HW card disable configuration. */
  1017. rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
  1018. PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
  1019. /* Reset MCU IO Wrapper */
  1020. u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
  1021. rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
  1022. u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
  1023. rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
  1024. /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
  1025. /* lock ISO/CLK/Power control register */
  1026. rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
  1027. }
  1028. static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
  1029. {
  1030. u8 tmp;
  1031. /* write reg 0x350 Bit[26]=1. Enable debug port. */
  1032. tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
  1033. if (!(tmp & BIT(2))) {
  1034. rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
  1035. mdelay(100); /* Suggested by DD Justin_tsai. */
  1036. }
  1037. /* read reg 0x350 Bit[25] if 1 : RX hang
  1038. * read reg 0x350 Bit[24] if 1 : TX hang
  1039. */
  1040. tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
  1041. if ((tmp & BIT(0)) || (tmp & BIT(1))) {
  1042. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  1043. "CheckPcieDMAHang8723BE(): true!!\n");
  1044. return true;
  1045. }
  1046. return false;
  1047. }
  1048. static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
  1049. bool mac_power_on)
  1050. {
  1051. u8 tmp;
  1052. bool release_mac_rx_pause;
  1053. u8 backup_pcie_dma_pause;
  1054. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  1055. "ResetPcieInterfaceDMA8723BE()\n");
  1056. /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
  1057. * released by SD1 Alan.
  1058. * 2013.05.07, by tynli.
  1059. */
  1060. /* 1. disable register write lock
  1061. * write 0x1C bit[1:0] = 2'h0
  1062. * write 0xCC bit[2] = 1'b1
  1063. */
  1064. tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
  1065. tmp &= ~(BIT(1) | BIT(0));
  1066. rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
  1067. tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
  1068. tmp |= BIT(2);
  1069. rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
  1070. /* 2. Check and pause TRX DMA
  1071. * write 0x284 bit[18] = 1'b1
  1072. * write 0x301 = 0xFF
  1073. */
  1074. tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
  1075. if (tmp & BIT(2)) {
  1076. /* Already pause before the function for another purpose. */
  1077. release_mac_rx_pause = false;
  1078. } else {
  1079. rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
  1080. release_mac_rx_pause = true;
  1081. }
  1082. backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
  1083. if (backup_pcie_dma_pause != 0xFF)
  1084. rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
  1085. if (mac_power_on) {
  1086. /* 3. reset TRX function
  1087. * write 0x100 = 0x00
  1088. */
  1089. rtl_write_byte(rtlpriv, REG_CR, 0);
  1090. }
  1091. /* 4. Reset PCIe DMA
  1092. * write 0x003 bit[0] = 0
  1093. */
  1094. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  1095. tmp &= ~(BIT(0));
  1096. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
  1097. /* 5. Enable PCIe DMA
  1098. * write 0x003 bit[0] = 1
  1099. */
  1100. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  1101. tmp |= BIT(0);
  1102. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
  1103. if (mac_power_on) {
  1104. /* 6. enable TRX function
  1105. * write 0x100 = 0xFF
  1106. */
  1107. rtl_write_byte(rtlpriv, REG_CR, 0xFF);
  1108. /* We should init LLT & RQPN and
  1109. * prepare Tx/Rx descrptor address later
  1110. * because MAC function is reset.
  1111. */
  1112. }
  1113. /* 7. Restore PCIe autoload down bit
  1114. * write 0xF8 bit[17] = 1'b1
  1115. */
  1116. tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
  1117. tmp |= BIT(1);
  1118. rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
  1119. /* In MAC power on state, BB and RF maybe in ON state,
  1120. * if we release TRx DMA here
  1121. * it will cause packets to be started to Tx/Rx,
  1122. * so we release Tx/Rx DMA later.
  1123. */
  1124. if (!mac_power_on) {
  1125. /* 8. release TRX DMA
  1126. * write 0x284 bit[18] = 1'b0
  1127. * write 0x301 = 0x00
  1128. */
  1129. if (release_mac_rx_pause) {
  1130. tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
  1131. rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
  1132. (tmp & (~BIT(2))));
  1133. }
  1134. rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
  1135. backup_pcie_dma_pause);
  1136. }
  1137. /* 9. lock system register
  1138. * write 0xCC bit[2] = 1'b0
  1139. */
  1140. tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
  1141. tmp &= ~(BIT(2));
  1142. rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
  1143. }
  1144. int rtl8723be_hw_init(struct ieee80211_hw *hw)
  1145. {
  1146. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1147. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1148. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1149. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1150. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1151. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1152. bool rtstatus = true;
  1153. int err;
  1154. u8 tmp_u1b;
  1155. unsigned long flags;
  1156. /* reenable interrupts to not interfere with other devices */
  1157. local_save_flags(flags);
  1158. local_irq_enable();
  1159. rtlhal->fw_ready = false;
  1160. rtlpriv->rtlhal.being_init_adapter = true;
  1161. rtlpriv->intf_ops->disable_aspm(hw);
  1162. tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
  1163. if (tmp_u1b != 0 && tmp_u1b != 0xea) {
  1164. rtlhal->mac_func_enable = true;
  1165. } else {
  1166. rtlhal->mac_func_enable = false;
  1167. rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
  1168. }
  1169. if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
  1170. _rtl8723be_reset_pcie_interface_dma(rtlpriv,
  1171. rtlhal->mac_func_enable);
  1172. rtlhal->mac_func_enable = false;
  1173. }
  1174. if (rtlhal->mac_func_enable) {
  1175. _rtl8723be_poweroff_adapter(hw);
  1176. rtlhal->mac_func_enable = false;
  1177. }
  1178. rtstatus = _rtl8723be_init_mac(hw);
  1179. if (!rtstatus) {
  1180. pr_err("Init MAC failed\n");
  1181. err = 1;
  1182. goto exit;
  1183. }
  1184. tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
  1185. rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
  1186. err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
  1187. if (err) {
  1188. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1189. "Failed to download FW. Init HW without FW now..\n");
  1190. err = 1;
  1191. goto exit;
  1192. }
  1193. rtlhal->fw_ready = true;
  1194. rtlhal->last_hmeboxnum = 0;
  1195. rtl8723be_phy_mac_config(hw);
  1196. /* because last function modify RCR, so we update
  1197. * rcr var here, or TP will unstable for receive_config
  1198. * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
  1199. * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
  1200. */
  1201. rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
  1202. rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
  1203. rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
  1204. rtl8723be_phy_bb_config(hw);
  1205. rtl8723be_phy_rf_config(hw);
  1206. rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
  1207. RF_CHNLBW, RFREG_OFFSET_MASK);
  1208. rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
  1209. RF_CHNLBW, RFREG_OFFSET_MASK);
  1210. rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
  1211. rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
  1212. _rtl8723be_hw_configure(hw);
  1213. rtlhal->mac_func_enable = true;
  1214. rtl_cam_reset_all_entry(hw);
  1215. rtl8723be_enable_hw_security_config(hw);
  1216. ppsc->rfpwr_state = ERFON;
  1217. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
  1218. _rtl8723be_enable_aspm_back_door(hw);
  1219. rtlpriv->intf_ops->enable_aspm(hw);
  1220. rtl8723be_bt_hw_init(hw);
  1221. if (ppsc->rfpwr_state == ERFON) {
  1222. rtl8723be_phy_set_rfpath_switch(hw, 1);
  1223. /* when use 1ant NIC, iqk will disturb BT music
  1224. * root cause is not clear now, is something
  1225. * related with 'mdelay' and Reg[0x948]
  1226. */
  1227. if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
  1228. !rtlpriv->cfg->ops->get_btc_status()) {
  1229. rtl8723be_phy_iq_calibrate(hw,
  1230. (rtlphy->iqk_initialized ?
  1231. true : false));
  1232. rtlphy->iqk_initialized = true;
  1233. }
  1234. rtl8723be_dm_check_txpower_tracking(hw);
  1235. rtl8723be_phy_lc_calibrate(hw);
  1236. }
  1237. rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
  1238. /* Release Rx DMA. */
  1239. tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
  1240. if (tmp_u1b & BIT(2)) {
  1241. /* Release Rx DMA if needed */
  1242. tmp_u1b &= (~BIT(2));
  1243. rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
  1244. }
  1245. /* Release Tx/Rx PCIE DMA. */
  1246. rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
  1247. rtl8723be_dm_init(hw);
  1248. exit:
  1249. local_irq_restore(flags);
  1250. rtlpriv->rtlhal.being_init_adapter = false;
  1251. return err;
  1252. }
  1253. static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
  1254. {
  1255. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1256. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1257. enum version_8723e version = VERSION_UNKNOWN;
  1258. u32 value32;
  1259. value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
  1260. if ((value32 & (CHIP_8723B)) != CHIP_8723B)
  1261. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
  1262. else
  1263. version = (enum version_8723e)CHIP_8723B;
  1264. rtlphy->rf_type = RF_1T1R;
  1265. /* treat rtl8723be chip as MP version in default */
  1266. version = (enum version_8723e)(version | NORMAL_CHIP);
  1267. value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
  1268. /* cut version */
  1269. version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
  1270. /* Manufacture */
  1271. if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
  1272. version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
  1273. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  1274. "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
  1275. "RF_2T2R" : "RF_1T1R");
  1276. return version;
  1277. }
  1278. static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
  1279. enum nl80211_iftype type)
  1280. {
  1281. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1282. u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
  1283. enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
  1284. u8 mode = MSR_NOLINK;
  1285. switch (type) {
  1286. case NL80211_IFTYPE_UNSPECIFIED:
  1287. mode = MSR_NOLINK;
  1288. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  1289. "Set Network type to NO LINK!\n");
  1290. break;
  1291. case NL80211_IFTYPE_ADHOC:
  1292. case NL80211_IFTYPE_MESH_POINT:
  1293. mode = MSR_ADHOC;
  1294. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  1295. "Set Network type to Ad Hoc!\n");
  1296. break;
  1297. case NL80211_IFTYPE_STATION:
  1298. mode = MSR_INFRA;
  1299. ledaction = LED_CTL_LINK;
  1300. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  1301. "Set Network type to STA!\n");
  1302. break;
  1303. case NL80211_IFTYPE_AP:
  1304. mode = MSR_AP;
  1305. ledaction = LED_CTL_LINK;
  1306. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  1307. "Set Network type to AP!\n");
  1308. break;
  1309. default:
  1310. pr_err("Network type %d not support!\n", type);
  1311. return 1;
  1312. }
  1313. /* MSR_INFRA == Link in infrastructure network;
  1314. * MSR_ADHOC == Link in ad hoc network;
  1315. * Therefore, check link state is necessary.
  1316. *
  1317. * MSR_AP == AP mode; link state is not cared here.
  1318. */
  1319. if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1320. mode = MSR_NOLINK;
  1321. ledaction = LED_CTL_NO_LINK;
  1322. }
  1323. if (mode == MSR_NOLINK || mode == MSR_INFRA) {
  1324. _rtl8723be_stop_tx_beacon(hw);
  1325. _rtl8723be_enable_bcn_sub_func(hw);
  1326. } else if (mode == MSR_ADHOC || mode == MSR_AP) {
  1327. _rtl8723be_resume_tx_beacon(hw);
  1328. _rtl8723be_disable_bcn_sub_func(hw);
  1329. } else {
  1330. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1331. "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
  1332. mode);
  1333. }
  1334. rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
  1335. rtlpriv->cfg->ops->led_control(hw, ledaction);
  1336. if (mode == MSR_AP)
  1337. rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
  1338. else
  1339. rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
  1340. return 0;
  1341. }
  1342. void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
  1343. {
  1344. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1345. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1346. u32 reg_rcr = rtlpci->receive_config;
  1347. if (rtlpriv->psc.rfpwr_state != ERFON)
  1348. return;
  1349. if (check_bssid) {
  1350. reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
  1351. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
  1352. (u8 *)(&reg_rcr));
  1353. _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
  1354. } else if (!check_bssid) {
  1355. reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
  1356. _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
  1357. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
  1358. (u8 *)(&reg_rcr));
  1359. }
  1360. }
  1361. int rtl8723be_set_network_type(struct ieee80211_hw *hw,
  1362. enum nl80211_iftype type)
  1363. {
  1364. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1365. if (_rtl8723be_set_media_status(hw, type))
  1366. return -EOPNOTSUPP;
  1367. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1368. if (type != NL80211_IFTYPE_AP)
  1369. rtl8723be_set_check_bssid(hw, true);
  1370. } else {
  1371. rtl8723be_set_check_bssid(hw, false);
  1372. }
  1373. return 0;
  1374. }
  1375. /* don't set REG_EDCA_BE_PARAM here
  1376. * because mac80211 will send pkt when scan
  1377. */
  1378. void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
  1379. {
  1380. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1381. rtl8723_dm_init_edca_turbo(hw);
  1382. switch (aci) {
  1383. case AC1_BK:
  1384. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
  1385. break;
  1386. case AC0_BE:
  1387. break;
  1388. case AC2_VI:
  1389. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
  1390. break;
  1391. case AC3_VO:
  1392. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
  1393. break;
  1394. default:
  1395. WARN_ONCE(true, "rtl8723be: invalid aci: %d !\n", aci);
  1396. break;
  1397. }
  1398. }
  1399. void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
  1400. {
  1401. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1402. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1403. rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
  1404. rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
  1405. rtlpci->irq_enabled = true;
  1406. /*enable system interrupt*/
  1407. rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
  1408. }
  1409. void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
  1410. {
  1411. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1412. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1413. rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
  1414. rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
  1415. rtlpci->irq_enabled = false;
  1416. /*synchronize_irq(rtlpci->pdev->irq);*/
  1417. }
  1418. void rtl8723be_card_disable(struct ieee80211_hw *hw)
  1419. {
  1420. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1421. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1422. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1423. enum nl80211_iftype opmode;
  1424. mac->link_state = MAC80211_NOLINK;
  1425. opmode = NL80211_IFTYPE_UNSPECIFIED;
  1426. _rtl8723be_set_media_status(hw, opmode);
  1427. if (rtlpriv->rtlhal.driver_is_goingto_unload ||
  1428. ppsc->rfoff_reason > RF_CHANGE_BY_PS)
  1429. rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
  1430. RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
  1431. _rtl8723be_poweroff_adapter(hw);
  1432. /* after power off we should do iqk again */
  1433. if (!rtlpriv->cfg->ops->get_btc_status())
  1434. rtlpriv->phy.iqk_initialized = false;
  1435. }
  1436. void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
  1437. struct rtl_int *intvec)
  1438. {
  1439. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1440. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1441. intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
  1442. rtl_write_dword(rtlpriv, ISR, intvec->inta);
  1443. intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) &
  1444. rtlpci->irq_mask[1];
  1445. rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
  1446. }
  1447. void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
  1448. {
  1449. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1450. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1451. u16 bcn_interval, atim_window;
  1452. bcn_interval = mac->beacon_interval;
  1453. atim_window = 2; /*FIX MERGE */
  1454. rtl8723be_disable_interrupt(hw);
  1455. rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
  1456. rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
  1457. rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
  1458. rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
  1459. rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
  1460. rtl_write_byte(rtlpriv, 0x606, 0x30);
  1461. rtl8723be_enable_interrupt(hw);
  1462. }
  1463. void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
  1464. {
  1465. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1466. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1467. u16 bcn_interval = mac->beacon_interval;
  1468. RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
  1469. "beacon_interval:%d\n", bcn_interval);
  1470. rtl8723be_disable_interrupt(hw);
  1471. rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
  1472. rtl8723be_enable_interrupt(hw);
  1473. }
  1474. void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
  1475. u32 add_msr, u32 rm_msr)
  1476. {
  1477. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1478. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1479. RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
  1480. "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
  1481. if (add_msr)
  1482. rtlpci->irq_mask[0] |= add_msr;
  1483. if (rm_msr)
  1484. rtlpci->irq_mask[0] &= (~rm_msr);
  1485. rtl8723be_disable_interrupt(hw);
  1486. rtl8723be_enable_interrupt(hw);
  1487. }
  1488. static u8 _rtl8723be_get_chnl_group(u8 chnl)
  1489. {
  1490. u8 group;
  1491. if (chnl < 3)
  1492. group = 0;
  1493. else if (chnl < 9)
  1494. group = 1;
  1495. else
  1496. group = 2;
  1497. return group;
  1498. }
  1499. static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
  1500. struct txpower_info_2g *pw2g,
  1501. struct txpower_info_5g *pw5g,
  1502. bool autoload_fail, u8 *hwinfo)
  1503. {
  1504. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1505. u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
  1506. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  1507. "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
  1508. (addr + 1), hwinfo[addr + 1]);
  1509. if (0xFF == hwinfo[addr + 1]) /*YJ,add,120316*/
  1510. autoload_fail = true;
  1511. if (autoload_fail) {
  1512. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  1513. "auto load fail : Use Default value!\n");
  1514. for (path = 0; path < MAX_RF_PATH; path++) {
  1515. /* 2.4G default value */
  1516. for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
  1517. pw2g->index_cck_base[path][group] = 0x2D;
  1518. pw2g->index_bw40_base[path][group] = 0x2D;
  1519. }
  1520. for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
  1521. if (cnt == 0) {
  1522. pw2g->bw20_diff[path][0] = 0x02;
  1523. pw2g->ofdm_diff[path][0] = 0x04;
  1524. } else {
  1525. pw2g->bw20_diff[path][cnt] = 0xFE;
  1526. pw2g->bw40_diff[path][cnt] = 0xFE;
  1527. pw2g->cck_diff[path][cnt] = 0xFE;
  1528. pw2g->ofdm_diff[path][cnt] = 0xFE;
  1529. }
  1530. }
  1531. }
  1532. return;
  1533. }
  1534. for (path = 0; path < MAX_RF_PATH; path++) {
  1535. /*2.4G default value*/
  1536. for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
  1537. pw2g->index_cck_base[path][group] = hwinfo[addr++];
  1538. if (pw2g->index_cck_base[path][group] == 0xFF)
  1539. pw2g->index_cck_base[path][group] = 0x2D;
  1540. }
  1541. for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
  1542. pw2g->index_bw40_base[path][group] = hwinfo[addr++];
  1543. if (pw2g->index_bw40_base[path][group] == 0xFF)
  1544. pw2g->index_bw40_base[path][group] = 0x2D;
  1545. }
  1546. for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
  1547. if (cnt == 0) {
  1548. pw2g->bw40_diff[path][cnt] = 0;
  1549. if (hwinfo[addr] == 0xFF) {
  1550. pw2g->bw20_diff[path][cnt] = 0x02;
  1551. } else {
  1552. pw2g->bw20_diff[path][cnt] =
  1553. (hwinfo[addr] & 0xf0) >> 4;
  1554. /*bit sign number to 8 bit sign number*/
  1555. if (pw2g->bw20_diff[path][cnt] & BIT(3))
  1556. pw2g->bw20_diff[path][cnt] |=
  1557. 0xF0;
  1558. }
  1559. if (hwinfo[addr] == 0xFF) {
  1560. pw2g->ofdm_diff[path][cnt] = 0x04;
  1561. } else {
  1562. pw2g->ofdm_diff[path][cnt] =
  1563. (hwinfo[addr] & 0x0f);
  1564. /*bit sign number to 8 bit sign number*/
  1565. if (pw2g->ofdm_diff[path][cnt] & BIT(3))
  1566. pw2g->ofdm_diff[path][cnt] |=
  1567. 0xF0;
  1568. }
  1569. pw2g->cck_diff[path][cnt] = 0;
  1570. addr++;
  1571. } else {
  1572. if (hwinfo[addr] == 0xFF) {
  1573. pw2g->bw40_diff[path][cnt] = 0xFE;
  1574. } else {
  1575. pw2g->bw40_diff[path][cnt] =
  1576. (hwinfo[addr] & 0xf0) >> 4;
  1577. if (pw2g->bw40_diff[path][cnt] & BIT(3))
  1578. pw2g->bw40_diff[path][cnt] |=
  1579. 0xF0;
  1580. }
  1581. if (hwinfo[addr] == 0xFF) {
  1582. pw2g->bw20_diff[path][cnt] = 0xFE;
  1583. } else {
  1584. pw2g->bw20_diff[path][cnt] =
  1585. (hwinfo[addr] & 0x0f);
  1586. if (pw2g->bw20_diff[path][cnt] & BIT(3))
  1587. pw2g->bw20_diff[path][cnt] |=
  1588. 0xF0;
  1589. }
  1590. addr++;
  1591. if (hwinfo[addr] == 0xFF) {
  1592. pw2g->ofdm_diff[path][cnt] = 0xFE;
  1593. } else {
  1594. pw2g->ofdm_diff[path][cnt] =
  1595. (hwinfo[addr] & 0xf0) >> 4;
  1596. if (pw2g->ofdm_diff[path][cnt] & BIT(3))
  1597. pw2g->ofdm_diff[path][cnt] |=
  1598. 0xF0;
  1599. }
  1600. if (hwinfo[addr] == 0xFF)
  1601. pw2g->cck_diff[path][cnt] = 0xFE;
  1602. else {
  1603. pw2g->cck_diff[path][cnt] =
  1604. (hwinfo[addr] & 0x0f);
  1605. if (pw2g->cck_diff[path][cnt] & BIT(3))
  1606. pw2g->cck_diff[path][cnt] |=
  1607. 0xF0;
  1608. }
  1609. addr++;
  1610. }
  1611. }
  1612. /*5G default value*/
  1613. for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
  1614. pw5g->index_bw40_base[path][group] = hwinfo[addr++];
  1615. if (pw5g->index_bw40_base[path][group] == 0xFF)
  1616. pw5g->index_bw40_base[path][group] = 0xFE;
  1617. }
  1618. for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
  1619. if (cnt == 0) {
  1620. pw5g->bw40_diff[path][cnt] = 0;
  1621. if (hwinfo[addr] == 0xFF) {
  1622. pw5g->bw20_diff[path][cnt] = 0;
  1623. } else {
  1624. pw5g->bw20_diff[path][0] =
  1625. (hwinfo[addr] & 0xf0) >> 4;
  1626. if (pw5g->bw20_diff[path][cnt] & BIT(3))
  1627. pw5g->bw20_diff[path][cnt] |=
  1628. 0xF0;
  1629. }
  1630. if (hwinfo[addr] == 0xFF)
  1631. pw5g->ofdm_diff[path][cnt] = 0x04;
  1632. else {
  1633. pw5g->ofdm_diff[path][0] =
  1634. (hwinfo[addr] & 0x0f);
  1635. if (pw5g->ofdm_diff[path][cnt] & BIT(3))
  1636. pw5g->ofdm_diff[path][cnt] |=
  1637. 0xF0;
  1638. }
  1639. addr++;
  1640. } else {
  1641. if (hwinfo[addr] == 0xFF) {
  1642. pw5g->bw40_diff[path][cnt] = 0xFE;
  1643. } else {
  1644. pw5g->bw40_diff[path][cnt] =
  1645. (hwinfo[addr] & 0xf0) >> 4;
  1646. if (pw5g->bw40_diff[path][cnt] & BIT(3))
  1647. pw5g->bw40_diff[path][cnt] |= 0xF0;
  1648. }
  1649. if (hwinfo[addr] == 0xFF) {
  1650. pw5g->bw20_diff[path][cnt] = 0xFE;
  1651. } else {
  1652. pw5g->bw20_diff[path][cnt] =
  1653. (hwinfo[addr] & 0x0f);
  1654. if (pw5g->bw20_diff[path][cnt] & BIT(3))
  1655. pw5g->bw20_diff[path][cnt] |= 0xF0;
  1656. }
  1657. addr++;
  1658. }
  1659. }
  1660. if (hwinfo[addr] == 0xFF) {
  1661. pw5g->ofdm_diff[path][1] = 0xFE;
  1662. pw5g->ofdm_diff[path][2] = 0xFE;
  1663. } else {
  1664. pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
  1665. pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
  1666. }
  1667. addr++;
  1668. if (hwinfo[addr] == 0xFF)
  1669. pw5g->ofdm_diff[path][3] = 0xFE;
  1670. else
  1671. pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
  1672. addr++;
  1673. for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
  1674. if (pw5g->ofdm_diff[path][cnt] == 0xFF)
  1675. pw5g->ofdm_diff[path][cnt] = 0xFE;
  1676. else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
  1677. pw5g->ofdm_diff[path][cnt] |= 0xF0;
  1678. }
  1679. }
  1680. }
  1681. static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
  1682. bool autoload_fail,
  1683. u8 *hwinfo)
  1684. {
  1685. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1686. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  1687. struct txpower_info_2g pw2g;
  1688. struct txpower_info_5g pw5g;
  1689. u8 rf_path, index;
  1690. u8 i;
  1691. _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
  1692. hwinfo);
  1693. for (rf_path = 0; rf_path < 2; rf_path++) {
  1694. for (i = 0; i < 14; i++) {
  1695. index = _rtl8723be_get_chnl_group(i+1);
  1696. rtlefuse->txpwrlevel_cck[rf_path][i] =
  1697. pw2g.index_cck_base[rf_path][index];
  1698. rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
  1699. pw2g.index_bw40_base[rf_path][index];
  1700. }
  1701. for (i = 0; i < MAX_TX_COUNT; i++) {
  1702. rtlefuse->txpwr_ht20diff[rf_path][i] =
  1703. pw2g.bw20_diff[rf_path][i];
  1704. rtlefuse->txpwr_ht40diff[rf_path][i] =
  1705. pw2g.bw40_diff[rf_path][i];
  1706. rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
  1707. pw2g.ofdm_diff[rf_path][i];
  1708. }
  1709. for (i = 0; i < 14; i++) {
  1710. RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
  1711. "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
  1712. rf_path, i,
  1713. rtlefuse->txpwrlevel_cck[rf_path][i],
  1714. rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
  1715. }
  1716. }
  1717. if (!autoload_fail)
  1718. rtlefuse->eeprom_thermalmeter =
  1719. hwinfo[EEPROM_THERMAL_METER_88E];
  1720. else
  1721. rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
  1722. if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
  1723. rtlefuse->apk_thermalmeterignore = true;
  1724. rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
  1725. }
  1726. rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
  1727. RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
  1728. "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
  1729. if (!autoload_fail) {
  1730. rtlefuse->eeprom_regulatory =
  1731. hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
  1732. if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
  1733. rtlefuse->eeprom_regulatory = 0;
  1734. } else {
  1735. rtlefuse->eeprom_regulatory = 0;
  1736. }
  1737. RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
  1738. "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
  1739. }
  1740. static u8 _rtl8723be_read_package_type(struct ieee80211_hw *hw)
  1741. {
  1742. u8 package_type;
  1743. u8 value;
  1744. efuse_power_switch(hw, false, true);
  1745. if (!efuse_one_byte_read(hw, 0x1FB, &value))
  1746. value = 0;
  1747. efuse_power_switch(hw, false, false);
  1748. switch (value & 0x7) {
  1749. case 0x4:
  1750. package_type = PACKAGE_TFBGA79;
  1751. break;
  1752. case 0x5:
  1753. package_type = PACKAGE_TFBGA90;
  1754. break;
  1755. case 0x6:
  1756. package_type = PACKAGE_QFN68;
  1757. break;
  1758. case 0x7:
  1759. package_type = PACKAGE_TFBGA80;
  1760. break;
  1761. default:
  1762. package_type = PACKAGE_DEFAULT;
  1763. break;
  1764. }
  1765. return package_type;
  1766. }
  1767. static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
  1768. bool pseudo_test)
  1769. {
  1770. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1771. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  1772. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1773. int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
  1774. EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
  1775. EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
  1776. COUNTRY_CODE_WORLD_WIDE_13};
  1777. u8 *hwinfo;
  1778. int i;
  1779. bool is_toshiba_smid1 = false;
  1780. bool is_toshiba_smid2 = false;
  1781. bool is_samsung_smid = false;
  1782. bool is_lenovo_smid = false;
  1783. u16 toshiba_smid1[] = {
  1784. 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
  1785. 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
  1786. 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
  1787. 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
  1788. };
  1789. u16 toshiba_smid2[] = {
  1790. 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
  1791. 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
  1792. };
  1793. u16 samsung_smid[] = {
  1794. 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
  1795. 0x8193, 0x9191, 0x9192, 0x9193
  1796. };
  1797. u16 lenovo_smid[] = {
  1798. 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
  1799. };
  1800. if (pseudo_test) {
  1801. /* needs to be added */
  1802. return;
  1803. }
  1804. hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
  1805. if (!hwinfo)
  1806. return;
  1807. if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
  1808. goto exit;
  1809. /*parse xtal*/
  1810. rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
  1811. if (rtlefuse->crystalcap == 0xFF)
  1812. rtlefuse->crystalcap = 0x20;
  1813. _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
  1814. hwinfo);
  1815. rtl8723be_read_bt_coexist_info_from_hwpg(hw,
  1816. rtlefuse->autoload_failflag,
  1817. hwinfo);
  1818. if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
  1819. rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
  1820. rtlhal->board_type = rtlefuse->board_type;
  1821. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  1822. "board_type = 0x%x\n", rtlefuse->board_type);
  1823. rtlhal->package_type = _rtl8723be_read_package_type(hw);
  1824. /* set channel plan from efuse */
  1825. rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
  1826. if (rtlhal->oem_id == RT_CID_DEFAULT) {
  1827. /* Does this one have a Toshiba SMID from group 1? */
  1828. for (i = 0; i < ARRAY_SIZE(toshiba_smid1); i++) {
  1829. if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
  1830. is_toshiba_smid1 = true;
  1831. break;
  1832. }
  1833. }
  1834. /* Does this one have a Toshiba SMID from group 2? */
  1835. for (i = 0; i < ARRAY_SIZE(toshiba_smid2); i++) {
  1836. if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
  1837. is_toshiba_smid2 = true;
  1838. break;
  1839. }
  1840. }
  1841. /* Does this one have a Samsung SMID? */
  1842. for (i = 0; i < ARRAY_SIZE(samsung_smid); i++) {
  1843. if (rtlefuse->eeprom_smid == samsung_smid[i]) {
  1844. is_samsung_smid = true;
  1845. break;
  1846. }
  1847. }
  1848. /* Does this one have a Lenovo SMID? */
  1849. for (i = 0; i < ARRAY_SIZE(lenovo_smid); i++) {
  1850. if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
  1851. is_lenovo_smid = true;
  1852. break;
  1853. }
  1854. }
  1855. switch (rtlefuse->eeprom_oemid) {
  1856. case EEPROM_CID_DEFAULT:
  1857. if (rtlefuse->eeprom_did == 0x8176) {
  1858. if (rtlefuse->eeprom_svid == 0x10EC &&
  1859. is_toshiba_smid1) {
  1860. rtlhal->oem_id = RT_CID_TOSHIBA;
  1861. } else if (rtlefuse->eeprom_svid == 0x1025) {
  1862. rtlhal->oem_id = RT_CID_819X_ACER;
  1863. } else if (rtlefuse->eeprom_svid == 0x10EC &&
  1864. is_samsung_smid) {
  1865. rtlhal->oem_id = RT_CID_819X_SAMSUNG;
  1866. } else if (rtlefuse->eeprom_svid == 0x10EC &&
  1867. is_lenovo_smid) {
  1868. rtlhal->oem_id = RT_CID_819X_LENOVO;
  1869. } else if ((rtlefuse->eeprom_svid == 0x10EC &&
  1870. rtlefuse->eeprom_smid == 0x8197) ||
  1871. (rtlefuse->eeprom_svid == 0x10EC &&
  1872. rtlefuse->eeprom_smid == 0x9196)) {
  1873. rtlhal->oem_id = RT_CID_819X_CLEVO;
  1874. } else if ((rtlefuse->eeprom_svid == 0x1028 &&
  1875. rtlefuse->eeprom_smid == 0x8194) ||
  1876. (rtlefuse->eeprom_svid == 0x1028 &&
  1877. rtlefuse->eeprom_smid == 0x8198) ||
  1878. (rtlefuse->eeprom_svid == 0x1028 &&
  1879. rtlefuse->eeprom_smid == 0x9197) ||
  1880. (rtlefuse->eeprom_svid == 0x1028 &&
  1881. rtlefuse->eeprom_smid == 0x9198)) {
  1882. rtlhal->oem_id = RT_CID_819X_DELL;
  1883. } else if ((rtlefuse->eeprom_svid == 0x103C &&
  1884. rtlefuse->eeprom_smid == 0x1629)) {
  1885. rtlhal->oem_id = RT_CID_819X_HP;
  1886. } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
  1887. rtlefuse->eeprom_smid == 0x2315)) {
  1888. rtlhal->oem_id = RT_CID_819X_QMI;
  1889. } else if ((rtlefuse->eeprom_svid == 0x10EC &&
  1890. rtlefuse->eeprom_smid == 0x8203)) {
  1891. rtlhal->oem_id = RT_CID_819X_PRONETS;
  1892. } else if ((rtlefuse->eeprom_svid == 0x1043 &&
  1893. rtlefuse->eeprom_smid == 0x84B5)) {
  1894. rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
  1895. } else {
  1896. rtlhal->oem_id = RT_CID_DEFAULT;
  1897. }
  1898. } else if (rtlefuse->eeprom_did == 0x8178) {
  1899. if (rtlefuse->eeprom_svid == 0x10EC &&
  1900. is_toshiba_smid2)
  1901. rtlhal->oem_id = RT_CID_TOSHIBA;
  1902. else if (rtlefuse->eeprom_svid == 0x1025)
  1903. rtlhal->oem_id = RT_CID_819X_ACER;
  1904. else if ((rtlefuse->eeprom_svid == 0x10EC &&
  1905. rtlefuse->eeprom_smid == 0x8186))
  1906. rtlhal->oem_id = RT_CID_819X_PRONETS;
  1907. else if ((rtlefuse->eeprom_svid == 0x1043 &&
  1908. rtlefuse->eeprom_smid == 0x84B6))
  1909. rtlhal->oem_id =
  1910. RT_CID_819X_EDIMAX_ASUS;
  1911. else
  1912. rtlhal->oem_id = RT_CID_DEFAULT;
  1913. } else {
  1914. rtlhal->oem_id = RT_CID_DEFAULT;
  1915. }
  1916. break;
  1917. case EEPROM_CID_TOSHIBA:
  1918. rtlhal->oem_id = RT_CID_TOSHIBA;
  1919. break;
  1920. case EEPROM_CID_CCX:
  1921. rtlhal->oem_id = RT_CID_CCX;
  1922. break;
  1923. case EEPROM_CID_QMI:
  1924. rtlhal->oem_id = RT_CID_819X_QMI;
  1925. break;
  1926. case EEPROM_CID_WHQL:
  1927. break;
  1928. default:
  1929. rtlhal->oem_id = RT_CID_DEFAULT;
  1930. break;
  1931. }
  1932. }
  1933. exit:
  1934. kfree(hwinfo);
  1935. }
  1936. static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
  1937. {
  1938. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1939. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1940. rtlpriv->ledctl.led_opendrain = true;
  1941. switch (rtlhal->oem_id) {
  1942. case RT_CID_819X_HP:
  1943. rtlpriv->ledctl.led_opendrain = true;
  1944. break;
  1945. case RT_CID_819X_LENOVO:
  1946. case RT_CID_DEFAULT:
  1947. case RT_CID_TOSHIBA:
  1948. case RT_CID_CCX:
  1949. case RT_CID_819X_ACER:
  1950. case RT_CID_WHQL:
  1951. default:
  1952. break;
  1953. }
  1954. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1955. "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
  1956. }
  1957. void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
  1958. {
  1959. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1960. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  1961. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1962. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1963. u8 tmp_u1b;
  1964. rtlhal->version = _rtl8723be_read_chip_version(hw);
  1965. if (get_rf_type(rtlphy) == RF_1T1R)
  1966. rtlpriv->dm.rfpath_rxenable[0] = true;
  1967. else
  1968. rtlpriv->dm.rfpath_rxenable[0] =
  1969. rtlpriv->dm.rfpath_rxenable[1] = true;
  1970. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
  1971. rtlhal->version);
  1972. tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
  1973. if (tmp_u1b & BIT(4)) {
  1974. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
  1975. rtlefuse->epromtype = EEPROM_93C46;
  1976. } else {
  1977. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
  1978. rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
  1979. }
  1980. if (tmp_u1b & BIT(5)) {
  1981. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
  1982. rtlefuse->autoload_failflag = false;
  1983. _rtl8723be_read_adapter_info(hw, false);
  1984. } else {
  1985. pr_err("Autoload ERR!!\n");
  1986. }
  1987. _rtl8723be_hal_customized_behavior(hw);
  1988. }
  1989. static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
  1990. u8 rate_index)
  1991. {
  1992. u8 ret = 0;
  1993. switch (rate_index) {
  1994. case RATR_INX_WIRELESS_NGB:
  1995. ret = 1;
  1996. break;
  1997. case RATR_INX_WIRELESS_N:
  1998. case RATR_INX_WIRELESS_NG:
  1999. ret = 5;
  2000. break;
  2001. case RATR_INX_WIRELESS_NB:
  2002. ret = 3;
  2003. break;
  2004. case RATR_INX_WIRELESS_GB:
  2005. ret = 6;
  2006. break;
  2007. case RATR_INX_WIRELESS_G:
  2008. ret = 7;
  2009. break;
  2010. case RATR_INX_WIRELESS_B:
  2011. ret = 8;
  2012. break;
  2013. default:
  2014. ret = 0;
  2015. break;
  2016. }
  2017. return ret;
  2018. }
  2019. static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
  2020. struct ieee80211_sta *sta,
  2021. u8 rssi_level, bool update_bw)
  2022. {
  2023. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2024. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  2025. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  2026. struct rtl_sta_info *sta_entry = NULL;
  2027. u32 ratr_bitmap;
  2028. u8 ratr_index;
  2029. u8 curtxbw_40mhz = (sta->ht_cap.cap &
  2030. IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
  2031. u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
  2032. 1 : 0;
  2033. u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
  2034. 1 : 0;
  2035. enum wireless_mode wirelessmode = 0;
  2036. bool shortgi = false;
  2037. u8 rate_mask[7];
  2038. u8 macid = 0;
  2039. sta_entry = (struct rtl_sta_info *)sta->drv_priv;
  2040. wirelessmode = sta_entry->wireless_mode;
  2041. if (mac->opmode == NL80211_IFTYPE_STATION ||
  2042. mac->opmode == NL80211_IFTYPE_MESH_POINT)
  2043. curtxbw_40mhz = mac->bw_40;
  2044. else if (mac->opmode == NL80211_IFTYPE_AP ||
  2045. mac->opmode == NL80211_IFTYPE_ADHOC)
  2046. macid = sta->aid + 1;
  2047. ratr_bitmap = sta->supp_rates[0];
  2048. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  2049. ratr_bitmap = 0xfff;
  2050. ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
  2051. sta->ht_cap.mcs.rx_mask[0] << 12);
  2052. switch (wirelessmode) {
  2053. case WIRELESS_MODE_B:
  2054. ratr_index = RATR_INX_WIRELESS_B;
  2055. if (ratr_bitmap & 0x0000000c)
  2056. ratr_bitmap &= 0x0000000d;
  2057. else
  2058. ratr_bitmap &= 0x0000000f;
  2059. break;
  2060. case WIRELESS_MODE_G:
  2061. ratr_index = RATR_INX_WIRELESS_GB;
  2062. if (rssi_level == 1)
  2063. ratr_bitmap &= 0x00000f00;
  2064. else if (rssi_level == 2)
  2065. ratr_bitmap &= 0x00000ff0;
  2066. else
  2067. ratr_bitmap &= 0x00000ff5;
  2068. break;
  2069. case WIRELESS_MODE_N_24G:
  2070. case WIRELESS_MODE_N_5G:
  2071. ratr_index = RATR_INX_WIRELESS_NGB;
  2072. if (rtlphy->rf_type == RF_1T1R) {
  2073. if (curtxbw_40mhz) {
  2074. if (rssi_level == 1)
  2075. ratr_bitmap &= 0x000f0000;
  2076. else if (rssi_level == 2)
  2077. ratr_bitmap &= 0x000ff000;
  2078. else
  2079. ratr_bitmap &= 0x000ff015;
  2080. } else {
  2081. if (rssi_level == 1)
  2082. ratr_bitmap &= 0x000f0000;
  2083. else if (rssi_level == 2)
  2084. ratr_bitmap &= 0x000ff000;
  2085. else
  2086. ratr_bitmap &= 0x000ff005;
  2087. }
  2088. } else {
  2089. if (curtxbw_40mhz) {
  2090. if (rssi_level == 1)
  2091. ratr_bitmap &= 0x0f8f0000;
  2092. else if (rssi_level == 2)
  2093. ratr_bitmap &= 0x0f8ff000;
  2094. else
  2095. ratr_bitmap &= 0x0f8ff015;
  2096. } else {
  2097. if (rssi_level == 1)
  2098. ratr_bitmap &= 0x0f8f0000;
  2099. else if (rssi_level == 2)
  2100. ratr_bitmap &= 0x0f8ff000;
  2101. else
  2102. ratr_bitmap &= 0x0f8ff005;
  2103. }
  2104. }
  2105. if ((curtxbw_40mhz && curshortgi_40mhz) ||
  2106. (!curtxbw_40mhz && curshortgi_20mhz)) {
  2107. if (macid == 0)
  2108. shortgi = true;
  2109. else if (macid == 1)
  2110. shortgi = false;
  2111. }
  2112. break;
  2113. default:
  2114. ratr_index = RATR_INX_WIRELESS_NGB;
  2115. if (rtlphy->rf_type == RF_1T2R)
  2116. ratr_bitmap &= 0x000ff0ff;
  2117. else
  2118. ratr_bitmap &= 0x0f0ff0ff;
  2119. break;
  2120. }
  2121. sta_entry->ratr_index = ratr_index;
  2122. RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
  2123. "ratr_bitmap :%x\n", ratr_bitmap);
  2124. *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
  2125. (ratr_index << 28);
  2126. rate_mask[0] = macid;
  2127. rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
  2128. (shortgi ? 0x80 : 0x00);
  2129. rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3);
  2130. rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
  2131. rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
  2132. rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
  2133. rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
  2134. RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
  2135. "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
  2136. ratr_index, ratr_bitmap,
  2137. rate_mask[0], rate_mask[1],
  2138. rate_mask[2], rate_mask[3],
  2139. rate_mask[4], rate_mask[5],
  2140. rate_mask[6]);
  2141. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
  2142. _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
  2143. }
  2144. void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
  2145. struct ieee80211_sta *sta,
  2146. u8 rssi_level, bool update_bw)
  2147. {
  2148. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2149. if (rtlpriv->dm.useramask)
  2150. rtl8723be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
  2151. }
  2152. void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
  2153. {
  2154. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2155. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  2156. u16 sifs_timer;
  2157. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
  2158. if (!mac->ht_enable)
  2159. sifs_timer = 0x0a0a;
  2160. else
  2161. sifs_timer = 0x0e0e;
  2162. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
  2163. }
  2164. bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
  2165. {
  2166. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2167. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  2168. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  2169. enum rf_pwrstate e_rfpowerstate_toset;
  2170. u8 u1tmp;
  2171. bool b_actuallyset = false;
  2172. if (rtlpriv->rtlhal.being_init_adapter)
  2173. return false;
  2174. if (ppsc->swrf_processing)
  2175. return false;
  2176. spin_lock(&rtlpriv->locks.rf_ps_lock);
  2177. if (ppsc->rfchange_inprogress) {
  2178. spin_unlock(&rtlpriv->locks.rf_ps_lock);
  2179. return false;
  2180. } else {
  2181. ppsc->rfchange_inprogress = true;
  2182. spin_unlock(&rtlpriv->locks.rf_ps_lock);
  2183. }
  2184. rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
  2185. rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
  2186. u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
  2187. if (rtlphy->polarity_ctl)
  2188. e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
  2189. else
  2190. e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
  2191. if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
  2192. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  2193. "GPIOChangeRF - HW Radio ON, RF ON\n");
  2194. e_rfpowerstate_toset = ERFON;
  2195. ppsc->hwradiooff = false;
  2196. b_actuallyset = true;
  2197. } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
  2198. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  2199. "GPIOChangeRF - HW Radio OFF, RF OFF\n");
  2200. e_rfpowerstate_toset = ERFOFF;
  2201. ppsc->hwradiooff = true;
  2202. b_actuallyset = true;
  2203. }
  2204. if (b_actuallyset) {
  2205. spin_lock(&rtlpriv->locks.rf_ps_lock);
  2206. ppsc->rfchange_inprogress = false;
  2207. spin_unlock(&rtlpriv->locks.rf_ps_lock);
  2208. } else {
  2209. if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
  2210. RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
  2211. spin_lock(&rtlpriv->locks.rf_ps_lock);
  2212. ppsc->rfchange_inprogress = false;
  2213. spin_unlock(&rtlpriv->locks.rf_ps_lock);
  2214. }
  2215. *valid = 1;
  2216. return !ppsc->hwradiooff;
  2217. }
  2218. void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
  2219. u8 *p_macaddr, bool is_group, u8 enc_algo,
  2220. bool is_wepkey, bool clear_all)
  2221. {
  2222. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2223. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  2224. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  2225. u8 *macaddr = p_macaddr;
  2226. u32 entry_id = 0;
  2227. bool is_pairwise = false;
  2228. static u8 cam_const_addr[4][6] = {
  2229. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  2230. {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
  2231. {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
  2232. {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
  2233. };
  2234. static u8 cam_const_broad[] = {
  2235. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
  2236. };
  2237. if (clear_all) {
  2238. u8 idx = 0;
  2239. u8 cam_offset = 0;
  2240. u8 clear_number = 5;
  2241. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
  2242. for (idx = 0; idx < clear_number; idx++) {
  2243. rtl_cam_mark_invalid(hw, cam_offset + idx);
  2244. rtl_cam_empty_entry(hw, cam_offset + idx);
  2245. if (idx < 5) {
  2246. memset(rtlpriv->sec.key_buf[idx], 0,
  2247. MAX_KEY_LEN);
  2248. rtlpriv->sec.key_len[idx] = 0;
  2249. }
  2250. }
  2251. } else {
  2252. switch (enc_algo) {
  2253. case WEP40_ENCRYPTION:
  2254. enc_algo = CAM_WEP40;
  2255. break;
  2256. case WEP104_ENCRYPTION:
  2257. enc_algo = CAM_WEP104;
  2258. break;
  2259. case TKIP_ENCRYPTION:
  2260. enc_algo = CAM_TKIP;
  2261. break;
  2262. case AESCCMP_ENCRYPTION:
  2263. enc_algo = CAM_AES;
  2264. break;
  2265. default:
  2266. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  2267. "switch case %#x not processed\n", enc_algo);
  2268. enc_algo = CAM_TKIP;
  2269. break;
  2270. }
  2271. if (is_wepkey || rtlpriv->sec.use_defaultkey) {
  2272. macaddr = cam_const_addr[key_index];
  2273. entry_id = key_index;
  2274. } else {
  2275. if (is_group) {
  2276. macaddr = cam_const_broad;
  2277. entry_id = key_index;
  2278. } else {
  2279. if (mac->opmode == NL80211_IFTYPE_AP) {
  2280. entry_id = rtl_cam_get_free_entry(hw,
  2281. p_macaddr);
  2282. if (entry_id >= TOTAL_CAM_ENTRY) {
  2283. pr_err("Can not find free hw security cam entry\n");
  2284. return;
  2285. }
  2286. } else {
  2287. entry_id = CAM_PAIRWISE_KEY_POSITION;
  2288. }
  2289. key_index = PAIRWISE_KEYIDX;
  2290. is_pairwise = true;
  2291. }
  2292. }
  2293. if (rtlpriv->sec.key_len[key_index] == 0) {
  2294. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  2295. "delete one entry, entry_id is %d\n",
  2296. entry_id);
  2297. if (mac->opmode == NL80211_IFTYPE_AP)
  2298. rtl_cam_del_entry(hw, p_macaddr);
  2299. rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
  2300. } else {
  2301. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  2302. "add one entry\n");
  2303. if (is_pairwise) {
  2304. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  2305. "set Pairwise key\n");
  2306. rtl_cam_add_one_entry(hw, macaddr, key_index,
  2307. entry_id, enc_algo,
  2308. CAM_CONFIG_NO_USEDK,
  2309. rtlpriv->sec.key_buf[key_index]);
  2310. } else {
  2311. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  2312. "set group key\n");
  2313. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  2314. rtl_cam_add_one_entry(hw,
  2315. rtlefuse->dev_addr,
  2316. PAIRWISE_KEYIDX,
  2317. CAM_PAIRWISE_KEY_POSITION,
  2318. enc_algo,
  2319. CAM_CONFIG_NO_USEDK,
  2320. rtlpriv->sec.key_buf
  2321. [entry_id]);
  2322. }
  2323. rtl_cam_add_one_entry(hw, macaddr, key_index,
  2324. entry_id, enc_algo,
  2325. CAM_CONFIG_NO_USEDK,
  2326. rtlpriv->sec.key_buf[entry_id]);
  2327. }
  2328. }
  2329. }
  2330. }
  2331. void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
  2332. bool auto_load_fail, u8 *hwinfo)
  2333. {
  2334. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2335. struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
  2336. u8 value;
  2337. u32 tmpu_32;
  2338. if (!auto_load_fail) {
  2339. tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
  2340. if (tmpu_32 & BIT(18))
  2341. rtlpriv->btcoexist.btc_info.btcoexist = 1;
  2342. else
  2343. rtlpriv->btcoexist.btc_info.btcoexist = 0;
  2344. value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
  2345. rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
  2346. rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
  2347. rtlpriv->btcoexist.btc_info.single_ant_path =
  2348. (value & 0x40 ? ANT_AUX : ANT_MAIN); /*0xc3[6]*/
  2349. } else {
  2350. rtlpriv->btcoexist.btc_info.btcoexist = 0;
  2351. rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
  2352. rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
  2353. rtlpriv->btcoexist.btc_info.single_ant_path = ANT_MAIN;
  2354. }
  2355. /* override ant_num / ant_path */
  2356. if (mod_params->ant_sel) {
  2357. rtlpriv->btcoexist.btc_info.ant_num =
  2358. (mod_params->ant_sel == 1 ? ANT_X1 : ANT_X2);
  2359. rtlpriv->btcoexist.btc_info.single_ant_path =
  2360. (mod_params->ant_sel == 1 ? ANT_AUX : ANT_MAIN);
  2361. }
  2362. }
  2363. void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
  2364. {
  2365. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2366. /* 0:Low, 1:High, 2:From Efuse. */
  2367. rtlpriv->btcoexist.reg_bt_iso = 2;
  2368. /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
  2369. rtlpriv->btcoexist.reg_bt_sco = 3;
  2370. /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
  2371. rtlpriv->btcoexist.reg_bt_sco = 0;
  2372. }
  2373. void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
  2374. {
  2375. struct rtl_priv *rtlpriv = rtl_priv(hw);
  2376. if (rtlpriv->cfg->ops->get_btc_status())
  2377. rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
  2378. }
  2379. void rtl8723be_suspend(struct ieee80211_hw *hw)
  2380. {
  2381. }
  2382. void rtl8723be_resume(struct ieee80211_hw *hw)
  2383. {
  2384. }