ark_hsuart.c 49 KB

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  1. /*
  2. * Driver for AMBA serial ports
  3. *
  4. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5. *
  6. * Copyright 1999 ARM Limited
  7. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  8. * Copyright (C) 2010 ST-Ericsson SA
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * This is a generic driver for ARM AMBA-type serial ports. They
  25. * have a lot of 16550-like features, but are not register compatible.
  26. * Note that although they do have CTS, DCD and DSR inputs, they do
  27. * not have an RI input, nor do they have DTR or RTS outputs. If
  28. * required, these have to be supplied via some other means (eg, GPIO)
  29. * and hooked into this driver.
  30. */
  31. #include <linux/module.h>
  32. #include <linux/ioport.h>
  33. #include <linux/init.h>
  34. #include <linux/console.h>
  35. #include <linux/sysrq.h>
  36. #include <linux/device.h>
  37. #include <linux/tty.h>
  38. #include <linux/tty_flip.h>
  39. #include <linux/serial_core.h>
  40. #include <linux/serial.h>
  41. #include <linux/clk.h>
  42. #include <linux/slab.h>
  43. #include <linux/of.h>
  44. #include <linux/of_device.h>
  45. #include <linux/io.h>
  46. #include <linux/dmaengine.h>
  47. #include <linux/dma-mapping.h>
  48. #include <linux/scatterlist.h>
  49. #include <linux/delay.h>
  50. #include <linux/types.h>
  51. #include <linux/platform_device.h>
  52. #include <asm/io.h>
  53. #include <asm-generic/sizes.h>
  54. #define HSUART_DEBUG
  55. #ifdef HSUART_DEBUG
  56. #define hsuart_printk(format, args...) printk(format, ##args)
  57. #else
  58. #define hsuart_printk(format, args...)
  59. #endif
  60. #define PORT_ARK 120
  61. #define HSUART_NR 2
  62. #define ARK_HSUART_MAJOR 6
  63. #define ARK_HSUART_MINOR 0
  64. #define ARK_ISR_PASS_LIMIT 256
  65. #define HSUART_DR_ERROR (HSUART_DR_OE | HSUART_DR_BE | HSUART_DR_PE | HSUART_DR_FE)
  66. #define HSUART_DUMMY_DR_RX (1 << 16)
  67. #define HSUART_WA_SAVE_NR 13
  68. /* -------------------------------------------------------------------------------
  69. * UART Register Offsets.
  70. */
  71. #define HSUART_RXD 0x00
  72. #define HSUART_TXD 0x40
  73. #define HSUART_UCR1 0x80
  74. #define HSUART_UCR2 0x84
  75. #define HSUART_UCR3 0x88
  76. #define HSUART_UCR4 0x8C
  77. #define HSUART_UFCR 0x90
  78. #define HSUART_USR1 0x94
  79. #define HSUART_USR2 0x98
  80. #define HSUART_UESC 0x9C
  81. #define HSUART_UTIM 0xA0
  82. #define HSUART_UBIR 0xA4
  83. #define HSUART_UBMR 0xA8
  84. #define HSUART_UBRC 0xAC
  85. #define HSUART_ONEMS 0xB0
  86. #define HSUART_UTS 0xB4
  87. #define HSUART_RXDMAEN (1 << 8)
  88. #define HSUART_TXDMAEN (1 << 3)
  89. #define HSUART_DR_OE (1 << 13)
  90. #define HSUART_DR_FE (1 << 12)
  91. #define HSUART_DR_BE (1 << 11)
  92. #define HSUART_DR_PE (1 << 10)
  93. #define HSUART_UTS_RXFF 0x08
  94. #define HSUART_UTS_TXFF 0x10
  95. #define HSUART_UTS_RXFE 0x20
  96. #define HSUART_UTS_TXFE 0x40
  97. #define HSUART_INT_RXD (1<<0)
  98. #define HSUART_INT_RXTIMEOUT (1<<1)
  99. #define HSUART_INT_TXD (1<<2)
  100. #define HSUART_INT_ERR_PARITY (1<<3)
  101. #define HSUART_INT_ERR_FRAME (1<<4)
  102. #define HSUART_INT_ERR_OVERRUN (1<<5)
  103. #define HSUART_INT_RTSD (1<<6)
  104. #define HSUART_INT_ERR (HSUART_INT_ERR_PARITY | HSUART_INT_ERR_FRAME | HSUART_INT_ERR_OVERRUN)
  105. struct ark_hsuart_data {
  106. bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
  107. void *dma_rx_param;
  108. void *dma_tx_param;
  109. void (*init) (void);
  110. void (*exit) (void);
  111. void (*reset) (void);
  112. };
  113. static const char hsuartx_name[][sizeof("ark_hsuartx")]={
  114. "ark_hsuart0",
  115. "ark_hsuart1",
  116. };
  117. struct ark_uart_iface{
  118. void (*get_mcu_carback_data)(unsigned char ch);
  119. void (*set_uartx_app_used)(unsigned int uart,bool en);
  120. unsigned int kernel_uart;
  121. };
  122. static void ark_hsuart_lockup_wa(unsigned long data);
  123. static const u32 hsuart_wa_reg[HSUART_WA_SAVE_NR] = {
  124. HSUART_UCR1,
  125. HSUART_UCR2,
  126. HSUART_UCR3,
  127. HSUART_UCR4,
  128. HSUART_UFCR,
  129. HSUART_USR1,
  130. HSUART_USR2,
  131. HSUART_UESC,
  132. HSUART_UTIM,
  133. HSUART_UBIR,
  134. HSUART_UBMR,
  135. HSUART_UBRC,
  136. HSUART_ONEMS ,
  137. };
  138. static u32 hsuart_wa_regdata[HSUART_WA_SAVE_NR];
  139. static DECLARE_TASKLET(ark_hsuart_lockup_tlet, ark_hsuart_lockup_wa, 0);
  140. /* Deals with DMA transactions */
  141. struct ark_hsuart_sgbuf {
  142. struct scatterlist sg;
  143. char *buf;
  144. };
  145. struct ark_hsuart_dmarx_data {
  146. struct dma_chan *chan;
  147. struct completion complete;
  148. bool use_buf_b;
  149. struct ark_hsuart_sgbuf sgbuf_a;
  150. struct ark_hsuart_sgbuf sgbuf_b;
  151. dma_cookie_t cookie;
  152. bool running;
  153. };
  154. struct ark_hsuart_dmatx_data {
  155. struct dma_chan *chan;
  156. struct scatterlist sg;
  157. char *buf;
  158. bool queued;
  159. };
  160. /*
  161. * We wrap our port structure around the generic uart_port.
  162. */
  163. struct ark_hsuart_port {
  164. struct uart_port port;
  165. struct clk *clk;
  166. unsigned int dmacr; /* dma control reg */
  167. unsigned int fifosize; /* vendor-specific */
  168. bool autorts;
  169. char type[12];
  170. bool interrupt_may_hang; /* vendor-specific */
  171. unsigned int sigs;
  172. #ifdef CONFIG_DMA_ENGINE
  173. /* DMA stuff */
  174. bool using_tx_dma;
  175. bool using_rx_dma;
  176. struct ark_hsuart_dmarx_data dmarx;
  177. struct ark_hsuart_dmatx_data dmatx;
  178. bool dma_probed;
  179. #endif
  180. };
  181. static struct ark_hsuart_port *ark_hsuart_ports[HSUART_NR];
  182. static void ark_hsuart_disable_interrupt(struct ark_hsuart_port *uap, u32 intr)
  183. {
  184. if(intr & HSUART_INT_RXD)
  185. writew(readl(uap->port.membase + HSUART_UCR1) & ~(1<<9), uap->port.membase + HSUART_UCR1);
  186. if(intr & HSUART_INT_RXTIMEOUT)
  187. writew(readl(uap->port.membase + HSUART_UCR2) & ~(1<<3), uap->port.membase + HSUART_UCR2);
  188. if(intr & HSUART_INT_TXD)
  189. writew(readl(uap->port.membase + HSUART_UCR1) & ~(1<<13), uap->port.membase + HSUART_UCR1);
  190. if(intr & HSUART_INT_ERR_PARITY)
  191. writew(readl(uap->port.membase + HSUART_UCR3) & ~(1<<12), uap->port.membase + HSUART_UCR3);
  192. if(intr & HSUART_INT_ERR_FRAME)
  193. writew(readl(uap->port.membase + HSUART_UCR3) & ~(1<<11), uap->port.membase + HSUART_UCR3);
  194. if(intr & HSUART_INT_ERR_OVERRUN)
  195. writew(readl(uap->port.membase + HSUART_UCR4) & ~(1<<1), uap->port.membase + HSUART_UCR4);
  196. if(intr & HSUART_INT_RTSD)
  197. writew(readl(uap->port.membase + HSUART_UCR1) & ~(1<<5), uap->port.membase + HSUART_UCR1);
  198. }
  199. static void ark_hsuart_enable_interrupt(struct ark_hsuart_port *uap, u32 intr)
  200. {
  201. if(intr & HSUART_INT_RXD)
  202. writew(readl(uap->port.membase + HSUART_UCR1) | (1<<9), uap->port.membase + HSUART_UCR1);
  203. if(intr & HSUART_INT_RXTIMEOUT)
  204. writew(readl(uap->port.membase + HSUART_UCR2) | (1<<3), uap->port.membase + HSUART_UCR2);
  205. if(intr & HSUART_INT_TXD)
  206. writew(readl(uap->port.membase + HSUART_UCR1) | (1<<13), uap->port.membase + HSUART_UCR1);
  207. if(intr & HSUART_INT_ERR_PARITY)
  208. writew(readl(uap->port.membase + HSUART_UCR3) | (1<<12), uap->port.membase + HSUART_UCR3);
  209. if(intr & HSUART_INT_ERR_FRAME)
  210. writew(readl(uap->port.membase + HSUART_UCR3) | (1<<11), uap->port.membase + HSUART_UCR3);
  211. if(intr & HSUART_INT_ERR_OVERRUN)
  212. writew(readl(uap->port.membase + HSUART_UCR4) | (1<<1), uap->port.membase + HSUART_UCR4);
  213. if(intr & HSUART_INT_RTSD)
  214. writew(readl(uap->port.membase + HSUART_UCR1) | (1<<5), uap->port.membase + HSUART_UCR1);
  215. }
  216. static void ark_hsuart_clear_interrupt(struct ark_hsuart_port *uap, u32 intr)
  217. {
  218. if(intr & HSUART_INT_RXTIMEOUT)
  219. writew(readl(uap->port.membase + HSUART_USR1) | (1<<8), uap->port.membase + HSUART_USR1);
  220. if(intr & HSUART_INT_ERR_PARITY)
  221. writew(readl(uap->port.membase + HSUART_USR1) | (1<<15), uap->port.membase + HSUART_USR1);
  222. if(intr & HSUART_INT_ERR_FRAME)
  223. writew(readl(uap->port.membase + HSUART_USR1) | (1<<10), uap->port.membase + HSUART_USR1);
  224. if(intr & HSUART_INT_ERR_OVERRUN)
  225. writew(readl(uap->port.membase + HSUART_USR2) | (1<<1), uap->port.membase + HSUART_USR2);
  226. if(intr & HSUART_INT_RTSD)
  227. writew(readl(uap->port.membase + HSUART_USR1) | (1<<12), uap->port.membase + HSUART_USR1);
  228. }
  229. static u32 ark_hsuart_get_interrupt_status(struct ark_hsuart_port *uap)
  230. {
  231. u32 status = 0;
  232. if(readl(uap->port.membase + HSUART_USR1) & (1<<9))
  233. status |= HSUART_INT_RXD;
  234. if(readl(uap->port.membase + HSUART_USR1) & (1<<8))
  235. status |= HSUART_INT_RXTIMEOUT;
  236. if((readl(uap->port.membase + HSUART_USR1) & (1<<13)) &&
  237. (readl(uap->port.membase + HSUART_UCR1) & (1<<13)))
  238. status |= HSUART_INT_TXD;
  239. if(readl(uap->port.membase + HSUART_USR1) & (1<<15))
  240. status |= HSUART_INT_ERR_PARITY;
  241. if(readl(uap->port.membase + HSUART_USR1) & (1<<10))
  242. status |= HSUART_INT_ERR_FRAME;
  243. if(readl(uap->port.membase + HSUART_USR2) & (1<<1))
  244. status |= HSUART_INT_ERR_OVERRUN;
  245. if(readl(uap->port.membase + HSUART_USR1) & (1<<12))
  246. status |= HSUART_INT_RTSD;
  247. return status;
  248. }
  249. static inline void ark_hsuart_write_dmacr(struct ark_hsuart_port *uap, unsigned int dmacr)
  250. {
  251. u32 ucr = readl(uap->port.membase + HSUART_UCR1);
  252. ucr &= ~(HSUART_RXDMAEN | HSUART_TXDMAEN);
  253. ucr |= dmacr;
  254. writew(ucr, uap->port.membase + HSUART_UCR1);
  255. }
  256. /*
  257. * Reads up to 256 characters from the FIFO or until it's empty and
  258. * inserts them into the TTY layer. Returns the number of characters
  259. * read from the FIFO.
  260. */
  261. static int ark_hsuart_fifo_to_tty(struct ark_hsuart_port *uap)
  262. {
  263. u16 status, ch;
  264. unsigned int flag, max_count = 256;
  265. int fifotaken = 0;
  266. int hsuart_port = 0;
  267. if(ark_hsuart_ports[0] == uap){
  268. hsuart_port = 4;
  269. }
  270. else if (ark_hsuart_ports[1] == uap){
  271. hsuart_port = 5;
  272. }
  273. while (max_count--) {
  274. status = readw(uap->port.membase + HSUART_UTS);
  275. if (status & HSUART_UTS_RXFE)
  276. break;
  277. /* Take chars from the FIFO and update status */
  278. ch = readw(uap->port.membase + HSUART_RXD) |
  279. HSUART_DUMMY_DR_RX;
  280. flag = TTY_NORMAL;
  281. uap->port.icount.rx++;
  282. fifotaken++;
  283. if (unlikely(ch & HSUART_DR_ERROR)) {
  284. if (ch & HSUART_DR_BE) {
  285. ch &= ~(HSUART_DR_FE | HSUART_DR_PE);
  286. uap->port.icount.brk++;
  287. if (uart_handle_break(&uap->port))
  288. continue;
  289. } else if (ch & HSUART_DR_PE)
  290. uap->port.icount.parity++;
  291. else if (ch & HSUART_DR_FE)
  292. uap->port.icount.frame++;
  293. if (ch & HSUART_DR_OE)
  294. uap->port.icount.overrun++;
  295. ch &= uap->port.read_status_mask;
  296. if (ch & HSUART_DR_BE)
  297. flag = TTY_BREAK;
  298. else if (ch & HSUART_DR_PE)
  299. flag = TTY_PARITY;
  300. else if (ch & HSUART_DR_FE)
  301. flag = TTY_FRAME;
  302. }
  303. if (uart_handle_sysrq_char(&uap->port, ch & 255))
  304. continue;
  305. uart_insert_char(&uap->port, ch, HSUART_DR_OE, ch, flag);
  306. }
  307. return fifotaken;
  308. }
  309. /*
  310. * All the DMA operation mode stuff goes inside this ifdef.
  311. * This assumes that you have a generic DMA device interface,
  312. * no custom DMA interfaces are supported.
  313. */
  314. #ifdef CONFIG_DMA_ENGINE
  315. #define ARK_HSUART_DMA_BUFFER_SIZE PAGE_SIZE
  316. static int ark_hsuart_sgbuf_init(struct dma_chan *chan, struct ark_hsuart_sgbuf *sg,
  317. enum dma_data_direction dir)
  318. {
  319. dma_addr_t dma_addr;
  320. sg->buf = dma_alloc_coherent(chan->device->dev,
  321. ARK_HSUART_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
  322. if (!sg->buf)
  323. return -ENOMEM;
  324. sg_init_table(&sg->sg, 1);
  325. sg_set_page(&sg->sg, phys_to_page(dma_addr),
  326. ARK_HSUART_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
  327. sg_dma_address(&sg->sg) = dma_addr;
  328. sg_dma_len(&sg->sg) = ARK_HSUART_DMA_BUFFER_SIZE;
  329. return 0;
  330. }
  331. static void ark_hsuart_sgbuf_free(struct dma_chan *chan, struct ark_hsuart_sgbuf *sg,
  332. enum dma_data_direction dir)
  333. {
  334. if (sg->buf) {
  335. dma_free_coherent(chan->device->dev,
  336. ARK_HSUART_DMA_BUFFER_SIZE, sg->buf,
  337. sg_dma_address(&sg->sg));
  338. }
  339. }
  340. static void ark_hsuart_dma_probe(struct ark_hsuart_port *uap)
  341. {
  342. /* DMA is the sole user of the platform data right now */
  343. struct ark_hsuart_data *plat = dev_get_platdata(uap->port.dev);
  344. struct device *dev = uap->port.dev;
  345. struct dma_slave_config tx_conf = {
  346. .dst_addr = uap->port.mapbase + HSUART_TXD,
  347. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  348. .direction = DMA_MEM_TO_DEV,
  349. .dst_maxburst = uap->fifosize >> 1,
  350. .device_fc = false,
  351. };
  352. struct dma_chan *chan;
  353. dma_cap_mask_t mask;
  354. uap->dma_probed = true;
  355. chan = dma_request_slave_channel_reason(dev, "tx");
  356. if (IS_ERR(chan)) {
  357. if (PTR_ERR(chan) == -EPROBE_DEFER) {
  358. uap->dma_probed = false;
  359. return;
  360. }
  361. /* We need platform data */
  362. if (!plat || !plat->dma_filter) {
  363. dev_info(uap->port.dev, "no TX platform data\n");
  364. } else {
  365. /* Try to acquire a generic DMA engine slave TX channel */
  366. dma_cap_zero(mask);
  367. dma_cap_set(DMA_SLAVE, mask);
  368. chan = dma_request_channel(mask, plat->dma_filter,
  369. plat->dma_tx_param);
  370. if (!chan) {
  371. dev_err(uap->port.dev, "no TX DMA channel!\n");
  372. } else {
  373. dmaengine_slave_config(chan, &tx_conf);
  374. uap->dmatx.chan = chan;
  375. dev_info(uap->port.dev, "DMA channel TX %s\n",
  376. dma_chan_name(uap->dmatx.chan));
  377. }
  378. }
  379. } else {
  380. dmaengine_slave_config(chan, &tx_conf);
  381. uap->dmatx.chan = chan;
  382. dev_info(uap->port.dev, "DMA channel TX %s\n",
  383. dma_chan_name(uap->dmatx.chan));
  384. }
  385. /* Optionally make use of an RX channel as well */
  386. chan = dma_request_slave_channel(dev, "rx");
  387. if (!chan && plat && plat->dma_rx_param) {
  388. chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
  389. if (!chan) {
  390. dev_err(uap->port.dev, "no RX DMA channel!\n");
  391. return;
  392. }
  393. }
  394. if (chan) {
  395. struct dma_slave_config rx_conf = {
  396. .src_addr = uap->port.mapbase + HSUART_RXD,
  397. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  398. .direction = DMA_DEV_TO_MEM,
  399. .src_maxburst = uap->fifosize >> 2,
  400. .device_fc = false,
  401. };
  402. struct dma_slave_caps caps;
  403. /*
  404. * Some DMA controllers provide information on their capabilities.
  405. * If the controller does, check for suitable residue processing
  406. * otherwise assime all is well.
  407. */
  408. if (0 == dma_get_slave_caps(chan, &caps)) {
  409. if (caps.residue_granularity ==
  410. DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
  411. dma_release_channel(chan);
  412. dev_info(uap->port.dev,
  413. "RX DMA disabled - no residue processing\n");
  414. return;
  415. }
  416. }
  417. dmaengine_slave_config(chan, &rx_conf);
  418. uap->dmarx.chan = chan;
  419. dev_info(uap->port.dev, "DMA channel RX %s\n",
  420. dma_chan_name(uap->dmarx.chan));
  421. }
  422. }
  423. static void ark_hsuart_dma_remove(struct ark_hsuart_port *uap)
  424. {
  425. /* TODO: remove the initcall if it has not yet executed */
  426. if (uap->dmatx.chan)
  427. dma_release_channel(uap->dmatx.chan);
  428. if (uap->dmarx.chan)
  429. dma_release_channel(uap->dmarx.chan);
  430. }
  431. /* Forward declare this for the refill routine */
  432. static int ark_hsuart_dma_tx_refill(struct ark_hsuart_port *uap);
  433. /*
  434. * The current DMA TX buffer has been sent.
  435. * Try to queue up another DMA buffer.
  436. */
  437. static void ark_hsuart_dma_tx_callback(void *data)
  438. {
  439. struct ark_hsuart_port *uap = data;
  440. struct ark_hsuart_dmatx_data *dmatx = &uap->dmatx;
  441. unsigned long flags;
  442. u16 dmacr;
  443. spin_lock_irqsave(&uap->port.lock, flags);
  444. if (uap->dmatx.queued)
  445. dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
  446. DMA_TO_DEVICE);
  447. dmacr = uap->dmacr;
  448. uap->dmacr = dmacr & ~HSUART_TXDMAEN;
  449. ark_hsuart_write_dmacr(uap, uap->dmacr);
  450. /*
  451. * If TX DMA was disabled, it means that we've stopped the DMA for
  452. * some reason (eg, XOFF received, or we want to send an X-char.)
  453. *
  454. * Note: we need to be careful here of a potential race between DMA
  455. * and the rest of the driver - if the driver disables TX DMA while
  456. * a TX buffer completing, we must update the tx queued status to
  457. * get further refills (hence we check dmacr).
  458. */
  459. if (!(dmacr & HSUART_TXDMAEN) || uart_tx_stopped(&uap->port) ||
  460. uart_circ_empty(&uap->port.state->xmit)) {
  461. uap->dmatx.queued = false;
  462. spin_unlock_irqrestore(&uap->port.lock, flags);
  463. return;
  464. }
  465. if (ark_hsuart_dma_tx_refill(uap) <= 0) {
  466. /*
  467. * We didn't queue a DMA buffer for some reason, but we
  468. * have data pending to be sent. Re-enable the TX IRQ.
  469. */
  470. ark_hsuart_enable_interrupt(uap, HSUART_INT_TXD);
  471. }
  472. spin_unlock_irqrestore(&uap->port.lock, flags);
  473. }
  474. /*
  475. * Try to refill the TX DMA buffer.
  476. * Locking: called with port lock held and IRQs disabled.
  477. * Returns:
  478. * 1 if we queued up a TX DMA buffer.
  479. * 0 if we didn't want to handle this by DMA
  480. * <0 on error
  481. */
  482. static int ark_hsuart_dma_tx_refill(struct ark_hsuart_port *uap)
  483. {
  484. struct ark_hsuart_dmatx_data *dmatx = &uap->dmatx;
  485. struct dma_chan *chan = dmatx->chan;
  486. struct dma_device *dma_dev = chan->device;
  487. struct dma_async_tx_descriptor *desc;
  488. struct circ_buf *xmit = &uap->port.state->xmit;
  489. unsigned int count;
  490. /*
  491. * Try to avoid the overhead involved in using DMA if the
  492. * transaction fits in the first half of the FIFO, by using
  493. * the standard interrupt handling. This ensures that we
  494. * issue a uart_write_wakeup() at the appropriate time.
  495. */
  496. count = uart_circ_chars_pending(xmit);
  497. if (count < (uap->fifosize >> 1)) {
  498. uap->dmatx.queued = false;
  499. return 0;
  500. }
  501. /*
  502. * Bodge: don't send the last character by DMA, as this
  503. * will prevent XON from notifying us to restart DMA.
  504. */
  505. count -= 1;
  506. /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
  507. if (count > ARK_HSUART_DMA_BUFFER_SIZE)
  508. count = ARK_HSUART_DMA_BUFFER_SIZE;
  509. if (xmit->tail < xmit->head)
  510. memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
  511. else {
  512. size_t first = UART_XMIT_SIZE - xmit->tail;
  513. size_t second = xmit->head;
  514. memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
  515. if (second)
  516. memcpy(&dmatx->buf[first], &xmit->buf[0], second);
  517. }
  518. dmatx->sg.length = count;
  519. if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
  520. uap->dmatx.queued = false;
  521. dev_dbg(uap->port.dev, "unable to map TX DMA\n");
  522. return -EBUSY;
  523. }
  524. desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
  525. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  526. if (!desc) {
  527. dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
  528. uap->dmatx.queued = false;
  529. /*
  530. * If DMA cannot be used right now, we complete this
  531. * transaction via IRQ and let the TTY layer retry.
  532. */
  533. dev_dbg(uap->port.dev, "TX DMA busy\n");
  534. return -EBUSY;
  535. }
  536. /* Some data to go along to the callback */
  537. desc->callback = ark_hsuart_dma_tx_callback;
  538. desc->callback_param = uap;
  539. /* All errors should happen at prepare time */
  540. dmaengine_submit(desc);
  541. /* Fire the DMA transaction */
  542. dma_dev->device_issue_pending(chan);
  543. uap->dmacr |= HSUART_TXDMAEN;
  544. ark_hsuart_write_dmacr(uap, uap->dmacr);
  545. uap->dmatx.queued = true;
  546. /*
  547. * Now we know that DMA will fire, so advance the ring buffer
  548. * with the stuff we just dispatched.
  549. */
  550. xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
  551. uap->port.icount.tx += count;
  552. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  553. uart_write_wakeup(&uap->port);
  554. return 1;
  555. }
  556. /*
  557. * We received a transmit interrupt without a pending X-char but with
  558. * pending characters.
  559. * Locking: called with port lock held and IRQs disabled.
  560. * Returns:
  561. * false if we want to use PIO to transmit
  562. * true if we queued a DMA buffer
  563. */
  564. static bool ark_hsuart_dma_tx_irq(struct ark_hsuart_port *uap)
  565. {
  566. if (!uap->using_tx_dma)
  567. return false;
  568. /*
  569. * If we already have a TX buffer queued, but received a
  570. * TX interrupt, it will be because we've just sent an X-char.
  571. * Ensure the TX DMA is enabled and the TX IRQ is disabled.
  572. */
  573. if (uap->dmatx.queued) {
  574. uap->dmacr |= HSUART_TXDMAEN;
  575. ark_hsuart_write_dmacr(uap, uap->dmacr);
  576. ark_hsuart_disable_interrupt(uap, HSUART_INT_TXD);
  577. return true;
  578. }
  579. /*
  580. * We don't have a TX buffer queued, so try to queue one.
  581. * If we successfully queued a buffer, mask the TX IRQ.
  582. */
  583. if (ark_hsuart_dma_tx_refill(uap) > 0) {
  584. ark_hsuart_disable_interrupt(uap, HSUART_INT_TXD);
  585. return true;
  586. }
  587. return false;
  588. }
  589. /*
  590. * Stop the DMA transmit (eg, due to received XOFF).
  591. * Locking: called with port lock held and IRQs disabled.
  592. */
  593. static inline void ark_hsuart_dma_tx_stop(struct ark_hsuart_port *uap)
  594. {
  595. if (uap->dmatx.queued) {
  596. uap->dmacr &= ~HSUART_TXDMAEN;
  597. ark_hsuart_write_dmacr(uap, uap->dmacr);
  598. }
  599. }
  600. /*
  601. * Try to start a DMA transmit, or in the case of an XON/OFF
  602. * character queued for send, try to get that character out ASAP.
  603. * Locking: called with port lock held and IRQs disabled.
  604. * Returns:
  605. * false if we want the TX IRQ to be enabled
  606. * true if we have a buffer queued
  607. */
  608. static inline bool ark_hsuart_dma_tx_start(struct ark_hsuart_port *uap)
  609. {
  610. u16 dmacr;
  611. if (!uap->using_tx_dma)
  612. return false;
  613. if (!uap->port.x_char) {
  614. /* no X-char, try to push chars out in DMA mode */
  615. bool ret = true;
  616. if (!uap->dmatx.queued) {
  617. if (ark_hsuart_dma_tx_refill(uap) > 0) {
  618. ark_hsuart_disable_interrupt(uap, HSUART_INT_TXD);
  619. ret = true;
  620. } else {
  621. ark_hsuart_enable_interrupt(uap, HSUART_INT_TXD);
  622. ret = false;
  623. }
  624. } else if (!(uap->dmacr & HSUART_TXDMAEN)) {
  625. uap->dmacr |= HSUART_TXDMAEN;
  626. ark_hsuart_write_dmacr(uap, uap->dmacr);
  627. }
  628. return ret;
  629. }
  630. /*
  631. * We have an X-char to send. Disable DMA to prevent it loading
  632. * the TX fifo, and then see if we can stuff it into the FIFO.
  633. */
  634. dmacr = uap->dmacr;
  635. uap->dmacr &= ~HSUART_TXDMAEN;
  636. ark_hsuart_write_dmacr(uap, uap->dmacr);
  637. if (readw(uap->port.membase + HSUART_UTS) & HSUART_UTS_TXFF) {
  638. /*
  639. * No space in the FIFO, so enable the transmit interrupt
  640. * so we know when there is space. Note that once we've
  641. * loaded the character, we should just re-enable DMA.
  642. */
  643. return false;
  644. }
  645. writew(uap->port.x_char, uap->port.membase + HSUART_TXD);
  646. uap->port.icount.tx++;
  647. uap->port.x_char = 0;
  648. /* Success - restore the DMA state */
  649. uap->dmacr = dmacr;
  650. ark_hsuart_write_dmacr(uap, uap->dmacr);
  651. return true;
  652. }
  653. /*
  654. * Flush the transmit buffer.
  655. * Locking: called with port lock held and IRQs disabled.
  656. */
  657. static void ark_hsuart_dma_flush_buffer(struct uart_port *port)
  658. {
  659. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  660. if (!uap->using_tx_dma)
  661. return;
  662. /* Avoid deadlock with the DMA engine callback */
  663. spin_unlock(&uap->port.lock);
  664. dmaengine_terminate_all(uap->dmatx.chan);
  665. spin_lock(&uap->port.lock);
  666. if (uap->dmatx.queued) {
  667. dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
  668. DMA_TO_DEVICE);
  669. uap->dmatx.queued = false;
  670. uap->dmacr &= ~HSUART_TXDMAEN;
  671. ark_hsuart_write_dmacr(uap, uap->dmacr);
  672. }
  673. }
  674. static void ark_hsuart_dma_rx_callback(void *data);
  675. static int ark_hsuart_dma_rx_trigger_dma(struct ark_hsuart_port *uap)
  676. {
  677. struct dma_chan *rxchan = uap->dmarx.chan;
  678. struct ark_hsuart_dmarx_data *dmarx = &uap->dmarx;
  679. struct dma_async_tx_descriptor *desc;
  680. struct ark_hsuart_sgbuf *sgbuf;
  681. if (!rxchan)
  682. return -EIO;
  683. /* Start the RX DMA job */
  684. sgbuf = uap->dmarx.use_buf_b ?
  685. &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
  686. desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
  687. DMA_DEV_TO_MEM,
  688. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  689. /*
  690. * If the DMA engine is busy and cannot prepare a
  691. * channel, no big deal, the driver will fall back
  692. * to interrupt mode as a result of this error code.
  693. */
  694. if (!desc) {
  695. uap->dmarx.running = false;
  696. dmaengine_terminate_all(rxchan);
  697. return -EBUSY;
  698. }
  699. /* Some data to go along to the callback */
  700. desc->callback = ark_hsuart_dma_rx_callback;
  701. desc->callback_param = uap;
  702. dmarx->cookie = dmaengine_submit(desc);
  703. dma_async_issue_pending(rxchan);
  704. uap->dmacr |= HSUART_RXDMAEN;
  705. ark_hsuart_write_dmacr(uap, uap->dmacr);
  706. uap->dmarx.running = true;
  707. ark_hsuart_disable_interrupt(uap, HSUART_INT_RXD);
  708. return 0;
  709. }
  710. /*
  711. * This is called when either the DMA job is complete, or
  712. * the FIFO timeout interrupt occurred. This must be called
  713. * with the port spinlock uap->port.lock held.
  714. */
  715. static void ark_hsuart_dma_rx_chars(struct ark_hsuart_port *uap,
  716. u32 pending, bool use_buf_b,
  717. bool readfifo)
  718. {
  719. struct tty_port *port = &uap->port.state->port;
  720. struct ark_hsuart_sgbuf *sgbuf = use_buf_b ?
  721. &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
  722. int dma_count = 0;
  723. u32 fifotaken = 0; /* only used for vdbg() */
  724. /* Pick everything from the DMA first */
  725. if (pending) {
  726. /*
  727. * First take all chars in the DMA pipe, then look in the FIFO.
  728. * Note that tty_insert_flip_buf() tries to take as many chars
  729. * as it can.
  730. */
  731. dma_count = tty_insert_flip_string(port, sgbuf->buf, pending);
  732. uap->port.icount.rx += dma_count;
  733. if (dma_count < pending)
  734. dev_warn(uap->port.dev,
  735. "couldn't insert all characters (TTY is full?)\n");
  736. }
  737. /*
  738. * Only continue with trying to read the FIFO if all DMA chars have
  739. * been taken first.
  740. */
  741. if (dma_count == pending && readfifo) {
  742. /* Clear any error flags */
  743. ark_hsuart_clear_interrupt(uap, HSUART_INT_ERR);
  744. /*
  745. * If we read all the DMA'd characters, and we had an
  746. * incomplete buffer, that could be due to an rx error, or
  747. * maybe we just timed out. Read any pending chars and check
  748. * the error status.
  749. *
  750. * Error conditions will only occur in the FIFO, these will
  751. * trigger an immediate interrupt and stop the DMA job, so we
  752. * will always find the error in the FIFO, never in the DMA
  753. * buffer.
  754. */
  755. fifotaken = ark_hsuart_fifo_to_tty(uap);
  756. }
  757. spin_unlock(&uap->port.lock);
  758. dev_vdbg(uap->port.dev,
  759. "Took %d chars from DMA buffer and %d chars from the FIFO\n",
  760. dma_count, fifotaken);
  761. tty_flip_buffer_push(port);
  762. spin_lock(&uap->port.lock);
  763. }
  764. static void ark_hsuart_dma_rx_irq(struct ark_hsuart_port *uap)
  765. {
  766. struct ark_hsuart_dmarx_data *dmarx = &uap->dmarx;
  767. struct dma_chan *rxchan = dmarx->chan;
  768. struct ark_hsuart_sgbuf *sgbuf = dmarx->use_buf_b ?
  769. &dmarx->sgbuf_b : &dmarx->sgbuf_a;
  770. size_t pending;
  771. struct dma_tx_state state;
  772. enum dma_status dmastat;
  773. /*
  774. * Pause the transfer so we can trust the current counter,
  775. * do this before we pause the ARK_HSUART block, else we may
  776. * overflow the FIFO.
  777. */
  778. if (dmaengine_pause(rxchan))
  779. dev_err(uap->port.dev, "unable to pause DMA transfer\n");
  780. dmastat = rxchan->device->device_tx_status(rxchan,
  781. dmarx->cookie, &state);
  782. if (dmastat != DMA_PAUSED)
  783. dev_err(uap->port.dev, "unable to pause DMA transfer\n");
  784. /* Disable RX DMA - incoming data will wait in the FIFO */
  785. uap->dmacr &= ~HSUART_RXDMAEN;
  786. ark_hsuart_write_dmacr(uap, uap->dmacr);
  787. uap->dmarx.running = false;
  788. pending = sgbuf->sg.length - state.residue;
  789. BUG_ON(pending > ARK_HSUART_DMA_BUFFER_SIZE);
  790. /* Then we terminate the transfer - we now know our residue */
  791. dmaengine_terminate_all(rxchan);
  792. /*
  793. * This will take the chars we have so far and insert
  794. * into the framework.
  795. */
  796. ark_hsuart_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
  797. /* Switch buffer & re-trigger DMA job */
  798. dmarx->use_buf_b = !dmarx->use_buf_b;
  799. if (ark_hsuart_dma_rx_trigger_dma(uap)) {
  800. dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
  801. "fall back to interrupt mode\n");
  802. ark_hsuart_enable_interrupt(uap, HSUART_INT_RXD);
  803. }
  804. }
  805. static void ark_hsuart_dma_rx_callback(void *data)
  806. {
  807. struct ark_hsuart_port *uap = data;
  808. struct ark_hsuart_dmarx_data *dmarx = &uap->dmarx;
  809. struct dma_chan *rxchan = dmarx->chan;
  810. bool lastbuf = dmarx->use_buf_b;
  811. struct ark_hsuart_sgbuf *sgbuf = dmarx->use_buf_b ?
  812. &dmarx->sgbuf_b : &dmarx->sgbuf_a;
  813. size_t pending;
  814. struct dma_tx_state state;
  815. int ret;
  816. /*
  817. * This completion interrupt occurs typically when the
  818. * RX buffer is totally stuffed but no timeout has yet
  819. * occurred. When that happens, we just want the RX
  820. * routine to flush out the secondary DMA buffer while
  821. * we immediately trigger the next DMA job.
  822. */
  823. spin_lock_irq(&uap->port.lock);
  824. /*
  825. * Rx data can be taken by the UART interrupts during
  826. * the DMA irq handler. So we check the residue here.
  827. */
  828. rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
  829. pending = sgbuf->sg.length - state.residue;
  830. BUG_ON(pending > ARK_HSUART_DMA_BUFFER_SIZE);
  831. /* Then we terminate the transfer - we now know our residue */
  832. dmaengine_terminate_all(rxchan);
  833. uap->dmarx.running = false;
  834. dmarx->use_buf_b = !lastbuf;
  835. ret = ark_hsuart_dma_rx_trigger_dma(uap);
  836. ark_hsuart_dma_rx_chars(uap, pending, lastbuf, false);
  837. spin_unlock_irq(&uap->port.lock);
  838. /*
  839. * Do this check after we picked the DMA chars so we don't
  840. * get some IRQ immediately from RX.
  841. */
  842. if (ret) {
  843. dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
  844. "fall back to interrupt mode\n");
  845. ark_hsuart_enable_interrupt(uap, HSUART_INT_RXD);
  846. }
  847. }
  848. /*
  849. * Stop accepting received characters, when we're shutting down or
  850. * suspending this port.
  851. * Locking: called with port lock held and IRQs disabled.
  852. */
  853. static inline void ark_hsuart_dma_rx_stop(struct ark_hsuart_port *uap)
  854. {
  855. /* FIXME. Just disable the DMA enable */
  856. uap->dmacr &= ~HSUART_RXDMAEN;
  857. ark_hsuart_write_dmacr(uap, uap->dmacr);
  858. }
  859. static void ark_hsuart_dma_startup(struct ark_hsuart_port *uap)
  860. {
  861. int ret;
  862. if (!uap->dma_probed)
  863. ark_hsuart_dma_probe(uap);
  864. if (uap->dmatx.chan) {
  865. uap->dmatx.buf = kmalloc(ARK_HSUART_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
  866. if (!uap->dmatx.buf) {
  867. dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
  868. uap->port.fifosize = uap->fifosize;
  869. } else {
  870. sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, ARK_HSUART_DMA_BUFFER_SIZE);
  871. /* The DMA buffer is now the FIFO the TTY subsystem can use */
  872. uap->port.fifosize = ARK_HSUART_DMA_BUFFER_SIZE;
  873. uap->using_tx_dma = true;
  874. }
  875. }
  876. if (!uap->dmarx.chan)
  877. goto skip_rx;
  878. /* Allocate and map DMA RX buffers */
  879. ret = ark_hsuart_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
  880. DMA_FROM_DEVICE);
  881. if (ret) {
  882. dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
  883. "RX buffer A", ret);
  884. goto skip_rx;
  885. }
  886. ret = ark_hsuart_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
  887. DMA_FROM_DEVICE);
  888. if (ret) {
  889. dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
  890. "RX buffer B", ret);
  891. ark_hsuart_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
  892. DMA_FROM_DEVICE);
  893. goto skip_rx;
  894. }
  895. uap->using_rx_dma = true;
  896. skip_rx:
  897. /* Turn on DMA error (RX/TX will be enabled on demand) */
  898. ark_hsuart_write_dmacr(uap, uap->dmacr);
  899. /*
  900. * ST Micro variants has some specific dma burst threshold
  901. * compensation. Set this to 16 bytes, so burst will only
  902. * be issued above/below 16 bytes.
  903. */
  904. if (uap->using_rx_dma) {
  905. if (ark_hsuart_dma_rx_trigger_dma(uap))
  906. dev_dbg(uap->port.dev, "could not trigger initial "
  907. "RX DMA job, fall back to interrupt mode\n");
  908. }
  909. }
  910. static void ark_hsuart_dma_shutdown(struct ark_hsuart_port *uap)
  911. {
  912. if (!(uap->using_tx_dma || uap->using_rx_dma))
  913. return;
  914. /* Disable RX and TX DMA */
  915. while (!(readw(uap->port.membase + HSUART_UTS) & HSUART_UTS_TXFE))
  916. barrier();
  917. spin_lock_irq(&uap->port.lock);
  918. uap->dmacr &= ~(HSUART_RXDMAEN | HSUART_TXDMAEN);
  919. ark_hsuart_write_dmacr(uap, uap->dmacr);
  920. spin_unlock_irq(&uap->port.lock);
  921. if (uap->using_tx_dma) {
  922. /* In theory, this should already be done by ark_hsuart_dma_flush_buffer */
  923. dmaengine_terminate_all(uap->dmatx.chan);
  924. if (uap->dmatx.queued) {
  925. dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
  926. DMA_TO_DEVICE);
  927. uap->dmatx.queued = false;
  928. }
  929. kfree(uap->dmatx.buf);
  930. uap->using_tx_dma = false;
  931. }
  932. if (uap->using_rx_dma) {
  933. dmaengine_terminate_all(uap->dmarx.chan);
  934. /* Clean up the RX DMA */
  935. ark_hsuart_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
  936. ark_hsuart_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
  937. uap->using_rx_dma = false;
  938. }
  939. }
  940. static inline bool ark_hsuart_dma_rx_available(struct ark_hsuart_port *uap)
  941. {
  942. return uap->using_rx_dma;
  943. }
  944. static inline bool ark_hsuart_dma_rx_running(struct ark_hsuart_port *uap)
  945. {
  946. return uap->using_rx_dma && uap->dmarx.running;
  947. }
  948. #else /* CONFIG_DMA_ENGINE */
  949. /* Blank functions if the DMA engine is not available */
  950. static inline void ark_hsuart_dma_probe(struct ark_hsuart_port *uap)
  951. {
  952. }
  953. static inline void ark_hsuart_dma_remove(struct ark_hsuart_port *uap)
  954. {
  955. }
  956. static inline void ark_hsuart_dma_startup(struct ark_hsuart_port *uap)
  957. {
  958. }
  959. static inline void ark_hsuart_dma_shutdown(struct ark_hsuart_port *uap)
  960. {
  961. }
  962. static inline bool ark_hsuart_dma_tx_irq(struct ark_hsuart_port *uap)
  963. {
  964. return false;
  965. }
  966. static inline void ark_hsuart_dma_tx_stop(struct ark_hsuart_port *uap)
  967. {
  968. }
  969. static inline bool ark_hsuart_dma_tx_start(struct ark_hsuart_port *uap)
  970. {
  971. return false;
  972. }
  973. static inline void ark_hsuart_dma_rx_irq(struct ark_hsuart_port *uap)
  974. {
  975. }
  976. static inline void ark_hsuart_dma_rx_stop(struct ark_hsuart_port *uap)
  977. {
  978. }
  979. static inline int ark_hsuart_dma_rx_trigger_dma(struct ark_hsuart_port *uap)
  980. {
  981. return -EIO;
  982. }
  983. static inline bool ark_hsuart_dma_rx_available(struct ark_hsuart_port *uap)
  984. {
  985. return false;
  986. }
  987. static inline bool ark_hsuart_dma_rx_running(struct ark_hsuart_port *uap)
  988. {
  989. return false;
  990. }
  991. #define ark_hsuart_dma_flush_buffer NULL
  992. #endif /* CONFIG_DMA_ENGINE */
  993. /*
  994. * ark_hsuart_lockup_wa
  995. * This workaround aims to break the deadlock situation
  996. * when after long transfer over uart in hardware flow
  997. * control, uart interrupt registers cannot be cleared.
  998. * Hence uart transfer gets blocked.
  999. *
  1000. * It is seen that during such deadlock condition ICR
  1001. * don't get cleared even on multiple write. This leads
  1002. * pass_counter to decrease and finally reach zero. This
  1003. * can be taken as trigger point to run this UART_BT_WA.
  1004. *
  1005. */
  1006. static void ark_hsuart_lockup_wa(unsigned long data)
  1007. {
  1008. struct ark_hsuart_port *uap = ark_hsuart_ports[0];
  1009. void __iomem *base = uap->port.membase;
  1010. struct circ_buf *xmit = &uap->port.state->xmit;
  1011. struct tty_struct *tty = uap->port.state->port.tty;
  1012. int buf_empty_retries = 200;
  1013. int loop;
  1014. /* Stop HCI layer from submitting data for tx */
  1015. tty->hw_stopped = 1;
  1016. while (!uart_circ_empty(xmit)) {
  1017. if (buf_empty_retries-- == 0)
  1018. break;
  1019. udelay(100);
  1020. }
  1021. /* Backup registers */
  1022. for (loop = 0; loop < HSUART_WA_SAVE_NR; loop++)
  1023. hsuart_wa_regdata[loop] = readl(base + hsuart_wa_reg[loop]);
  1024. /* Disable UART so that FIFO data is flushed out */
  1025. writew(0x00, uap->port.membase + HSUART_UCR1);
  1026. /* Soft reset UART module */
  1027. /* Restore registers */
  1028. for (loop = 0; loop < HSUART_WA_SAVE_NR; loop++)
  1029. writew(hsuart_wa_regdata[loop] ,
  1030. uap->port.membase + hsuart_wa_reg[loop]);
  1031. /* Initialise the old status of the modem signals */
  1032. /* Start Tx/Rx */
  1033. tty->hw_stopped = 0;
  1034. }
  1035. static void ark_hsuart_stop_tx(struct uart_port *port)
  1036. {
  1037. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1038. ark_hsuart_disable_interrupt(uap, HSUART_INT_TXD);
  1039. ark_hsuart_dma_tx_stop(uap);
  1040. }
  1041. static void ark_hsuart_start_tx(struct uart_port *port)
  1042. {
  1043. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1044. if (!ark_hsuart_dma_tx_start(uap)) {
  1045. ark_hsuart_enable_interrupt(uap, HSUART_INT_TXD);
  1046. }
  1047. }
  1048. static void ark_hsuart_stop_rx(struct uart_port *port)
  1049. {
  1050. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1051. ark_hsuart_disable_interrupt(uap, HSUART_INT_RXD | HSUART_INT_RXTIMEOUT |
  1052. HSUART_INT_ERR);
  1053. ark_hsuart_dma_rx_stop(uap);
  1054. }
  1055. static void ark_hsuart_enable_ms(struct uart_port *port)
  1056. {
  1057. //struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1058. //uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
  1059. //writew(uap->im, uap->port.membase + UART011_IMSC);
  1060. }
  1061. static void ark_hsuart_rx_chars(struct ark_hsuart_port *uap)
  1062. {
  1063. struct tty_port *port = &uap->port.state->port;
  1064. ark_hsuart_fifo_to_tty(uap);
  1065. spin_unlock(&uap->port.lock);
  1066. tty_flip_buffer_push(port);
  1067. /*
  1068. * If we were temporarily out of DMA mode for a while,
  1069. * attempt to switch back to DMA mode again.
  1070. */
  1071. if (ark_hsuart_dma_rx_available(uap)) {
  1072. if (ark_hsuart_dma_rx_trigger_dma(uap)) {
  1073. dev_dbg(uap->port.dev, "could not trigger RX DMA job "
  1074. "fall back to interrupt mode again\n");
  1075. ark_hsuart_enable_interrupt(uap, HSUART_INT_RXD);
  1076. } else
  1077. ark_hsuart_disable_interrupt(uap, HSUART_INT_RXD);
  1078. }
  1079. spin_lock(&uap->port.lock);
  1080. }
  1081. static void ark_hsuart_tx_chars(struct ark_hsuart_port *uap)
  1082. {
  1083. struct circ_buf *xmit = &uap->port.state->xmit;
  1084. int count;
  1085. if (uap->port.x_char) {
  1086. writew(uap->port.x_char, uap->port.membase + HSUART_TXD);
  1087. uap->port.icount.tx++;
  1088. uap->port.x_char = 0;
  1089. return;
  1090. }
  1091. if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
  1092. ark_hsuart_stop_tx(&uap->port);
  1093. return;
  1094. }
  1095. /* If we are using DMA mode, try to send some characters. */
  1096. if (ark_hsuart_dma_tx_irq(uap))
  1097. return;
  1098. count = uap->fifosize >> 1;
  1099. do {
  1100. writew(xmit->buf[xmit->tail], uap->port.membase + HSUART_TXD);
  1101. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  1102. uap->port.icount.tx++;
  1103. if (uart_circ_empty(xmit))
  1104. break;
  1105. } while (--count > 0);
  1106. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  1107. uart_write_wakeup(&uap->port);
  1108. if (uart_circ_empty(xmit))
  1109. ark_hsuart_stop_tx(&uap->port);
  1110. }
  1111. /* static void ark_hsuart_modem_status(struct ark_hsuart_port *uap)
  1112. {
  1113. unsigned int status, delta;
  1114. status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  1115. delta = status ^ uap->old_status;
  1116. uap->old_status = status;
  1117. if (!delta)
  1118. return;
  1119. if (delta & UART01x_FR_DCD)
  1120. uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
  1121. if (delta & UART01x_FR_DSR)
  1122. uap->port.icount.dsr++;
  1123. if (delta & UART01x_FR_CTS)
  1124. uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
  1125. wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
  1126. } */
  1127. static irqreturn_t ark_hsuart_int(int irq, void *dev_id)
  1128. {
  1129. struct ark_hsuart_port *uap = dev_id;
  1130. unsigned long flags;
  1131. unsigned int status, pass_counter = ARK_ISR_PASS_LIMIT;
  1132. int handled = 0;
  1133. spin_lock_irqsave(&uap->port.lock, flags);
  1134. status = ark_hsuart_get_interrupt_status(uap);
  1135. if (status) {
  1136. do {
  1137. ark_hsuart_clear_interrupt(uap, status);
  1138. if (status & (HSUART_INT_RXD | HSUART_INT_RXTIMEOUT)) {
  1139. if (ark_hsuart_dma_rx_running(uap))
  1140. ark_hsuart_dma_rx_irq(uap);
  1141. else
  1142. ark_hsuart_rx_chars(uap);
  1143. }
  1144. /*if (status & (UART011_DSRMIS|UART011_DCDMIS|
  1145. UART011_CTSMIS|UART011_RIMIS))
  1146. ark_hsuart_modem_status(uap);*/
  1147. if (status & HSUART_INT_TXD)
  1148. ark_hsuart_tx_chars(uap);
  1149. if (status & HSUART_INT_RTSD)
  1150. uart_handle_cts_change(&uap->port, readw(uap->port.membase + HSUART_USR1) & (1 << 14));
  1151. if (pass_counter-- == 0) {
  1152. if (uap->interrupt_may_hang)
  1153. tasklet_schedule(&ark_hsuart_lockup_tlet);
  1154. break;
  1155. }
  1156. status = ark_hsuart_get_interrupt_status(uap);
  1157. } while (status != 0);
  1158. handled = 1;
  1159. }
  1160. spin_unlock_irqrestore(&uap->port.lock, flags);
  1161. return IRQ_RETVAL(handled);
  1162. }
  1163. static unsigned int ark_hsuart_tx_empty(struct uart_port *port)
  1164. {
  1165. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1166. unsigned int status = readw(uap->port.membase + HSUART_UTS);
  1167. return status & HSUART_UTS_TXFE ? 0 : TIOCSER_TEMT;
  1168. }
  1169. static unsigned int ark_hsuart_get_mctrl(struct uart_port *port)
  1170. {
  1171. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1172. unsigned int sigs = 0;
  1173. sigs = (readw(port->membase + HSUART_USR1) & (1 << 14)) ? TIOCM_CTS : 0;
  1174. sigs |= (uap->sigs & TIOCM_RTS);
  1175. return sigs;
  1176. }
  1177. static void ark_hsuart_set_mctrl(struct uart_port *port, unsigned int sigs)
  1178. {
  1179. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1180. unsigned int ucr2, ucr4;
  1181. uap->sigs = sigs;
  1182. if (sigs & TIOCM_RTS) {
  1183. ucr2 = readw(port->membase + HSUART_UCR2);
  1184. ucr2 |= (1 << 13);
  1185. writew(ucr2, port->membase + HSUART_UCR2);
  1186. ucr4 = readw(port->membase + HSUART_UCR4);
  1187. ucr4 &= ~(0x3F << 10);
  1188. ucr4 |= (uap->fifosize * 3 / 4) << 10;
  1189. writew(ucr4, port->membase + HSUART_UCR4);
  1190. }
  1191. }
  1192. static void ark_hsuart_break_ctl(struct uart_port *port, int break_state)
  1193. {
  1194. #if 0
  1195. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1196. unsigned long flags;
  1197. unsigned int lcr_h;
  1198. spin_lock_irqsave(&uap->port.lock, flags);
  1199. lcr_h = readw(uap->port.membase + uap->lcrh_tx);
  1200. if (break_state == -1)
  1201. lcr_h |= UART01x_LCRH_BRK;
  1202. else
  1203. lcr_h &= ~UART01x_LCRH_BRK;
  1204. writew(lcr_h, uap->port.membase + uap->lcrh_tx);
  1205. spin_unlock_irqrestore(&uap->port.lock, flags);
  1206. #endif
  1207. }
  1208. static int ark_hsuart_startup(struct uart_port *port)
  1209. {
  1210. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1211. int retval;
  1212. int hsuart_port= 0;
  1213. if(ark_hsuart_ports[0] == uap){
  1214. hsuart_port = 4;
  1215. }
  1216. else if (ark_hsuart_ports[1] == uap){
  1217. hsuart_port = 5;
  1218. }
  1219. uap->port.uartclk = clk_get_rate(uap->clk);
  1220. /* Clear pending error and receive interrupts */
  1221. ark_hsuart_clear_interrupt(uap, HSUART_INT_RXD | HSUART_INT_RXTIMEOUT |
  1222. HSUART_INT_TXD | HSUART_INT_ERR);
  1223. /*
  1224. * Allocate the IRQ
  1225. */
  1226. retval = request_irq(uap->port.irq, ark_hsuart_int, 0,
  1227. hsuartx_name[uap->port.line], uap);
  1228. if (retval)
  1229. goto clk_dis;
  1230. writew(((uap->fifosize >> 1) << 10) | (uap->fifosize >> 1) | (5 << 7),
  1231. uap->port.membase + HSUART_UFCR);
  1232. writew((1 << 14) | (1 << 12) | 7, uap->port.membase + HSUART_UCR2);
  1233. writew(0xF, uap->port.membase + HSUART_UBIR);
  1234. writew(1, uap->port.membase + HSUART_UCR1);
  1235. /*
  1236. * Provoke TX FIFO interrupt into asserting.
  1237. */
  1238. /*writew(0, uap->port.membase + HSUART_TXD);
  1239. while (!(readw(uap->port.membase + HSUART_USR2) & (1 << 3)))
  1240. barrier();*/
  1241. /* restore RTS and DTR */
  1242. /*
  1243. * initialise the old status of the modem signals
  1244. */
  1245. /* Startup DMA */
  1246. ark_hsuart_dma_startup(uap);
  1247. /*
  1248. * Finally, enable interrupts
  1249. */
  1250. spin_lock_irq(&uap->port.lock);
  1251. if (!ark_hsuart_dma_rx_running(uap))
  1252. ark_hsuart_enable_interrupt(uap, HSUART_INT_RXD | HSUART_INT_RXTIMEOUT | HSUART_INT_ERR);
  1253. else
  1254. ark_hsuart_enable_interrupt(uap, HSUART_INT_RXTIMEOUT | HSUART_INT_ERR);
  1255. spin_unlock_irq(&uap->port.lock);
  1256. return 0;
  1257. clk_dis:
  1258. return retval;
  1259. }
  1260. static void ark_hsuart_shutdown(struct uart_port *port)
  1261. {
  1262. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1263. /*
  1264. * disable all interrupts
  1265. */
  1266. spin_lock_irq(&uap->port.lock);
  1267. ark_hsuart_disable_interrupt(uap, HSUART_INT_RXD | HSUART_INT_RXTIMEOUT |
  1268. HSUART_INT_TXD | HSUART_INT_ERR);
  1269. spin_unlock_irq(&uap->port.lock);
  1270. ark_hsuart_dma_shutdown(uap);
  1271. /*
  1272. * Free the interrupt
  1273. */
  1274. free_irq(uap->port.irq, uap);
  1275. /*
  1276. * disable the port
  1277. * disable the port. It should not disable RTS and DTR.
  1278. * Also RTS and DTR state should be preserved to restore
  1279. * it during startup().
  1280. */
  1281. uap->autorts = false;
  1282. writew(readw(port->membase + HSUART_UCR1) & ~1, uap->port.membase + HSUART_UCR1);
  1283. /*
  1284. * disable break condition and fifos
  1285. */
  1286. /*
  1287. * Shut down the clock producer
  1288. */
  1289. }
  1290. static void
  1291. ark_hsuart_set_termios(struct uart_port *port, struct ktermios *termios,
  1292. struct ktermios *old)
  1293. {
  1294. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1295. unsigned int ucr2;
  1296. unsigned long flags;
  1297. unsigned int baud;
  1298. /*
  1299. * Ask the core to calculate the divisor for us.
  1300. */
  1301. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
  1302. printk("%s %d hsuart%d baud:%d c_cflag:0x%x\n",
  1303. __func__, __LINE__, port->line, baud, termios->c_cflag);
  1304. writew(readw(port->membase + HSUART_UCR1) & ~1, port->membase + HSUART_UCR1);
  1305. ucr2 = readw(port->membase + HSUART_UCR2);
  1306. ucr2 &= ~(0xF << 5);
  1307. switch (termios->c_cflag & CSIZE) {
  1308. case CS8:
  1309. ucr2 |= (1 << 5);
  1310. break;
  1311. }
  1312. if (termios->c_cflag & CSTOPB)
  1313. ucr2 |= (1 << 6);
  1314. if (termios->c_cflag & PARENB) {
  1315. ucr2 |= (1 << 8);
  1316. if (termios->c_cflag & PARODD)
  1317. ucr2 |= (1 << 7);
  1318. }
  1319. if (termios->c_cflag & CRTSCTS) {
  1320. ucr2 &= ~(1 << 14);
  1321. ark_hsuart_enable_interrupt(uap, HSUART_INT_RTSD);
  1322. }
  1323. else {
  1324. ucr2 |= (1 << 14);
  1325. ark_hsuart_disable_interrupt(uap, HSUART_INT_RTSD);
  1326. }
  1327. writew(ucr2, port->membase + HSUART_UCR2);
  1328. spin_lock_irqsave(&port->lock, flags);
  1329. /*
  1330. * Update the per-port timeout.
  1331. */
  1332. uart_update_timeout(port, termios->c_cflag, baud);
  1333. port->read_status_mask = HSUART_DR_OE | 255;
  1334. if (termios->c_iflag & INPCK)
  1335. port->read_status_mask |= HSUART_DR_FE | HSUART_DR_PE;
  1336. if (termios->c_iflag & (BRKINT | PARMRK))
  1337. port->read_status_mask |= HSUART_DR_BE;
  1338. /*
  1339. * Characters to ignore
  1340. */
  1341. port->ignore_status_mask = 0;
  1342. if (termios->c_iflag & IGNPAR)
  1343. port->ignore_status_mask |= HSUART_DR_FE | HSUART_DR_PE;
  1344. if (termios->c_iflag & IGNBRK) {
  1345. port->ignore_status_mask |= HSUART_DR_BE;
  1346. /*
  1347. * If we're ignoring parity and break indicators,
  1348. * ignore overruns too (for real raw support).
  1349. */
  1350. if (termios->c_iflag & IGNPAR)
  1351. port->ignore_status_mask |= HSUART_DR_OE;
  1352. }
  1353. /*
  1354. * Ignore all characters if CREAD is not set.
  1355. */
  1356. if ((termios->c_cflag & CREAD) == 0)
  1357. port->ignore_status_mask |= HSUART_DUMMY_DR_RX;
  1358. if (UART_ENABLE_MS(port, termios->c_cflag))
  1359. ark_hsuart_enable_ms(port);
  1360. /* Set baud rate */
  1361. writew(0xF, port->membase + HSUART_UBIR);
  1362. writew(port->uartclk / baud - 1, port->membase + HSUART_UBMR);
  1363. writew(readw(port->membase + HSUART_UCR1) | 1, port->membase + HSUART_UCR1);
  1364. spin_unlock_irqrestore(&port->lock, flags);
  1365. }
  1366. static const char *ark_hsuart_type(struct uart_port *port)
  1367. {
  1368. struct ark_hsuart_port *uap = (struct ark_hsuart_port *)port;
  1369. return uap->port.type == PORT_ARK ? "ARK HS UART" : NULL;
  1370. }
  1371. /*
  1372. * Configure/autoconfigure the port.
  1373. */
  1374. static void ark_hsuart_config_port(struct uart_port *port, int flags)
  1375. {
  1376. if (flags & UART_CONFIG_TYPE) {
  1377. port->type = PORT_ARK;
  1378. }
  1379. }
  1380. /*
  1381. * verify the new serial_struct (for TIOCSSERIAL).
  1382. */
  1383. static int ark_hsuart_verify_port(struct uart_port *port, struct serial_struct *ser)
  1384. {
  1385. int ret = 0;
  1386. if (ser->type != PORT_UNKNOWN && ser->type != PORT_ARK)
  1387. ret = -EINVAL;
  1388. if (ser->irq < 0 || ser->irq >= nr_irqs)
  1389. ret = -EINVAL;
  1390. if (ser->baud_base < 9600)
  1391. ret = -EINVAL;
  1392. return ret;
  1393. }
  1394. static struct uart_ops ark_hsuart_pops = {
  1395. .tx_empty = ark_hsuart_tx_empty,
  1396. .set_mctrl = ark_hsuart_set_mctrl,
  1397. .get_mctrl = ark_hsuart_get_mctrl,
  1398. .stop_tx = ark_hsuart_stop_tx,
  1399. .start_tx = ark_hsuart_start_tx,
  1400. .stop_rx = ark_hsuart_stop_rx,
  1401. .enable_ms = ark_hsuart_enable_ms,
  1402. .break_ctl = ark_hsuart_break_ctl,
  1403. .startup = ark_hsuart_startup,
  1404. .shutdown = ark_hsuart_shutdown,
  1405. .flush_buffer = ark_hsuart_dma_flush_buffer,
  1406. .set_termios = ark_hsuart_set_termios,
  1407. .type = ark_hsuart_type,
  1408. .config_port = ark_hsuart_config_port,
  1409. .verify_port = ark_hsuart_verify_port,
  1410. };
  1411. static struct uart_driver ark_hsuart_reg = {
  1412. .owner = THIS_MODULE,
  1413. .driver_name = "ttyHS",
  1414. .dev_name = "ttyHS",
  1415. .major = ARK_HSUART_MAJOR,
  1416. .minor = ARK_HSUART_MINOR,
  1417. .nr = HSUART_NR,
  1418. };
  1419. /*
  1420. * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
  1421. * could successfully get all information from dt or a negative errno.
  1422. */
  1423. static int ark_hsuart_probe_dt(struct ark_hsuart_port *uap,
  1424. struct platform_device *pdev)
  1425. {
  1426. struct device_node *np = pdev->dev.of_node;
  1427. int ret;
  1428. ret = of_alias_get_id(np, "hsserial");
  1429. if (ret < 0) {
  1430. dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
  1431. return ret;
  1432. }
  1433. uap->port.line = ret;
  1434. return 0;
  1435. }
  1436. static int ark_hsuart_probe(struct platform_device *pdev)
  1437. {
  1438. struct ark_hsuart_port *uap;
  1439. struct resource *res;
  1440. int irq;
  1441. void __iomem *base = NULL;
  1442. int ret;
  1443. uap = devm_kzalloc(&pdev->dev, sizeof(struct ark_hsuart_port), GFP_KERNEL);
  1444. if (uap == NULL) {
  1445. return -ENOMEM;
  1446. }
  1447. ret = ark_hsuart_probe_dt(uap, pdev);
  1448. if (ret > 0)
  1449. return ret;
  1450. if (uap->port.line >= ARRAY_SIZE(ark_hsuart_ports)) {
  1451. dev_err(&pdev->dev, "serial%d out of range\n",
  1452. uap->port.line);
  1453. return -EINVAL;
  1454. }
  1455. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1456. base = devm_ioremap_resource(&pdev->dev, res);
  1457. if (IS_ERR(base))
  1458. return PTR_ERR(base);
  1459. irq = platform_get_irq(pdev, 0);
  1460. if (irq < 0) {
  1461. dev_err(&pdev->dev, "no irq resource?\n");
  1462. return irq; /* -ENXIO */
  1463. }
  1464. uap->clk = devm_clk_get(&pdev->dev, NULL);
  1465. if (IS_ERR(uap->clk)) {
  1466. ret = PTR_ERR(uap->clk);
  1467. dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
  1468. return ret;
  1469. }
  1470. uap->fifosize = 32;
  1471. uap->port.dev = &pdev->dev;
  1472. uap->port.mapbase = res->start;
  1473. uap->port.membase = base;
  1474. uap->port.iotype = UPIO_MEM;
  1475. uap->port.irq = irq;
  1476. uap->port.fifosize = uap->fifosize;
  1477. uap->port.ops = &ark_hsuart_pops;
  1478. uap->port.flags = UPF_BOOT_AUTOCONF;
  1479. spin_lock_init(&uap->port.lock);
  1480. /* Ensure interrupts from this UART are masked and cleared */
  1481. ark_hsuart_disable_interrupt(uap, HSUART_INT_RXD | HSUART_INT_RXTIMEOUT |
  1482. HSUART_INT_TXD | HSUART_INT_ERR);
  1483. ark_hsuart_clear_interrupt(uap, HSUART_INT_RXD | HSUART_INT_RXTIMEOUT |
  1484. HSUART_INT_TXD | HSUART_INT_ERR);
  1485. ark_hsuart_ports[uap->port.line] = uap;
  1486. ret = uart_add_one_port(&ark_hsuart_reg, &uap->port);
  1487. if (ret) {
  1488. goto fail_uart_add_one_port;
  1489. }
  1490. platform_set_drvdata(pdev, uap);
  1491. return 0;
  1492. fail_uart_add_one_port:
  1493. platform_set_drvdata(pdev, NULL);
  1494. ark_hsuart_ports[uap->port.line] = NULL;
  1495. ark_hsuart_dma_remove(uap);
  1496. return ret;
  1497. }
  1498. static int ark_hsuart_remove(struct platform_device *pdev)
  1499. {
  1500. struct ark_hsuart_port *uap = platform_get_drvdata(pdev);
  1501. platform_set_drvdata(pdev, NULL);
  1502. uart_remove_one_port(&ark_hsuart_reg, &uap->port);
  1503. ark_hsuart_dma_remove(uap);
  1504. iounmap(uap->port.membase);
  1505. kfree(uap);
  1506. return 0;
  1507. }
  1508. #ifdef CONFIG_PM
  1509. static int ark_hsuart_suspend(struct device *dev)
  1510. {
  1511. struct platform_device *pdev = to_platform_device(dev);
  1512. struct ark_hsuart_port *uap = platform_get_drvdata(pdev);
  1513. if (!uap)
  1514. return -EINVAL;
  1515. return uart_suspend_port(&ark_hsuart_reg, &uap->port);
  1516. }
  1517. static int ark_hsuart_resume(struct device *dev)
  1518. {
  1519. struct platform_device *pdev = to_platform_device(dev);
  1520. struct ark_hsuart_port *uap = platform_get_drvdata(pdev);
  1521. if (!uap)
  1522. return -EINVAL;
  1523. return uart_resume_port(&ark_hsuart_reg, &uap->port);
  1524. }
  1525. static const struct dev_pm_ops ark_hsuart_pm_ops = {
  1526. .suspend = ark_hsuart_suspend,
  1527. .resume = ark_hsuart_resume,
  1528. };
  1529. #endif
  1530. static const struct of_device_id ark_hsuart_dt_ids[] = {
  1531. { .compatible = "arkmicro,ark-hsuart", },
  1532. { /* sentinel */ }
  1533. };
  1534. MODULE_DEVICE_TABLE(of, ark_hsuart_dt_ids);
  1535. static struct platform_driver ark_hsuart_driver = {
  1536. .probe = ark_hsuart_probe,
  1537. .remove = ark_hsuart_remove,
  1538. .driver = {
  1539. .name = "ark-hsuart",
  1540. .of_match_table = ark_hsuart_dt_ids,
  1541. #ifdef CONFIG_PM
  1542. .pm = &ark_hsuart_pm_ops,
  1543. #endif
  1544. },
  1545. };
  1546. static int __init ark_hsuart_init(void)
  1547. {
  1548. int ret;
  1549. ret = uart_register_driver(&ark_hsuart_reg);
  1550. if (ret == 0) {
  1551. ret = platform_driver_register(&ark_hsuart_driver);
  1552. if (ret)
  1553. uart_unregister_driver(&ark_hsuart_reg);
  1554. }
  1555. return ret;
  1556. }
  1557. static void __exit ark_hsuart_exit(void)
  1558. {
  1559. platform_driver_unregister(&ark_hsuart_driver);
  1560. uart_unregister_driver(&ark_hsuart_reg);
  1561. }
  1562. /*
  1563. * While this can be a module, if builtin it's most likely the console
  1564. * So let's leave module_exit but move module_init to an earlier place
  1565. */
  1566. arch_initcall(ark_hsuart_init);
  1567. module_exit(ark_hsuart_exit);
  1568. MODULE_AUTHOR("Sim, Arkmicro Ltd");
  1569. MODULE_DESCRIPTION("ARK high speed serial port driver");
  1570. MODULE_LICENSE("GPL");