max310x.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
  4. *
  5. * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
  6. *
  7. * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
  8. * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
  9. * Based on max3107.c, by Aavamobile
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/device.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/regmap.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/serial.h>
  22. #include <linux/tty.h>
  23. #include <linux/tty_flip.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/uaccess.h>
  26. #define MAX310X_NAME "max310x"
  27. #define MAX310X_MAJOR 204
  28. #define MAX310X_MINOR 209
  29. #define MAX310X_UART_NRMAX 16
  30. /* MAX310X register definitions */
  31. #define MAX310X_RHR_REG (0x00) /* RX FIFO */
  32. #define MAX310X_THR_REG (0x00) /* TX FIFO */
  33. #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
  34. #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
  35. #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
  36. #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
  37. #define MAX310X_REG_05 (0x05)
  38. #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
  39. #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
  40. #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
  41. #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
  42. #define MAX310X_MODE1_REG (0x09) /* MODE1 */
  43. #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
  44. #define MAX310X_LCR_REG (0x0b) /* LCR */
  45. #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
  46. #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
  47. #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
  48. #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
  49. #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
  50. #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
  51. #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
  52. #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
  53. #define MAX310X_XON1_REG (0x14) /* XON1 character */
  54. #define MAX310X_XON2_REG (0x15) /* XON2 character */
  55. #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
  56. #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
  57. #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
  58. #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
  59. #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
  60. #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
  61. #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
  62. #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
  63. #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
  64. #define MAX310X_REG_1F (0x1f)
  65. #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
  66. #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
  67. #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
  68. /* Extended registers */
  69. #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
  70. /* IRQ register bits */
  71. #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
  72. #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
  73. #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
  74. #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
  75. #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
  76. #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
  77. #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
  78. #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
  79. /* LSR register bits */
  80. #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
  81. #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
  82. #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
  83. #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
  84. #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
  85. #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
  86. #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
  87. /* Special character register bits */
  88. #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
  89. #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
  90. #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
  91. #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
  92. #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
  93. #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
  94. /* Status register bits */
  95. #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
  96. #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
  97. #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
  98. #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
  99. #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
  100. #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
  101. /* MODE1 register bits */
  102. #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
  103. #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
  104. #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
  105. #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
  106. #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
  107. #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
  108. #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
  109. #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
  110. /* MODE2 register bits */
  111. #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
  112. #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
  113. #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
  114. #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
  115. #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
  116. #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
  117. #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
  118. #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
  119. /* LCR register bits */
  120. #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
  121. #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
  122. *
  123. * Word length bits table:
  124. * 00 -> 5 bit words
  125. * 01 -> 6 bit words
  126. * 10 -> 7 bit words
  127. * 11 -> 8 bit words
  128. */
  129. #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
  130. *
  131. * STOP length bit table:
  132. * 0 -> 1 stop bit
  133. * 1 -> 1-1.5 stop bits if
  134. * word length is 5,
  135. * 2 stop bits otherwise
  136. */
  137. #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
  138. #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
  139. #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
  140. #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
  141. #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
  142. /* IRDA register bits */
  143. #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
  144. #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
  145. /* Flow control trigger level register masks */
  146. #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
  147. #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
  148. #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
  149. #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
  150. /* FIFO interrupt trigger level register masks */
  151. #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
  152. #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
  153. #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
  154. #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
  155. /* Flow control register bits */
  156. #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
  157. #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
  158. #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
  159. * are used in conjunction with
  160. * XOFF2 for definition of
  161. * special character */
  162. #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
  163. #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
  164. #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
  165. *
  166. * SWFLOW bits 1 & 0 table:
  167. * 00 -> no transmitter flow
  168. * control
  169. * 01 -> receiver compares
  170. * XON2 and XOFF2
  171. * and controls
  172. * transmitter
  173. * 10 -> receiver compares
  174. * XON1 and XOFF1
  175. * and controls
  176. * transmitter
  177. * 11 -> receiver compares
  178. * XON1, XON2, XOFF1 and
  179. * XOFF2 and controls
  180. * transmitter
  181. */
  182. #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
  183. #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
  184. *
  185. * SWFLOW bits 3 & 2 table:
  186. * 00 -> no received flow
  187. * control
  188. * 01 -> transmitter generates
  189. * XON2 and XOFF2
  190. * 10 -> transmitter generates
  191. * XON1 and XOFF1
  192. * 11 -> transmitter generates
  193. * XON1, XON2, XOFF1 and
  194. * XOFF2
  195. */
  196. /* PLL configuration register masks */
  197. #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
  198. #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
  199. /* Baud rate generator configuration register bits */
  200. #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
  201. #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
  202. /* Clock source register bits */
  203. #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
  204. #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
  205. #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
  206. #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
  207. #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
  208. /* Global commands */
  209. #define MAX310X_EXTREG_ENBL (0xce)
  210. #define MAX310X_EXTREG_DSBL (0xcd)
  211. /* Misc definitions */
  212. #define MAX310X_FIFO_SIZE (128)
  213. #define MAX310x_REV_MASK (0xf8)
  214. #define MAX310X_WRITE_BIT 0x80
  215. /* MAX3107 specific */
  216. #define MAX3107_REV_ID (0xa0)
  217. /* MAX3109 specific */
  218. #define MAX3109_REV_ID (0xc0)
  219. /* MAX14830 specific */
  220. #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
  221. #define MAX14830_REV_ID (0xb0)
  222. struct max310x_devtype {
  223. char name[9];
  224. int nr;
  225. int (*detect)(struct device *);
  226. void (*power)(struct uart_port *, int);
  227. };
  228. struct max310x_one {
  229. struct uart_port port;
  230. struct work_struct tx_work;
  231. struct work_struct md_work;
  232. struct work_struct rs_work;
  233. };
  234. struct max310x_port {
  235. struct max310x_devtype *devtype;
  236. struct regmap *regmap;
  237. struct mutex mutex;
  238. struct clk *clk;
  239. #ifdef CONFIG_GPIOLIB
  240. struct gpio_chip gpio;
  241. #endif
  242. struct max310x_one p[0];
  243. };
  244. static struct uart_driver max310x_uart = {
  245. .owner = THIS_MODULE,
  246. .driver_name = MAX310X_NAME,
  247. .dev_name = "ttyMAX",
  248. .major = MAX310X_MAJOR,
  249. .minor = MAX310X_MINOR,
  250. .nr = MAX310X_UART_NRMAX,
  251. };
  252. static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
  253. static u8 max310x_port_read(struct uart_port *port, u8 reg)
  254. {
  255. struct max310x_port *s = dev_get_drvdata(port->dev);
  256. unsigned int val = 0;
  257. regmap_read(s->regmap, port->iobase + reg, &val);
  258. return val;
  259. }
  260. static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
  261. {
  262. struct max310x_port *s = dev_get_drvdata(port->dev);
  263. regmap_write(s->regmap, port->iobase + reg, val);
  264. }
  265. static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
  266. {
  267. struct max310x_port *s = dev_get_drvdata(port->dev);
  268. regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
  269. }
  270. static int max3107_detect(struct device *dev)
  271. {
  272. struct max310x_port *s = dev_get_drvdata(dev);
  273. unsigned int val = 0;
  274. int ret;
  275. ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
  276. if (ret)
  277. return ret;
  278. if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
  279. dev_err(dev,
  280. "%s ID 0x%02x does not match\n", s->devtype->name, val);
  281. return -ENODEV;
  282. }
  283. return 0;
  284. }
  285. static int max3108_detect(struct device *dev)
  286. {
  287. struct max310x_port *s = dev_get_drvdata(dev);
  288. unsigned int val = 0;
  289. int ret;
  290. /* MAX3108 have not REV ID register, we just check default value
  291. * from clocksource register to make sure everything works.
  292. */
  293. ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
  294. if (ret)
  295. return ret;
  296. if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
  297. dev_err(dev, "%s not present\n", s->devtype->name);
  298. return -ENODEV;
  299. }
  300. return 0;
  301. }
  302. static int max3109_detect(struct device *dev)
  303. {
  304. struct max310x_port *s = dev_get_drvdata(dev);
  305. unsigned int val = 0;
  306. int ret;
  307. ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
  308. MAX310X_EXTREG_ENBL);
  309. if (ret)
  310. return ret;
  311. regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
  312. regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
  313. if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
  314. dev_err(dev,
  315. "%s ID 0x%02x does not match\n", s->devtype->name, val);
  316. return -ENODEV;
  317. }
  318. return 0;
  319. }
  320. static void max310x_power(struct uart_port *port, int on)
  321. {
  322. max310x_port_update(port, MAX310X_MODE1_REG,
  323. MAX310X_MODE1_FORCESLEEP_BIT,
  324. on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
  325. if (on)
  326. msleep(50);
  327. }
  328. static int max14830_detect(struct device *dev)
  329. {
  330. struct max310x_port *s = dev_get_drvdata(dev);
  331. unsigned int val = 0;
  332. int ret;
  333. ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
  334. MAX310X_EXTREG_ENBL);
  335. if (ret)
  336. return ret;
  337. regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
  338. regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
  339. if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
  340. dev_err(dev,
  341. "%s ID 0x%02x does not match\n", s->devtype->name, val);
  342. return -ENODEV;
  343. }
  344. return 0;
  345. }
  346. static void max14830_power(struct uart_port *port, int on)
  347. {
  348. max310x_port_update(port, MAX310X_BRGCFG_REG,
  349. MAX14830_BRGCFG_CLKDIS_BIT,
  350. on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
  351. if (on)
  352. msleep(50);
  353. }
  354. static const struct max310x_devtype max3107_devtype = {
  355. .name = "MAX3107",
  356. .nr = 1,
  357. .detect = max3107_detect,
  358. .power = max310x_power,
  359. };
  360. static const struct max310x_devtype max3108_devtype = {
  361. .name = "MAX3108",
  362. .nr = 1,
  363. .detect = max3108_detect,
  364. .power = max310x_power,
  365. };
  366. static const struct max310x_devtype max3109_devtype = {
  367. .name = "MAX3109",
  368. .nr = 2,
  369. .detect = max3109_detect,
  370. .power = max310x_power,
  371. };
  372. static const struct max310x_devtype max14830_devtype = {
  373. .name = "MAX14830",
  374. .nr = 4,
  375. .detect = max14830_detect,
  376. .power = max14830_power,
  377. };
  378. static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
  379. {
  380. switch (reg & 0x1f) {
  381. case MAX310X_IRQSTS_REG:
  382. case MAX310X_LSR_IRQSTS_REG:
  383. case MAX310X_SPCHR_IRQSTS_REG:
  384. case MAX310X_STS_IRQSTS_REG:
  385. case MAX310X_TXFIFOLVL_REG:
  386. case MAX310X_RXFIFOLVL_REG:
  387. return false;
  388. default:
  389. break;
  390. }
  391. return true;
  392. }
  393. static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
  394. {
  395. switch (reg & 0x1f) {
  396. case MAX310X_RHR_REG:
  397. case MAX310X_IRQSTS_REG:
  398. case MAX310X_LSR_IRQSTS_REG:
  399. case MAX310X_SPCHR_IRQSTS_REG:
  400. case MAX310X_STS_IRQSTS_REG:
  401. case MAX310X_TXFIFOLVL_REG:
  402. case MAX310X_RXFIFOLVL_REG:
  403. case MAX310X_GPIODATA_REG:
  404. case MAX310X_BRGDIVLSB_REG:
  405. case MAX310X_REG_05:
  406. case MAX310X_REG_1F:
  407. return true;
  408. default:
  409. break;
  410. }
  411. return false;
  412. }
  413. static bool max310x_reg_precious(struct device *dev, unsigned int reg)
  414. {
  415. switch (reg & 0x1f) {
  416. case MAX310X_RHR_REG:
  417. case MAX310X_IRQSTS_REG:
  418. case MAX310X_SPCHR_IRQSTS_REG:
  419. case MAX310X_STS_IRQSTS_REG:
  420. return true;
  421. default:
  422. break;
  423. }
  424. return false;
  425. }
  426. static int max310x_set_baud(struct uart_port *port, int baud)
  427. {
  428. unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
  429. /*
  430. * Calculate the integer divisor first. Select a proper mode
  431. * in case if the requested baud is too high for the pre-defined
  432. * clocks frequency.
  433. */
  434. div = port->uartclk / baud;
  435. if (div < 8) {
  436. /* Mode x4 */
  437. c = 4;
  438. mode = MAX310X_BRGCFG_4XMODE_BIT;
  439. } else if (div < 16) {
  440. /* Mode x2 */
  441. c = 8;
  442. mode = MAX310X_BRGCFG_2XMODE_BIT;
  443. } else {
  444. c = 16;
  445. }
  446. /* Calculate the divisor in accordance with the fraction coefficient */
  447. div /= c;
  448. F = c*baud;
  449. /* Calculate the baud rate fraction */
  450. if (div > 0)
  451. frac = (16*(port->uartclk % F)) / F;
  452. else
  453. div = 1;
  454. max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
  455. max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
  456. max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
  457. /* Return the actual baud rate we just programmed */
  458. return (16*port->uartclk) / (c*(16*div + frac));
  459. }
  460. static int max310x_update_best_err(unsigned long f, long *besterr)
  461. {
  462. /* Use baudrate 115200 for calculate error */
  463. long err = f % (460800 * 16);
  464. if ((*besterr < 0) || (*besterr > err)) {
  465. *besterr = err;
  466. return 0;
  467. }
  468. return 1;
  469. }
  470. static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
  471. unsigned long freq, bool xtal)
  472. {
  473. unsigned int div, clksrc, pllcfg = 0;
  474. long besterr = -1;
  475. unsigned long fdiv, fmul, bestfreq = freq;
  476. /* First, update error without PLL */
  477. max310x_update_best_err(freq, &besterr);
  478. /* Try all possible PLL dividers */
  479. for (div = 1; (div <= 63) && besterr; div++) {
  480. fdiv = DIV_ROUND_CLOSEST(freq, div);
  481. /* Try multiplier 6 */
  482. fmul = fdiv * 6;
  483. if ((fdiv >= 500000) && (fdiv <= 800000))
  484. if (!max310x_update_best_err(fmul, &besterr)) {
  485. pllcfg = (0 << 6) | div;
  486. bestfreq = fmul;
  487. }
  488. /* Try multiplier 48 */
  489. fmul = fdiv * 48;
  490. if ((fdiv >= 850000) && (fdiv <= 1200000))
  491. if (!max310x_update_best_err(fmul, &besterr)) {
  492. pllcfg = (1 << 6) | div;
  493. bestfreq = fmul;
  494. }
  495. /* Try multiplier 96 */
  496. fmul = fdiv * 96;
  497. if ((fdiv >= 425000) && (fdiv <= 1000000))
  498. if (!max310x_update_best_err(fmul, &besterr)) {
  499. pllcfg = (2 << 6) | div;
  500. bestfreq = fmul;
  501. }
  502. /* Try multiplier 144 */
  503. fmul = fdiv * 144;
  504. if ((fdiv >= 390000) && (fdiv <= 667000))
  505. if (!max310x_update_best_err(fmul, &besterr)) {
  506. pllcfg = (3 << 6) | div;
  507. bestfreq = fmul;
  508. }
  509. }
  510. /* Configure clock source */
  511. clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
  512. /* Configure PLL */
  513. if (pllcfg) {
  514. clksrc |= MAX310X_CLKSRC_PLL_BIT;
  515. regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
  516. } else
  517. clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
  518. regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
  519. /* Wait for crystal */
  520. if (xtal) {
  521. unsigned int val;
  522. msleep(10);
  523. regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
  524. if (!(val & MAX310X_STS_CLKREADY_BIT)) {
  525. dev_warn(dev, "clock is not stable yet\n");
  526. }
  527. }
  528. return (int)bestfreq;
  529. }
  530. static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
  531. {
  532. u8 header[] = { (port->iobase + MAX310X_THR_REG) | MAX310X_WRITE_BIT };
  533. struct spi_transfer xfer[] = {
  534. {
  535. .tx_buf = &header,
  536. .len = sizeof(header),
  537. }, {
  538. .tx_buf = txbuf,
  539. .len = len,
  540. }
  541. };
  542. spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
  543. }
  544. static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
  545. {
  546. u8 header[] = { port->iobase + MAX310X_RHR_REG };
  547. struct spi_transfer xfer[] = {
  548. {
  549. .tx_buf = &header,
  550. .len = sizeof(header),
  551. }, {
  552. .rx_buf = rxbuf,
  553. .len = len,
  554. }
  555. };
  556. spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
  557. }
  558. static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
  559. {
  560. unsigned int sts, ch, flag, i;
  561. u8 buf[MAX310X_FIFO_SIZE];
  562. if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
  563. /* We are just reading, happily ignoring any error conditions.
  564. * Break condition, parity checking, framing errors -- they
  565. * are all ignored. That means that we can do a batch-read.
  566. *
  567. * There is a small opportunity for race if the RX FIFO
  568. * overruns while we're reading the buffer; the datasheets says
  569. * that the LSR register applies to the "current" character.
  570. * That's also the reason why we cannot do batched reads when
  571. * asked to check the individual statuses.
  572. * */
  573. sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
  574. max310x_batch_read(port, buf, rxlen);
  575. port->icount.rx += rxlen;
  576. flag = TTY_NORMAL;
  577. sts &= port->read_status_mask;
  578. if (sts & MAX310X_LSR_RXOVR_BIT) {
  579. dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
  580. port->icount.overrun++;
  581. }
  582. for (i = 0; i < rxlen; ++i) {
  583. uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag);
  584. }
  585. } else {
  586. if (unlikely(rxlen >= port->fifosize)) {
  587. dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
  588. port->icount.buf_overrun++;
  589. /* Ensure sanity of RX level */
  590. rxlen = port->fifosize;
  591. }
  592. while (rxlen--) {
  593. ch = max310x_port_read(port, MAX310X_RHR_REG);
  594. sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
  595. sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
  596. MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
  597. port->icount.rx++;
  598. flag = TTY_NORMAL;
  599. if (unlikely(sts)) {
  600. if (sts & MAX310X_LSR_RXBRK_BIT) {
  601. port->icount.brk++;
  602. if (uart_handle_break(port))
  603. continue;
  604. } else if (sts & MAX310X_LSR_RXPAR_BIT)
  605. port->icount.parity++;
  606. else if (sts & MAX310X_LSR_FRERR_BIT)
  607. port->icount.frame++;
  608. else if (sts & MAX310X_LSR_RXOVR_BIT)
  609. port->icount.overrun++;
  610. sts &= port->read_status_mask;
  611. if (sts & MAX310X_LSR_RXBRK_BIT)
  612. flag = TTY_BREAK;
  613. else if (sts & MAX310X_LSR_RXPAR_BIT)
  614. flag = TTY_PARITY;
  615. else if (sts & MAX310X_LSR_FRERR_BIT)
  616. flag = TTY_FRAME;
  617. else if (sts & MAX310X_LSR_RXOVR_BIT)
  618. flag = TTY_OVERRUN;
  619. }
  620. if (uart_handle_sysrq_char(port, ch))
  621. continue;
  622. if (sts & port->ignore_status_mask)
  623. continue;
  624. uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
  625. }
  626. }
  627. tty_flip_buffer_push(&port->state->port);
  628. }
  629. static void max310x_handle_tx(struct uart_port *port)
  630. {
  631. struct circ_buf *xmit = &port->state->xmit;
  632. unsigned int txlen, to_send, until_end;
  633. if (unlikely(port->x_char)) {
  634. max310x_port_write(port, MAX310X_THR_REG, port->x_char);
  635. port->icount.tx++;
  636. port->x_char = 0;
  637. return;
  638. }
  639. if (uart_circ_empty(xmit) || uart_tx_stopped(port))
  640. return;
  641. /* Get length of data pending in circular buffer */
  642. to_send = uart_circ_chars_pending(xmit);
  643. until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  644. if (likely(to_send)) {
  645. /* Limit to size of TX FIFO */
  646. txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
  647. txlen = port->fifosize - txlen;
  648. to_send = (to_send > txlen) ? txlen : to_send;
  649. if (until_end < to_send) {
  650. /* It's a circ buffer -- wrap around.
  651. * We could do that in one SPI transaction, but meh. */
  652. max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
  653. max310x_batch_write(port, xmit->buf, to_send - until_end);
  654. } else {
  655. max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
  656. }
  657. /* Add data to send */
  658. port->icount.tx += to_send;
  659. xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
  660. }
  661. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  662. uart_write_wakeup(port);
  663. }
  664. static void max310x_start_tx(struct uart_port *port)
  665. {
  666. struct max310x_one *one = container_of(port, struct max310x_one, port);
  667. if (!work_pending(&one->tx_work))
  668. schedule_work(&one->tx_work);
  669. }
  670. static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
  671. {
  672. struct uart_port *port = &s->p[portno].port;
  673. irqreturn_t res = IRQ_NONE;
  674. do {
  675. unsigned int ists, lsr, rxlen;
  676. /* Read IRQ status & RX FIFO level */
  677. ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
  678. rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
  679. if (!ists && !rxlen)
  680. break;
  681. res = IRQ_HANDLED;
  682. if (ists & MAX310X_IRQ_CTS_BIT) {
  683. lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
  684. uart_handle_cts_change(port,
  685. !!(lsr & MAX310X_LSR_CTS_BIT));
  686. }
  687. if (rxlen)
  688. max310x_handle_rx(port, rxlen);
  689. if (ists & MAX310X_IRQ_TXEMPTY_BIT)
  690. max310x_start_tx(port);
  691. } while (1);
  692. return res;
  693. }
  694. static irqreturn_t max310x_ist(int irq, void *dev_id)
  695. {
  696. struct max310x_port *s = (struct max310x_port *)dev_id;
  697. bool handled = false;
  698. if (s->devtype->nr > 1) {
  699. do {
  700. unsigned int val = ~0;
  701. WARN_ON_ONCE(regmap_read(s->regmap,
  702. MAX310X_GLOBALIRQ_REG, &val));
  703. val = ((1 << s->devtype->nr) - 1) & ~val;
  704. if (!val)
  705. break;
  706. if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
  707. handled = true;
  708. } while (1);
  709. } else {
  710. if (max310x_port_irq(s, 0) == IRQ_HANDLED)
  711. handled = true;
  712. }
  713. return IRQ_RETVAL(handled);
  714. }
  715. static void max310x_wq_proc(struct work_struct *ws)
  716. {
  717. struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
  718. struct max310x_port *s = dev_get_drvdata(one->port.dev);
  719. mutex_lock(&s->mutex);
  720. max310x_handle_tx(&one->port);
  721. mutex_unlock(&s->mutex);
  722. }
  723. static unsigned int max310x_tx_empty(struct uart_port *port)
  724. {
  725. u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
  726. return lvl ? 0 : TIOCSER_TEMT;
  727. }
  728. static unsigned int max310x_get_mctrl(struct uart_port *port)
  729. {
  730. /* DCD and DSR are not wired and CTS/RTS is handled automatically
  731. * so just indicate DSR and CAR asserted
  732. */
  733. return TIOCM_DSR | TIOCM_CAR;
  734. }
  735. static void max310x_md_proc(struct work_struct *ws)
  736. {
  737. struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
  738. max310x_port_update(&one->port, MAX310X_MODE2_REG,
  739. MAX310X_MODE2_LOOPBACK_BIT,
  740. (one->port.mctrl & TIOCM_LOOP) ?
  741. MAX310X_MODE2_LOOPBACK_BIT : 0);
  742. }
  743. static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
  744. {
  745. struct max310x_one *one = container_of(port, struct max310x_one, port);
  746. schedule_work(&one->md_work);
  747. }
  748. static void max310x_break_ctl(struct uart_port *port, int break_state)
  749. {
  750. max310x_port_update(port, MAX310X_LCR_REG,
  751. MAX310X_LCR_TXBREAK_BIT,
  752. break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
  753. }
  754. static void max310x_set_termios(struct uart_port *port,
  755. struct ktermios *termios,
  756. struct ktermios *old)
  757. {
  758. unsigned int lcr = 0, flow = 0;
  759. int baud;
  760. /* Mask termios capabilities we don't support */
  761. termios->c_cflag &= ~CMSPAR;
  762. /* Word size */
  763. switch (termios->c_cflag & CSIZE) {
  764. case CS5:
  765. break;
  766. case CS6:
  767. lcr = MAX310X_LCR_LENGTH0_BIT;
  768. break;
  769. case CS7:
  770. lcr = MAX310X_LCR_LENGTH1_BIT;
  771. break;
  772. case CS8:
  773. default:
  774. lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
  775. break;
  776. }
  777. /* Parity */
  778. if (termios->c_cflag & PARENB) {
  779. lcr |= MAX310X_LCR_PARITY_BIT;
  780. if (!(termios->c_cflag & PARODD))
  781. lcr |= MAX310X_LCR_EVENPARITY_BIT;
  782. }
  783. /* Stop bits */
  784. if (termios->c_cflag & CSTOPB)
  785. lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
  786. /* Update LCR register */
  787. max310x_port_write(port, MAX310X_LCR_REG, lcr);
  788. /* Set read status mask */
  789. port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
  790. if (termios->c_iflag & INPCK)
  791. port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
  792. MAX310X_LSR_FRERR_BIT;
  793. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  794. port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
  795. /* Set status ignore mask */
  796. port->ignore_status_mask = 0;
  797. if (termios->c_iflag & IGNBRK)
  798. port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
  799. if (!(termios->c_cflag & CREAD))
  800. port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
  801. MAX310X_LSR_RXOVR_BIT |
  802. MAX310X_LSR_FRERR_BIT |
  803. MAX310X_LSR_RXBRK_BIT;
  804. /* Configure flow control */
  805. max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
  806. max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
  807. if (termios->c_cflag & CRTSCTS)
  808. flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
  809. MAX310X_FLOWCTRL_AUTORTS_BIT;
  810. if (termios->c_iflag & IXON)
  811. flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
  812. MAX310X_FLOWCTRL_SWFLOWEN_BIT;
  813. if (termios->c_iflag & IXOFF)
  814. flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
  815. MAX310X_FLOWCTRL_SWFLOWEN_BIT;
  816. max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
  817. /* Get baud rate generator configuration */
  818. baud = uart_get_baud_rate(port, termios, old,
  819. port->uartclk / 16 / 0xffff,
  820. port->uartclk / 4);
  821. /* Setup baudrate generator */
  822. baud = max310x_set_baud(port, baud);
  823. /* Update timeout according to new baud rate */
  824. uart_update_timeout(port, termios->c_cflag, baud);
  825. }
  826. static void max310x_rs_proc(struct work_struct *ws)
  827. {
  828. struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
  829. unsigned int val;
  830. val = (one->port.rs485.delay_rts_before_send << 4) |
  831. one->port.rs485.delay_rts_after_send;
  832. max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);
  833. if (one->port.rs485.flags & SER_RS485_ENABLED) {
  834. max310x_port_update(&one->port, MAX310X_MODE1_REG,
  835. MAX310X_MODE1_TRNSCVCTRL_BIT,
  836. MAX310X_MODE1_TRNSCVCTRL_BIT);
  837. max310x_port_update(&one->port, MAX310X_MODE2_REG,
  838. MAX310X_MODE2_ECHOSUPR_BIT,
  839. MAX310X_MODE2_ECHOSUPR_BIT);
  840. } else {
  841. max310x_port_update(&one->port, MAX310X_MODE1_REG,
  842. MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
  843. max310x_port_update(&one->port, MAX310X_MODE2_REG,
  844. MAX310X_MODE2_ECHOSUPR_BIT, 0);
  845. }
  846. }
  847. static int max310x_rs485_config(struct uart_port *port,
  848. struct serial_rs485 *rs485)
  849. {
  850. struct max310x_one *one = container_of(port, struct max310x_one, port);
  851. if ((rs485->delay_rts_before_send > 0x0f) ||
  852. (rs485->delay_rts_after_send > 0x0f))
  853. return -ERANGE;
  854. rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
  855. memset(rs485->padding, 0, sizeof(rs485->padding));
  856. port->rs485 = *rs485;
  857. schedule_work(&one->rs_work);
  858. return 0;
  859. }
  860. static int max310x_startup(struct uart_port *port)
  861. {
  862. struct max310x_port *s = dev_get_drvdata(port->dev);
  863. unsigned int val;
  864. s->devtype->power(port, 1);
  865. /* Configure MODE1 register */
  866. max310x_port_update(port, MAX310X_MODE1_REG,
  867. MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
  868. /* Configure MODE2 register & Reset FIFOs*/
  869. val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
  870. max310x_port_write(port, MAX310X_MODE2_REG, val);
  871. max310x_port_update(port, MAX310X_MODE2_REG,
  872. MAX310X_MODE2_FIFORST_BIT, 0);
  873. /* Configure flow control levels */
  874. /* Flow control halt level 96, resume level 48 */
  875. max310x_port_write(port, MAX310X_FLOWLVL_REG,
  876. MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
  877. /* Clear IRQ status register */
  878. max310x_port_read(port, MAX310X_IRQSTS_REG);
  879. /* Enable RX, TX, CTS change interrupts */
  880. val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
  881. max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
  882. return 0;
  883. }
  884. static void max310x_shutdown(struct uart_port *port)
  885. {
  886. struct max310x_port *s = dev_get_drvdata(port->dev);
  887. /* Disable all interrupts */
  888. max310x_port_write(port, MAX310X_IRQEN_REG, 0);
  889. s->devtype->power(port, 0);
  890. }
  891. static const char *max310x_type(struct uart_port *port)
  892. {
  893. struct max310x_port *s = dev_get_drvdata(port->dev);
  894. return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
  895. }
  896. static int max310x_request_port(struct uart_port *port)
  897. {
  898. /* Do nothing */
  899. return 0;
  900. }
  901. static void max310x_config_port(struct uart_port *port, int flags)
  902. {
  903. if (flags & UART_CONFIG_TYPE)
  904. port->type = PORT_MAX310X;
  905. }
  906. static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
  907. {
  908. if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
  909. return -EINVAL;
  910. if (s->irq != port->irq)
  911. return -EINVAL;
  912. return 0;
  913. }
  914. static void max310x_null_void(struct uart_port *port)
  915. {
  916. /* Do nothing */
  917. }
  918. static const struct uart_ops max310x_ops = {
  919. .tx_empty = max310x_tx_empty,
  920. .set_mctrl = max310x_set_mctrl,
  921. .get_mctrl = max310x_get_mctrl,
  922. .stop_tx = max310x_null_void,
  923. .start_tx = max310x_start_tx,
  924. .stop_rx = max310x_null_void,
  925. .break_ctl = max310x_break_ctl,
  926. .startup = max310x_startup,
  927. .shutdown = max310x_shutdown,
  928. .set_termios = max310x_set_termios,
  929. .type = max310x_type,
  930. .request_port = max310x_request_port,
  931. .release_port = max310x_null_void,
  932. .config_port = max310x_config_port,
  933. .verify_port = max310x_verify_port,
  934. };
  935. static int __maybe_unused max310x_suspend(struct device *dev)
  936. {
  937. struct max310x_port *s = dev_get_drvdata(dev);
  938. int i;
  939. for (i = 0; i < s->devtype->nr; i++) {
  940. uart_suspend_port(&max310x_uart, &s->p[i].port);
  941. s->devtype->power(&s->p[i].port, 0);
  942. }
  943. return 0;
  944. }
  945. static int __maybe_unused max310x_resume(struct device *dev)
  946. {
  947. struct max310x_port *s = dev_get_drvdata(dev);
  948. int i;
  949. for (i = 0; i < s->devtype->nr; i++) {
  950. s->devtype->power(&s->p[i].port, 1);
  951. uart_resume_port(&max310x_uart, &s->p[i].port);
  952. }
  953. return 0;
  954. }
  955. static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
  956. #ifdef CONFIG_GPIOLIB
  957. static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
  958. {
  959. unsigned int val;
  960. struct max310x_port *s = gpiochip_get_data(chip);
  961. struct uart_port *port = &s->p[offset / 4].port;
  962. val = max310x_port_read(port, MAX310X_GPIODATA_REG);
  963. return !!((val >> 4) & (1 << (offset % 4)));
  964. }
  965. static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  966. {
  967. struct max310x_port *s = gpiochip_get_data(chip);
  968. struct uart_port *port = &s->p[offset / 4].port;
  969. max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
  970. value ? 1 << (offset % 4) : 0);
  971. }
  972. static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  973. {
  974. struct max310x_port *s = gpiochip_get_data(chip);
  975. struct uart_port *port = &s->p[offset / 4].port;
  976. max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
  977. return 0;
  978. }
  979. static int max310x_gpio_direction_output(struct gpio_chip *chip,
  980. unsigned offset, int value)
  981. {
  982. struct max310x_port *s = gpiochip_get_data(chip);
  983. struct uart_port *port = &s->p[offset / 4].port;
  984. max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
  985. value ? 1 << (offset % 4) : 0);
  986. max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
  987. 1 << (offset % 4));
  988. return 0;
  989. }
  990. static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  991. unsigned long config)
  992. {
  993. struct max310x_port *s = gpiochip_get_data(chip);
  994. struct uart_port *port = &s->p[offset / 4].port;
  995. switch (pinconf_to_config_param(config)) {
  996. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  997. max310x_port_update(port, MAX310X_GPIOCFG_REG,
  998. 1 << ((offset % 4) + 4),
  999. 1 << ((offset % 4) + 4));
  1000. return 0;
  1001. case PIN_CONFIG_DRIVE_PUSH_PULL:
  1002. max310x_port_update(port, MAX310X_GPIOCFG_REG,
  1003. 1 << ((offset % 4) + 4), 0);
  1004. return 0;
  1005. default:
  1006. return -ENOTSUPP;
  1007. }
  1008. }
  1009. #endif
  1010. static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
  1011. struct regmap *regmap, int irq)
  1012. {
  1013. int i, ret, fmin, fmax, freq, uartclk;
  1014. struct clk *clk_osc, *clk_xtal;
  1015. struct max310x_port *s;
  1016. bool xtal = false;
  1017. if (IS_ERR(regmap))
  1018. return PTR_ERR(regmap);
  1019. /* Alloc port structure */
  1020. s = devm_kzalloc(dev, sizeof(*s) +
  1021. sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
  1022. if (!s) {
  1023. dev_err(dev, "Error allocating port structure\n");
  1024. return -ENOMEM;
  1025. }
  1026. clk_osc = devm_clk_get(dev, "osc");
  1027. clk_xtal = devm_clk_get(dev, "xtal");
  1028. if (!IS_ERR(clk_osc)) {
  1029. s->clk = clk_osc;
  1030. fmin = 500000;
  1031. fmax = 35000000;
  1032. } else if (!IS_ERR(clk_xtal)) {
  1033. s->clk = clk_xtal;
  1034. fmin = 1000000;
  1035. fmax = 4000000;
  1036. xtal = true;
  1037. } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
  1038. PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
  1039. return -EPROBE_DEFER;
  1040. } else {
  1041. dev_err(dev, "Cannot get clock\n");
  1042. return -EINVAL;
  1043. }
  1044. ret = clk_prepare_enable(s->clk);
  1045. if (ret)
  1046. return ret;
  1047. freq = clk_get_rate(s->clk);
  1048. /* Check frequency limits */
  1049. if (freq < fmin || freq > fmax) {
  1050. ret = -ERANGE;
  1051. goto out_clk;
  1052. }
  1053. s->regmap = regmap;
  1054. s->devtype = devtype;
  1055. dev_set_drvdata(dev, s);
  1056. /* Check device to ensure we are talking to what we expect */
  1057. ret = devtype->detect(dev);
  1058. if (ret)
  1059. goto out_clk;
  1060. for (i = 0; i < devtype->nr; i++) {
  1061. unsigned int offs = i << 5;
  1062. /* Reset port */
  1063. regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
  1064. MAX310X_MODE2_RST_BIT);
  1065. /* Clear port reset */
  1066. regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
  1067. /* Wait for port startup */
  1068. do {
  1069. regmap_read(s->regmap,
  1070. MAX310X_BRGDIVLSB_REG + offs, &ret);
  1071. } while (ret != 0x01);
  1072. regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
  1073. MAX310X_MODE1_AUTOSLEEP_BIT,
  1074. MAX310X_MODE1_AUTOSLEEP_BIT);
  1075. }
  1076. uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
  1077. dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
  1078. mutex_init(&s->mutex);
  1079. for (i = 0; i < devtype->nr; i++) {
  1080. unsigned int line;
  1081. line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
  1082. if (line == MAX310X_UART_NRMAX) {
  1083. ret = -ERANGE;
  1084. goto out_uart;
  1085. }
  1086. /* Initialize port data */
  1087. s->p[i].port.line = line;
  1088. s->p[i].port.dev = dev;
  1089. s->p[i].port.irq = irq;
  1090. s->p[i].port.type = PORT_MAX310X;
  1091. s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
  1092. s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
  1093. s->p[i].port.iotype = UPIO_PORT;
  1094. s->p[i].port.iobase = i * 0x20;
  1095. s->p[i].port.membase = (void __iomem *)~0;
  1096. s->p[i].port.uartclk = uartclk;
  1097. s->p[i].port.rs485_config = max310x_rs485_config;
  1098. s->p[i].port.ops = &max310x_ops;
  1099. /* Disable all interrupts */
  1100. max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
  1101. /* Clear IRQ status register */
  1102. max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
  1103. /* Enable IRQ pin */
  1104. max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
  1105. MAX310X_MODE1_IRQSEL_BIT,
  1106. MAX310X_MODE1_IRQSEL_BIT);
  1107. /* Initialize queue for start TX */
  1108. INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
  1109. /* Initialize queue for changing LOOPBACK mode */
  1110. INIT_WORK(&s->p[i].md_work, max310x_md_proc);
  1111. /* Initialize queue for changing RS485 mode */
  1112. INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
  1113. /* Register port */
  1114. ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
  1115. if (ret) {
  1116. s->p[i].port.dev = NULL;
  1117. goto out_uart;
  1118. }
  1119. set_bit(line, max310x_lines);
  1120. /* Go to suspend mode */
  1121. devtype->power(&s->p[i].port, 0);
  1122. }
  1123. #ifdef CONFIG_GPIOLIB
  1124. /* Setup GPIO cotroller */
  1125. s->gpio.owner = THIS_MODULE;
  1126. s->gpio.parent = dev;
  1127. s->gpio.label = devtype->name;
  1128. s->gpio.direction_input = max310x_gpio_direction_input;
  1129. s->gpio.get = max310x_gpio_get;
  1130. s->gpio.direction_output= max310x_gpio_direction_output;
  1131. s->gpio.set = max310x_gpio_set;
  1132. s->gpio.set_config = max310x_gpio_set_config;
  1133. s->gpio.base = -1;
  1134. s->gpio.ngpio = devtype->nr * 4;
  1135. s->gpio.can_sleep = 1;
  1136. ret = devm_gpiochip_add_data(dev, &s->gpio, s);
  1137. if (ret)
  1138. goto out_uart;
  1139. #endif
  1140. /* Setup interrupt */
  1141. ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
  1142. IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
  1143. if (!ret)
  1144. return 0;
  1145. dev_err(dev, "Unable to reguest IRQ %i\n", irq);
  1146. out_uart:
  1147. for (i = 0; i < devtype->nr; i++) {
  1148. if (s->p[i].port.dev) {
  1149. uart_remove_one_port(&max310x_uart, &s->p[i].port);
  1150. clear_bit(s->p[i].port.line, max310x_lines);
  1151. }
  1152. }
  1153. mutex_destroy(&s->mutex);
  1154. out_clk:
  1155. clk_disable_unprepare(s->clk);
  1156. return ret;
  1157. }
  1158. static int max310x_remove(struct device *dev)
  1159. {
  1160. struct max310x_port *s = dev_get_drvdata(dev);
  1161. int i;
  1162. for (i = 0; i < s->devtype->nr; i++) {
  1163. cancel_work_sync(&s->p[i].tx_work);
  1164. cancel_work_sync(&s->p[i].md_work);
  1165. cancel_work_sync(&s->p[i].rs_work);
  1166. uart_remove_one_port(&max310x_uart, &s->p[i].port);
  1167. clear_bit(s->p[i].port.line, max310x_lines);
  1168. s->devtype->power(&s->p[i].port, 0);
  1169. }
  1170. mutex_destroy(&s->mutex);
  1171. clk_disable_unprepare(s->clk);
  1172. return 0;
  1173. }
  1174. static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
  1175. { .compatible = "maxim,max3107", .data = &max3107_devtype, },
  1176. { .compatible = "maxim,max3108", .data = &max3108_devtype, },
  1177. { .compatible = "maxim,max3109", .data = &max3109_devtype, },
  1178. { .compatible = "maxim,max14830", .data = &max14830_devtype },
  1179. { }
  1180. };
  1181. MODULE_DEVICE_TABLE(of, max310x_dt_ids);
  1182. static struct regmap_config regcfg = {
  1183. .reg_bits = 8,
  1184. .val_bits = 8,
  1185. .write_flag_mask = MAX310X_WRITE_BIT,
  1186. .cache_type = REGCACHE_RBTREE,
  1187. .writeable_reg = max310x_reg_writeable,
  1188. .volatile_reg = max310x_reg_volatile,
  1189. .precious_reg = max310x_reg_precious,
  1190. };
  1191. #ifdef CONFIG_SPI_MASTER
  1192. static int max310x_spi_probe(struct spi_device *spi)
  1193. {
  1194. struct max310x_devtype *devtype;
  1195. struct regmap *regmap;
  1196. int ret;
  1197. /* Setup SPI bus */
  1198. spi->bits_per_word = 8;
  1199. spi->mode = spi->mode ? : SPI_MODE_0;
  1200. spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
  1201. ret = spi_setup(spi);
  1202. if (ret)
  1203. return ret;
  1204. if (spi->dev.of_node) {
  1205. const struct of_device_id *of_id =
  1206. of_match_device(max310x_dt_ids, &spi->dev);
  1207. if (!of_id)
  1208. return -ENODEV;
  1209. devtype = (struct max310x_devtype *)of_id->data;
  1210. } else {
  1211. const struct spi_device_id *id_entry = spi_get_device_id(spi);
  1212. devtype = (struct max310x_devtype *)id_entry->driver_data;
  1213. }
  1214. regcfg.max_register = devtype->nr * 0x20 - 1;
  1215. regmap = devm_regmap_init_spi(spi, &regcfg);
  1216. return max310x_probe(&spi->dev, devtype, regmap, spi->irq);
  1217. }
  1218. static int max310x_spi_remove(struct spi_device *spi)
  1219. {
  1220. return max310x_remove(&spi->dev);
  1221. }
  1222. static const struct spi_device_id max310x_id_table[] = {
  1223. { "max3107", (kernel_ulong_t)&max3107_devtype, },
  1224. { "max3108", (kernel_ulong_t)&max3108_devtype, },
  1225. { "max3109", (kernel_ulong_t)&max3109_devtype, },
  1226. { "max14830", (kernel_ulong_t)&max14830_devtype, },
  1227. { }
  1228. };
  1229. MODULE_DEVICE_TABLE(spi, max310x_id_table);
  1230. static struct spi_driver max310x_spi_driver = {
  1231. .driver = {
  1232. .name = MAX310X_NAME,
  1233. .of_match_table = of_match_ptr(max310x_dt_ids),
  1234. .pm = &max310x_pm_ops,
  1235. },
  1236. .probe = max310x_spi_probe,
  1237. .remove = max310x_spi_remove,
  1238. .id_table = max310x_id_table,
  1239. };
  1240. #endif
  1241. static int __init max310x_uart_init(void)
  1242. {
  1243. int ret;
  1244. bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
  1245. ret = uart_register_driver(&max310x_uart);
  1246. if (ret)
  1247. return ret;
  1248. #ifdef CONFIG_SPI_MASTER
  1249. spi_register_driver(&max310x_spi_driver);
  1250. #endif
  1251. return 0;
  1252. }
  1253. module_init(max310x_uart_init);
  1254. static void __exit max310x_uart_exit(void)
  1255. {
  1256. #ifdef CONFIG_SPI_MASTER
  1257. spi_unregister_driver(&max310x_spi_driver);
  1258. #endif
  1259. uart_unregister_driver(&max310x_uart);
  1260. }
  1261. module_exit(max310x_uart_exit);
  1262. MODULE_LICENSE("GPL");
  1263. MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
  1264. MODULE_DESCRIPTION("MAX310X serial driver");