mps2-uart.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MPS2 UART driver
  4. *
  5. * Copyright (C) 2015 ARM Limited
  6. *
  7. * Author: Vladimir Murzin <vladimir.murzin@arm.com>
  8. *
  9. * TODO: support for SysRq
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/bitops.h>
  13. #include <linux/clk.h>
  14. #include <linux/console.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/tty_flip.h>
  22. #include <linux/types.h>
  23. #define SERIAL_NAME "ttyMPS"
  24. #define DRIVER_NAME "mps2-uart"
  25. #define MAKE_NAME(x) (DRIVER_NAME # x)
  26. #define UARTn_DATA 0x00
  27. #define UARTn_STATE 0x04
  28. #define UARTn_STATE_TX_FULL BIT(0)
  29. #define UARTn_STATE_RX_FULL BIT(1)
  30. #define UARTn_STATE_TX_OVERRUN BIT(2)
  31. #define UARTn_STATE_RX_OVERRUN BIT(3)
  32. #define UARTn_CTRL 0x08
  33. #define UARTn_CTRL_TX_ENABLE BIT(0)
  34. #define UARTn_CTRL_RX_ENABLE BIT(1)
  35. #define UARTn_CTRL_TX_INT_ENABLE BIT(2)
  36. #define UARTn_CTRL_RX_INT_ENABLE BIT(3)
  37. #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
  38. #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
  39. #define UARTn_INT 0x0c
  40. #define UARTn_INT_TX BIT(0)
  41. #define UARTn_INT_RX BIT(1)
  42. #define UARTn_INT_TX_OVERRUN BIT(2)
  43. #define UARTn_INT_RX_OVERRUN BIT(3)
  44. #define UARTn_BAUDDIV 0x10
  45. #define UARTn_BAUDDIV_MASK GENMASK(20, 0)
  46. /*
  47. * Helpers to make typical enable/disable operations more readable.
  48. */
  49. #define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
  50. UARTn_CTRL_TX_INT_ENABLE |\
  51. UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
  52. #define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
  53. UARTn_CTRL_RX_INT_ENABLE |\
  54. UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
  55. #define MPS2_MAX_PORTS 3
  56. struct mps2_uart_port {
  57. struct uart_port port;
  58. struct clk *clk;
  59. unsigned int tx_irq;
  60. unsigned int rx_irq;
  61. };
  62. static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
  63. {
  64. return container_of(port, struct mps2_uart_port, port);
  65. }
  66. static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
  67. {
  68. struct mps2_uart_port *mps_port = to_mps2_port(port);
  69. writeb(val, mps_port->port.membase + off);
  70. }
  71. static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
  72. {
  73. struct mps2_uart_port *mps_port = to_mps2_port(port);
  74. return readb(mps_port->port.membase + off);
  75. }
  76. static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
  77. {
  78. struct mps2_uart_port *mps_port = to_mps2_port(port);
  79. writel_relaxed(val, mps_port->port.membase + off);
  80. }
  81. static unsigned int mps2_uart_tx_empty(struct uart_port *port)
  82. {
  83. u8 status = mps2_uart_read8(port, UARTn_STATE);
  84. return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
  85. }
  86. static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  87. {
  88. }
  89. static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
  90. {
  91. return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
  92. }
  93. static void mps2_uart_stop_tx(struct uart_port *port)
  94. {
  95. u8 control = mps2_uart_read8(port, UARTn_CTRL);
  96. control &= ~UARTn_CTRL_TX_INT_ENABLE;
  97. mps2_uart_write8(port, control, UARTn_CTRL);
  98. }
  99. static void mps2_uart_tx_chars(struct uart_port *port)
  100. {
  101. struct circ_buf *xmit = &port->state->xmit;
  102. while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
  103. if (port->x_char) {
  104. mps2_uart_write8(port, port->x_char, UARTn_DATA);
  105. port->x_char = 0;
  106. port->icount.tx++;
  107. continue;
  108. }
  109. if (uart_circ_empty(xmit) || uart_tx_stopped(port))
  110. break;
  111. mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
  112. xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
  113. port->icount.tx++;
  114. }
  115. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  116. uart_write_wakeup(port);
  117. if (uart_circ_empty(xmit))
  118. mps2_uart_stop_tx(port);
  119. }
  120. static void mps2_uart_start_tx(struct uart_port *port)
  121. {
  122. u8 control = mps2_uart_read8(port, UARTn_CTRL);
  123. control |= UARTn_CTRL_TX_INT_ENABLE;
  124. mps2_uart_write8(port, control, UARTn_CTRL);
  125. /*
  126. * We've just unmasked the TX IRQ and now slow-starting via
  127. * polling; if there is enough data to fill up the internal
  128. * write buffer in one go, the TX IRQ should assert, at which
  129. * point we switch to fully interrupt-driven TX.
  130. */
  131. mps2_uart_tx_chars(port);
  132. }
  133. static void mps2_uart_stop_rx(struct uart_port *port)
  134. {
  135. u8 control = mps2_uart_read8(port, UARTn_CTRL);
  136. control &= ~UARTn_CTRL_RX_GRP;
  137. mps2_uart_write8(port, control, UARTn_CTRL);
  138. }
  139. static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
  140. {
  141. }
  142. static void mps2_uart_rx_chars(struct uart_port *port)
  143. {
  144. struct tty_port *tport = &port->state->port;
  145. while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
  146. u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
  147. port->icount.rx++;
  148. tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
  149. }
  150. tty_flip_buffer_push(tport);
  151. }
  152. static irqreturn_t mps2_uart_rxirq(int irq, void *data)
  153. {
  154. struct uart_port *port = data;
  155. u8 irqflag = mps2_uart_read8(port, UARTn_INT);
  156. if (unlikely(!(irqflag & UARTn_INT_RX)))
  157. return IRQ_NONE;
  158. spin_lock(&port->lock);
  159. mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
  160. mps2_uart_rx_chars(port);
  161. spin_unlock(&port->lock);
  162. return IRQ_HANDLED;
  163. }
  164. static irqreturn_t mps2_uart_txirq(int irq, void *data)
  165. {
  166. struct uart_port *port = data;
  167. u8 irqflag = mps2_uart_read8(port, UARTn_INT);
  168. if (unlikely(!(irqflag & UARTn_INT_TX)))
  169. return IRQ_NONE;
  170. spin_lock(&port->lock);
  171. mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
  172. mps2_uart_tx_chars(port);
  173. spin_unlock(&port->lock);
  174. return IRQ_HANDLED;
  175. }
  176. static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
  177. {
  178. irqreturn_t handled = IRQ_NONE;
  179. struct uart_port *port = data;
  180. u8 irqflag = mps2_uart_read8(port, UARTn_INT);
  181. spin_lock(&port->lock);
  182. if (irqflag & UARTn_INT_RX_OVERRUN) {
  183. struct tty_port *tport = &port->state->port;
  184. mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
  185. port->icount.overrun++;
  186. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  187. tty_flip_buffer_push(tport);
  188. handled = IRQ_HANDLED;
  189. }
  190. /*
  191. * It's never been seen in practice and it never *should* happen since
  192. * we check if there is enough room in TX buffer before sending data.
  193. * So we keep this check in case something suspicious has happened.
  194. */
  195. if (irqflag & UARTn_INT_TX_OVERRUN) {
  196. mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
  197. handled = IRQ_HANDLED;
  198. }
  199. spin_unlock(&port->lock);
  200. return handled;
  201. }
  202. static int mps2_uart_startup(struct uart_port *port)
  203. {
  204. struct mps2_uart_port *mps_port = to_mps2_port(port);
  205. u8 control = mps2_uart_read8(port, UARTn_CTRL);
  206. int ret;
  207. control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
  208. mps2_uart_write8(port, control, UARTn_CTRL);
  209. ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
  210. MAKE_NAME(-rx), mps_port);
  211. if (ret) {
  212. dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
  213. return ret;
  214. }
  215. ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
  216. MAKE_NAME(-tx), mps_port);
  217. if (ret) {
  218. dev_err(port->dev, "failed to register txirq (%d)\n", ret);
  219. goto err_free_rxirq;
  220. }
  221. ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
  222. MAKE_NAME(-overrun), mps_port);
  223. if (ret) {
  224. dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
  225. goto err_free_txirq;
  226. }
  227. control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
  228. mps2_uart_write8(port, control, UARTn_CTRL);
  229. return 0;
  230. err_free_txirq:
  231. free_irq(mps_port->tx_irq, mps_port);
  232. err_free_rxirq:
  233. free_irq(mps_port->rx_irq, mps_port);
  234. return ret;
  235. }
  236. static void mps2_uart_shutdown(struct uart_port *port)
  237. {
  238. struct mps2_uart_port *mps_port = to_mps2_port(port);
  239. u8 control = mps2_uart_read8(port, UARTn_CTRL);
  240. control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
  241. mps2_uart_write8(port, control, UARTn_CTRL);
  242. free_irq(mps_port->rx_irq, mps_port);
  243. free_irq(mps_port->tx_irq, mps_port);
  244. free_irq(port->irq, mps_port);
  245. }
  246. static void
  247. mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
  248. struct ktermios *old)
  249. {
  250. unsigned long flags;
  251. unsigned int baud, bauddiv;
  252. termios->c_cflag &= ~(CRTSCTS | CMSPAR);
  253. termios->c_cflag &= ~CSIZE;
  254. termios->c_cflag |= CS8;
  255. termios->c_cflag &= ~PARENB;
  256. termios->c_cflag &= ~CSTOPB;
  257. baud = uart_get_baud_rate(port, termios, old,
  258. DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
  259. DIV_ROUND_CLOSEST(port->uartclk, 16));
  260. bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
  261. spin_lock_irqsave(&port->lock, flags);
  262. uart_update_timeout(port, termios->c_cflag, baud);
  263. mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
  264. spin_unlock_irqrestore(&port->lock, flags);
  265. if (tty_termios_baud_rate(termios))
  266. tty_termios_encode_baud_rate(termios, baud, baud);
  267. }
  268. static const char *mps2_uart_type(struct uart_port *port)
  269. {
  270. return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
  271. }
  272. static void mps2_uart_release_port(struct uart_port *port)
  273. {
  274. }
  275. static int mps2_uart_request_port(struct uart_port *port)
  276. {
  277. return 0;
  278. }
  279. static void mps2_uart_config_port(struct uart_port *port, int type)
  280. {
  281. if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
  282. port->type = PORT_MPS2UART;
  283. }
  284. static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
  285. {
  286. return -EINVAL;
  287. }
  288. static const struct uart_ops mps2_uart_pops = {
  289. .tx_empty = mps2_uart_tx_empty,
  290. .set_mctrl = mps2_uart_set_mctrl,
  291. .get_mctrl = mps2_uart_get_mctrl,
  292. .stop_tx = mps2_uart_stop_tx,
  293. .start_tx = mps2_uart_start_tx,
  294. .stop_rx = mps2_uart_stop_rx,
  295. .break_ctl = mps2_uart_break_ctl,
  296. .startup = mps2_uart_startup,
  297. .shutdown = mps2_uart_shutdown,
  298. .set_termios = mps2_uart_set_termios,
  299. .type = mps2_uart_type,
  300. .release_port = mps2_uart_release_port,
  301. .request_port = mps2_uart_request_port,
  302. .config_port = mps2_uart_config_port,
  303. .verify_port = mps2_uart_verify_port,
  304. };
  305. static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS];
  306. #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
  307. static void mps2_uart_console_putchar(struct uart_port *port, int ch)
  308. {
  309. while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
  310. cpu_relax();
  311. mps2_uart_write8(port, ch, UARTn_DATA);
  312. }
  313. static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
  314. {
  315. struct uart_port *port = &mps2_uart_ports[co->index].port;
  316. uart_console_write(port, s, cnt, mps2_uart_console_putchar);
  317. }
  318. static int mps2_uart_console_setup(struct console *co, char *options)
  319. {
  320. struct mps2_uart_port *mps_port;
  321. int baud = 9600;
  322. int bits = 8;
  323. int parity = 'n';
  324. int flow = 'n';
  325. if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
  326. return -ENODEV;
  327. mps_port = &mps2_uart_ports[co->index];
  328. if (options)
  329. uart_parse_options(options, &baud, &parity, &bits, &flow);
  330. return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
  331. }
  332. static struct uart_driver mps2_uart_driver;
  333. static struct console mps2_uart_console = {
  334. .name = SERIAL_NAME,
  335. .device = uart_console_device,
  336. .write = mps2_uart_console_write,
  337. .setup = mps2_uart_console_setup,
  338. .flags = CON_PRINTBUFFER,
  339. .index = -1,
  340. .data = &mps2_uart_driver,
  341. };
  342. #define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
  343. static void mps2_early_putchar(struct uart_port *port, int ch)
  344. {
  345. while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
  346. cpu_relax();
  347. writeb((unsigned char)ch, port->membase + UARTn_DATA);
  348. }
  349. static void mps2_early_write(struct console *con, const char *s, unsigned int n)
  350. {
  351. struct earlycon_device *dev = con->data;
  352. uart_console_write(&dev->port, s, n, mps2_early_putchar);
  353. }
  354. static int __init mps2_early_console_setup(struct earlycon_device *device,
  355. const char *opt)
  356. {
  357. if (!device->port.membase)
  358. return -ENODEV;
  359. device->con->write = mps2_early_write;
  360. return 0;
  361. }
  362. OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup);
  363. #else
  364. #define MPS2_SERIAL_CONSOLE NULL
  365. #endif
  366. static struct uart_driver mps2_uart_driver = {
  367. .driver_name = DRIVER_NAME,
  368. .dev_name = SERIAL_NAME,
  369. .nr = MPS2_MAX_PORTS,
  370. .cons = MPS2_SERIAL_CONSOLE,
  371. };
  372. static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev)
  373. {
  374. struct device_node *np = pdev->dev.of_node;
  375. int id;
  376. if (!np)
  377. return NULL;
  378. id = of_alias_get_id(np, "serial");
  379. if (id < 0)
  380. id = 0;
  381. if (WARN_ON(id >= MPS2_MAX_PORTS))
  382. return NULL;
  383. mps2_uart_ports[id].port.line = id;
  384. return &mps2_uart_ports[id];
  385. }
  386. static int mps2_init_port(struct mps2_uart_port *mps_port,
  387. struct platform_device *pdev)
  388. {
  389. struct resource *res;
  390. int ret;
  391. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  392. mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
  393. if (IS_ERR(mps_port->port.membase))
  394. return PTR_ERR(mps_port->port.membase);
  395. mps_port->port.mapbase = res->start;
  396. mps_port->port.mapsize = resource_size(res);
  397. mps_port->rx_irq = platform_get_irq(pdev, 0);
  398. mps_port->tx_irq = platform_get_irq(pdev, 1);
  399. mps_port->port.irq = platform_get_irq(pdev, 2);
  400. mps_port->port.iotype = UPIO_MEM;
  401. mps_port->port.flags = UPF_BOOT_AUTOCONF;
  402. mps_port->port.fifosize = 1;
  403. mps_port->port.ops = &mps2_uart_pops;
  404. mps_port->port.dev = &pdev->dev;
  405. mps_port->clk = devm_clk_get(&pdev->dev, NULL);
  406. if (IS_ERR(mps_port->clk))
  407. return PTR_ERR(mps_port->clk);
  408. ret = clk_prepare_enable(mps_port->clk);
  409. if (ret)
  410. return ret;
  411. mps_port->port.uartclk = clk_get_rate(mps_port->clk);
  412. clk_disable_unprepare(mps_port->clk);
  413. return ret;
  414. }
  415. static int mps2_serial_probe(struct platform_device *pdev)
  416. {
  417. struct mps2_uart_port *mps_port;
  418. int ret;
  419. mps_port = mps2_of_get_port(pdev);
  420. if (!mps_port)
  421. return -ENODEV;
  422. ret = mps2_init_port(mps_port, pdev);
  423. if (ret)
  424. return ret;
  425. ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
  426. if (ret)
  427. return ret;
  428. platform_set_drvdata(pdev, mps_port);
  429. return 0;
  430. }
  431. #ifdef CONFIG_OF
  432. static const struct of_device_id mps2_match[] = {
  433. { .compatible = "arm,mps2-uart", },
  434. {},
  435. };
  436. #endif
  437. static struct platform_driver mps2_serial_driver = {
  438. .probe = mps2_serial_probe,
  439. .driver = {
  440. .name = DRIVER_NAME,
  441. .of_match_table = of_match_ptr(mps2_match),
  442. .suppress_bind_attrs = true,
  443. },
  444. };
  445. static int __init mps2_uart_init(void)
  446. {
  447. int ret;
  448. ret = uart_register_driver(&mps2_uart_driver);
  449. if (ret)
  450. return ret;
  451. ret = platform_driver_register(&mps2_serial_driver);
  452. if (ret)
  453. uart_unregister_driver(&mps2_uart_driver);
  454. return ret;
  455. }
  456. arch_initcall(mps2_uart_init);