netx-serial.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  4. */
  5. #if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  6. #define SUPPORT_SYSRQ
  7. #endif
  8. #include <linux/device.h>
  9. #include <linux/module.h>
  10. #include <linux/ioport.h>
  11. #include <linux/init.h>
  12. #include <linux/console.h>
  13. #include <linux/sysrq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/tty.h>
  16. #include <linux/tty_flip.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/serial.h>
  19. #include <asm/io.h>
  20. #include <asm/irq.h>
  21. #include <mach/hardware.h>
  22. #include <mach/netx-regs.h>
  23. /* We've been assigned a range on the "Low-density serial ports" major */
  24. #define SERIAL_NX_MAJOR 204
  25. #define MINOR_START 170
  26. enum uart_regs {
  27. UART_DR = 0x00,
  28. UART_SR = 0x04,
  29. UART_LINE_CR = 0x08,
  30. UART_BAUDDIV_MSB = 0x0c,
  31. UART_BAUDDIV_LSB = 0x10,
  32. UART_CR = 0x14,
  33. UART_FR = 0x18,
  34. UART_IIR = 0x1c,
  35. UART_ILPR = 0x20,
  36. UART_RTS_CR = 0x24,
  37. UART_RTS_LEAD = 0x28,
  38. UART_RTS_TRAIL = 0x2c,
  39. UART_DRV_ENABLE = 0x30,
  40. UART_BRM_CR = 0x34,
  41. UART_RXFIFO_IRQLEVEL = 0x38,
  42. UART_TXFIFO_IRQLEVEL = 0x3c,
  43. };
  44. #define SR_FE (1<<0)
  45. #define SR_PE (1<<1)
  46. #define SR_BE (1<<2)
  47. #define SR_OE (1<<3)
  48. #define LINE_CR_BRK (1<<0)
  49. #define LINE_CR_PEN (1<<1)
  50. #define LINE_CR_EPS (1<<2)
  51. #define LINE_CR_STP2 (1<<3)
  52. #define LINE_CR_FEN (1<<4)
  53. #define LINE_CR_5BIT (0<<5)
  54. #define LINE_CR_6BIT (1<<5)
  55. #define LINE_CR_7BIT (2<<5)
  56. #define LINE_CR_8BIT (3<<5)
  57. #define LINE_CR_BITS_MASK (3<<5)
  58. #define CR_UART_EN (1<<0)
  59. #define CR_SIREN (1<<1)
  60. #define CR_SIRLP (1<<2)
  61. #define CR_MSIE (1<<3)
  62. #define CR_RIE (1<<4)
  63. #define CR_TIE (1<<5)
  64. #define CR_RTIE (1<<6)
  65. #define CR_LBE (1<<7)
  66. #define FR_CTS (1<<0)
  67. #define FR_DSR (1<<1)
  68. #define FR_DCD (1<<2)
  69. #define FR_BUSY (1<<3)
  70. #define FR_RXFE (1<<4)
  71. #define FR_TXFF (1<<5)
  72. #define FR_RXFF (1<<6)
  73. #define FR_TXFE (1<<7)
  74. #define IIR_MIS (1<<0)
  75. #define IIR_RIS (1<<1)
  76. #define IIR_TIS (1<<2)
  77. #define IIR_RTIS (1<<3)
  78. #define IIR_MASK 0xf
  79. #define RTS_CR_AUTO (1<<0)
  80. #define RTS_CR_RTS (1<<1)
  81. #define RTS_CR_COUNT (1<<2)
  82. #define RTS_CR_MOD2 (1<<3)
  83. #define RTS_CR_RTS_POL (1<<4)
  84. #define RTS_CR_CTS_CTR (1<<5)
  85. #define RTS_CR_CTS_POL (1<<6)
  86. #define RTS_CR_STICK (1<<7)
  87. #define UART_PORT_SIZE 0x40
  88. #define DRIVER_NAME "netx-uart"
  89. struct netx_port {
  90. struct uart_port port;
  91. };
  92. static void netx_stop_tx(struct uart_port *port)
  93. {
  94. unsigned int val;
  95. val = readl(port->membase + UART_CR);
  96. writel(val & ~CR_TIE, port->membase + UART_CR);
  97. }
  98. static void netx_stop_rx(struct uart_port *port)
  99. {
  100. unsigned int val;
  101. val = readl(port->membase + UART_CR);
  102. writel(val & ~CR_RIE, port->membase + UART_CR);
  103. }
  104. static void netx_enable_ms(struct uart_port *port)
  105. {
  106. unsigned int val;
  107. val = readl(port->membase + UART_CR);
  108. writel(val | CR_MSIE, port->membase + UART_CR);
  109. }
  110. static inline void netx_transmit_buffer(struct uart_port *port)
  111. {
  112. struct circ_buf *xmit = &port->state->xmit;
  113. if (port->x_char) {
  114. writel(port->x_char, port->membase + UART_DR);
  115. port->icount.tx++;
  116. port->x_char = 0;
  117. return;
  118. }
  119. if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
  120. netx_stop_tx(port);
  121. return;
  122. }
  123. do {
  124. /* send xmit->buf[xmit->tail]
  125. * out the port here */
  126. writel(xmit->buf[xmit->tail], port->membase + UART_DR);
  127. xmit->tail = (xmit->tail + 1) &
  128. (UART_XMIT_SIZE - 1);
  129. port->icount.tx++;
  130. if (uart_circ_empty(xmit))
  131. break;
  132. } while (!(readl(port->membase + UART_FR) & FR_TXFF));
  133. if (uart_circ_empty(xmit))
  134. netx_stop_tx(port);
  135. }
  136. static void netx_start_tx(struct uart_port *port)
  137. {
  138. writel(
  139. readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
  140. if (!(readl(port->membase + UART_FR) & FR_TXFF))
  141. netx_transmit_buffer(port);
  142. }
  143. static unsigned int netx_tx_empty(struct uart_port *port)
  144. {
  145. return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
  146. }
  147. static void netx_txint(struct uart_port *port)
  148. {
  149. struct circ_buf *xmit = &port->state->xmit;
  150. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  151. netx_stop_tx(port);
  152. return;
  153. }
  154. netx_transmit_buffer(port);
  155. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  156. uart_write_wakeup(port);
  157. }
  158. static void netx_rxint(struct uart_port *port, unsigned long *flags)
  159. {
  160. unsigned char rx, flg, status;
  161. while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
  162. rx = readl(port->membase + UART_DR);
  163. flg = TTY_NORMAL;
  164. port->icount.rx++;
  165. status = readl(port->membase + UART_SR);
  166. if (status & SR_BE) {
  167. writel(0, port->membase + UART_SR);
  168. if (uart_handle_break(port))
  169. continue;
  170. }
  171. if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
  172. if (status & SR_PE)
  173. port->icount.parity++;
  174. else if (status & SR_FE)
  175. port->icount.frame++;
  176. if (status & SR_OE)
  177. port->icount.overrun++;
  178. status &= port->read_status_mask;
  179. if (status & SR_BE)
  180. flg = TTY_BREAK;
  181. else if (status & SR_PE)
  182. flg = TTY_PARITY;
  183. else if (status & SR_FE)
  184. flg = TTY_FRAME;
  185. }
  186. if (uart_handle_sysrq_char(port, rx))
  187. continue;
  188. uart_insert_char(port, status, SR_OE, rx, flg);
  189. }
  190. spin_unlock_irqrestore(&port->lock, *flags);
  191. tty_flip_buffer_push(&port->state->port);
  192. spin_lock_irqsave(&port->lock, *flags);
  193. }
  194. static irqreturn_t netx_int(int irq, void *dev_id)
  195. {
  196. struct uart_port *port = dev_id;
  197. unsigned long flags;
  198. unsigned char status;
  199. spin_lock_irqsave(&port->lock,flags);
  200. status = readl(port->membase + UART_IIR) & IIR_MASK;
  201. while (status) {
  202. if (status & IIR_RIS)
  203. netx_rxint(port, &flags);
  204. if (status & IIR_TIS)
  205. netx_txint(port);
  206. if (status & IIR_MIS) {
  207. if (readl(port->membase + UART_FR) & FR_CTS)
  208. uart_handle_cts_change(port, 1);
  209. else
  210. uart_handle_cts_change(port, 0);
  211. }
  212. writel(0, port->membase + UART_IIR);
  213. status = readl(port->membase + UART_IIR) & IIR_MASK;
  214. }
  215. spin_unlock_irqrestore(&port->lock,flags);
  216. return IRQ_HANDLED;
  217. }
  218. static unsigned int netx_get_mctrl(struct uart_port *port)
  219. {
  220. unsigned int ret = TIOCM_DSR | TIOCM_CAR;
  221. if (readl(port->membase + UART_FR) & FR_CTS)
  222. ret |= TIOCM_CTS;
  223. return ret;
  224. }
  225. static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
  226. {
  227. unsigned int val;
  228. /* FIXME: Locking needed ? */
  229. if (mctrl & TIOCM_RTS) {
  230. val = readl(port->membase + UART_RTS_CR);
  231. writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
  232. }
  233. }
  234. static void netx_break_ctl(struct uart_port *port, int break_state)
  235. {
  236. unsigned int line_cr;
  237. spin_lock_irq(&port->lock);
  238. line_cr = readl(port->membase + UART_LINE_CR);
  239. if (break_state != 0)
  240. line_cr |= LINE_CR_BRK;
  241. else
  242. line_cr &= ~LINE_CR_BRK;
  243. writel(line_cr, port->membase + UART_LINE_CR);
  244. spin_unlock_irq(&port->lock);
  245. }
  246. static int netx_startup(struct uart_port *port)
  247. {
  248. int ret;
  249. ret = request_irq(port->irq, netx_int, 0,
  250. DRIVER_NAME, port);
  251. if (ret) {
  252. dev_err(port->dev, "unable to grab irq%d\n",port->irq);
  253. goto exit;
  254. }
  255. writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
  256. port->membase + UART_LINE_CR);
  257. writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
  258. port->membase + UART_CR);
  259. exit:
  260. return ret;
  261. }
  262. static void netx_shutdown(struct uart_port *port)
  263. {
  264. writel(0, port->membase + UART_CR) ;
  265. free_irq(port->irq, port);
  266. }
  267. static void
  268. netx_set_termios(struct uart_port *port, struct ktermios *termios,
  269. struct ktermios *old)
  270. {
  271. unsigned int baud, quot;
  272. unsigned char old_cr;
  273. unsigned char line_cr = LINE_CR_FEN;
  274. unsigned char rts_cr = 0;
  275. switch (termios->c_cflag & CSIZE) {
  276. case CS5:
  277. line_cr |= LINE_CR_5BIT;
  278. break;
  279. case CS6:
  280. line_cr |= LINE_CR_6BIT;
  281. break;
  282. case CS7:
  283. line_cr |= LINE_CR_7BIT;
  284. break;
  285. case CS8:
  286. line_cr |= LINE_CR_8BIT;
  287. break;
  288. }
  289. if (termios->c_cflag & CSTOPB)
  290. line_cr |= LINE_CR_STP2;
  291. if (termios->c_cflag & PARENB) {
  292. line_cr |= LINE_CR_PEN;
  293. if (!(termios->c_cflag & PARODD))
  294. line_cr |= LINE_CR_EPS;
  295. }
  296. if (termios->c_cflag & CRTSCTS)
  297. rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
  298. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  299. quot = baud * 4096;
  300. quot /= 1000;
  301. quot *= 256;
  302. quot /= 100000;
  303. spin_lock_irq(&port->lock);
  304. uart_update_timeout(port, termios->c_cflag, baud);
  305. old_cr = readl(port->membase + UART_CR);
  306. /* disable interrupts */
  307. writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
  308. port->membase + UART_CR);
  309. /* drain transmitter */
  310. while (readl(port->membase + UART_FR) & FR_BUSY);
  311. /* disable UART */
  312. writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
  313. /* modem status interrupts */
  314. old_cr &= ~CR_MSIE;
  315. if (UART_ENABLE_MS(port, termios->c_cflag))
  316. old_cr |= CR_MSIE;
  317. writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
  318. writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
  319. writel(line_cr, port->membase + UART_LINE_CR);
  320. writel(rts_cr, port->membase + UART_RTS_CR);
  321. /*
  322. * Characters to ignore
  323. */
  324. port->ignore_status_mask = 0;
  325. if (termios->c_iflag & IGNPAR)
  326. port->ignore_status_mask |= SR_PE;
  327. if (termios->c_iflag & IGNBRK) {
  328. port->ignore_status_mask |= SR_BE;
  329. /*
  330. * If we're ignoring parity and break indicators,
  331. * ignore overruns too (for real raw support).
  332. */
  333. if (termios->c_iflag & IGNPAR)
  334. port->ignore_status_mask |= SR_PE;
  335. }
  336. port->read_status_mask = 0;
  337. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  338. port->read_status_mask |= SR_BE;
  339. if (termios->c_iflag & INPCK)
  340. port->read_status_mask |= SR_PE | SR_FE;
  341. writel(old_cr, port->membase + UART_CR);
  342. spin_unlock_irq(&port->lock);
  343. }
  344. static const char *netx_type(struct uart_port *port)
  345. {
  346. return port->type == PORT_NETX ? "NETX" : NULL;
  347. }
  348. static void netx_release_port(struct uart_port *port)
  349. {
  350. release_mem_region(port->mapbase, UART_PORT_SIZE);
  351. }
  352. static int netx_request_port(struct uart_port *port)
  353. {
  354. return request_mem_region(port->mapbase, UART_PORT_SIZE,
  355. DRIVER_NAME) != NULL ? 0 : -EBUSY;
  356. }
  357. static void netx_config_port(struct uart_port *port, int flags)
  358. {
  359. if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
  360. port->type = PORT_NETX;
  361. }
  362. static int
  363. netx_verify_port(struct uart_port *port, struct serial_struct *ser)
  364. {
  365. int ret = 0;
  366. if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
  367. ret = -EINVAL;
  368. return ret;
  369. }
  370. static struct uart_ops netx_pops = {
  371. .tx_empty = netx_tx_empty,
  372. .set_mctrl = netx_set_mctrl,
  373. .get_mctrl = netx_get_mctrl,
  374. .stop_tx = netx_stop_tx,
  375. .start_tx = netx_start_tx,
  376. .stop_rx = netx_stop_rx,
  377. .enable_ms = netx_enable_ms,
  378. .break_ctl = netx_break_ctl,
  379. .startup = netx_startup,
  380. .shutdown = netx_shutdown,
  381. .set_termios = netx_set_termios,
  382. .type = netx_type,
  383. .release_port = netx_release_port,
  384. .request_port = netx_request_port,
  385. .config_port = netx_config_port,
  386. .verify_port = netx_verify_port,
  387. };
  388. static struct netx_port netx_ports[] = {
  389. {
  390. .port = {
  391. .type = PORT_NETX,
  392. .iotype = UPIO_MEM,
  393. .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
  394. .mapbase = NETX_PA_UART0,
  395. .irq = NETX_IRQ_UART0,
  396. .uartclk = 100000000,
  397. .fifosize = 16,
  398. .flags = UPF_BOOT_AUTOCONF,
  399. .ops = &netx_pops,
  400. .line = 0,
  401. },
  402. }, {
  403. .port = {
  404. .type = PORT_NETX,
  405. .iotype = UPIO_MEM,
  406. .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
  407. .mapbase = NETX_PA_UART1,
  408. .irq = NETX_IRQ_UART1,
  409. .uartclk = 100000000,
  410. .fifosize = 16,
  411. .flags = UPF_BOOT_AUTOCONF,
  412. .ops = &netx_pops,
  413. .line = 1,
  414. },
  415. }, {
  416. .port = {
  417. .type = PORT_NETX,
  418. .iotype = UPIO_MEM,
  419. .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
  420. .mapbase = NETX_PA_UART2,
  421. .irq = NETX_IRQ_UART2,
  422. .uartclk = 100000000,
  423. .fifosize = 16,
  424. .flags = UPF_BOOT_AUTOCONF,
  425. .ops = &netx_pops,
  426. .line = 2,
  427. },
  428. }
  429. };
  430. #ifdef CONFIG_SERIAL_NETX_CONSOLE
  431. static void netx_console_putchar(struct uart_port *port, int ch)
  432. {
  433. while (readl(port->membase + UART_FR) & FR_BUSY);
  434. writel(ch, port->membase + UART_DR);
  435. }
  436. static void
  437. netx_console_write(struct console *co, const char *s, unsigned int count)
  438. {
  439. struct uart_port *port = &netx_ports[co->index].port;
  440. unsigned char cr_save;
  441. cr_save = readl(port->membase + UART_CR);
  442. writel(cr_save | CR_UART_EN, port->membase + UART_CR);
  443. uart_console_write(port, s, count, netx_console_putchar);
  444. while (readl(port->membase + UART_FR) & FR_BUSY);
  445. writel(cr_save, port->membase + UART_CR);
  446. }
  447. static void __init
  448. netx_console_get_options(struct uart_port *port, int *baud,
  449. int *parity, int *bits, int *flow)
  450. {
  451. unsigned char line_cr;
  452. *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
  453. readl(port->membase + UART_BAUDDIV_LSB);
  454. *baud *= 1000;
  455. *baud /= 4096;
  456. *baud *= 1000;
  457. *baud /= 256;
  458. *baud *= 100;
  459. line_cr = readl(port->membase + UART_LINE_CR);
  460. *parity = 'n';
  461. if (line_cr & LINE_CR_PEN) {
  462. if (line_cr & LINE_CR_EPS)
  463. *parity = 'e';
  464. else
  465. *parity = 'o';
  466. }
  467. switch (line_cr & LINE_CR_BITS_MASK) {
  468. case LINE_CR_8BIT:
  469. *bits = 8;
  470. break;
  471. case LINE_CR_7BIT:
  472. *bits = 7;
  473. break;
  474. case LINE_CR_6BIT:
  475. *bits = 6;
  476. break;
  477. case LINE_CR_5BIT:
  478. *bits = 5;
  479. break;
  480. }
  481. if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
  482. *flow = 'r';
  483. }
  484. static int __init
  485. netx_console_setup(struct console *co, char *options)
  486. {
  487. struct netx_port *sport;
  488. int baud = 9600;
  489. int bits = 8;
  490. int parity = 'n';
  491. int flow = 'n';
  492. /*
  493. * Check whether an invalid uart number has been specified, and
  494. * if so, search for the first available port that does have
  495. * console support.
  496. */
  497. if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
  498. co->index = 0;
  499. sport = &netx_ports[co->index];
  500. if (options) {
  501. uart_parse_options(options, &baud, &parity, &bits, &flow);
  502. } else {
  503. /* if the UART is enabled, assume it has been correctly setup
  504. * by the bootloader and get the options
  505. */
  506. if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
  507. netx_console_get_options(&sport->port, &baud,
  508. &parity, &bits, &flow);
  509. }
  510. }
  511. return uart_set_options(&sport->port, co, baud, parity, bits, flow);
  512. }
  513. static struct uart_driver netx_reg;
  514. static struct console netx_console = {
  515. .name = "ttyNX",
  516. .write = netx_console_write,
  517. .device = uart_console_device,
  518. .setup = netx_console_setup,
  519. .flags = CON_PRINTBUFFER,
  520. .index = -1,
  521. .data = &netx_reg,
  522. };
  523. static int __init netx_console_init(void)
  524. {
  525. register_console(&netx_console);
  526. return 0;
  527. }
  528. console_initcall(netx_console_init);
  529. #define NETX_CONSOLE &netx_console
  530. #else
  531. #define NETX_CONSOLE NULL
  532. #endif
  533. static struct uart_driver netx_reg = {
  534. .owner = THIS_MODULE,
  535. .driver_name = DRIVER_NAME,
  536. .dev_name = "ttyNX",
  537. .major = SERIAL_NX_MAJOR,
  538. .minor = MINOR_START,
  539. .nr = ARRAY_SIZE(netx_ports),
  540. .cons = NETX_CONSOLE,
  541. };
  542. static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
  543. {
  544. struct netx_port *sport = platform_get_drvdata(pdev);
  545. if (sport)
  546. uart_suspend_port(&netx_reg, &sport->port);
  547. return 0;
  548. }
  549. static int serial_netx_resume(struct platform_device *pdev)
  550. {
  551. struct netx_port *sport = platform_get_drvdata(pdev);
  552. if (sport)
  553. uart_resume_port(&netx_reg, &sport->port);
  554. return 0;
  555. }
  556. static int serial_netx_probe(struct platform_device *pdev)
  557. {
  558. struct uart_port *port = &netx_ports[pdev->id].port;
  559. dev_info(&pdev->dev, "initialising\n");
  560. port->dev = &pdev->dev;
  561. writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
  562. uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
  563. platform_set_drvdata(pdev, &netx_ports[pdev->id]);
  564. return 0;
  565. }
  566. static int serial_netx_remove(struct platform_device *pdev)
  567. {
  568. struct netx_port *sport = platform_get_drvdata(pdev);
  569. if (sport)
  570. uart_remove_one_port(&netx_reg, &sport->port);
  571. return 0;
  572. }
  573. static struct platform_driver serial_netx_driver = {
  574. .probe = serial_netx_probe,
  575. .remove = serial_netx_remove,
  576. .suspend = serial_netx_suspend,
  577. .resume = serial_netx_resume,
  578. .driver = {
  579. .name = DRIVER_NAME,
  580. },
  581. };
  582. static int __init netx_serial_init(void)
  583. {
  584. int ret;
  585. printk(KERN_INFO "Serial: NetX driver\n");
  586. ret = uart_register_driver(&netx_reg);
  587. if (ret)
  588. return ret;
  589. ret = platform_driver_register(&serial_netx_driver);
  590. if (ret != 0)
  591. uart_unregister_driver(&netx_reg);
  592. return 0;
  593. }
  594. static void __exit netx_serial_exit(void)
  595. {
  596. platform_driver_unregister(&serial_netx_driver);
  597. uart_unregister_driver(&netx_reg);
  598. }
  599. module_init(netx_serial_init);
  600. module_exit(netx_serial_exit);
  601. MODULE_AUTHOR("Sascha Hauer");
  602. MODULE_DESCRIPTION("NetX serial port driver");
  603. MODULE_LICENSE("GPL");
  604. MODULE_ALIAS("platform:" DRIVER_NAME);