qcom_geni_serial.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
  3. #include <linux/clk.h>
  4. #include <linux/console.h>
  5. #include <linux/io.h>
  6. #include <linux/iopoll.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/qcom-geni-se.h>
  12. #include <linux/serial.h>
  13. #include <linux/serial_core.h>
  14. #include <linux/slab.h>
  15. #include <linux/tty.h>
  16. #include <linux/tty_flip.h>
  17. /* UART specific GENI registers */
  18. #define SE_UART_LOOPBACK_CFG 0x22c
  19. #define SE_UART_TX_TRANS_CFG 0x25c
  20. #define SE_UART_TX_WORD_LEN 0x268
  21. #define SE_UART_TX_STOP_BIT_LEN 0x26c
  22. #define SE_UART_TX_TRANS_LEN 0x270
  23. #define SE_UART_RX_TRANS_CFG 0x280
  24. #define SE_UART_RX_WORD_LEN 0x28c
  25. #define SE_UART_RX_STALE_CNT 0x294
  26. #define SE_UART_TX_PARITY_CFG 0x2a4
  27. #define SE_UART_RX_PARITY_CFG 0x2a8
  28. #define SE_UART_MANUAL_RFR 0x2ac
  29. /* SE_UART_TRANS_CFG */
  30. #define UART_TX_PAR_EN BIT(0)
  31. #define UART_CTS_MASK BIT(1)
  32. /* SE_UART_TX_WORD_LEN */
  33. #define TX_WORD_LEN_MSK GENMASK(9, 0)
  34. /* SE_UART_TX_STOP_BIT_LEN */
  35. #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
  36. #define TX_STOP_BIT_LEN_1 0
  37. #define TX_STOP_BIT_LEN_1_5 1
  38. #define TX_STOP_BIT_LEN_2 2
  39. /* SE_UART_TX_TRANS_LEN */
  40. #define TX_TRANS_LEN_MSK GENMASK(23, 0)
  41. /* SE_UART_RX_TRANS_CFG */
  42. #define UART_RX_INS_STATUS_BIT BIT(2)
  43. #define UART_RX_PAR_EN BIT(3)
  44. /* SE_UART_RX_WORD_LEN */
  45. #define RX_WORD_LEN_MASK GENMASK(9, 0)
  46. /* SE_UART_RX_STALE_CNT */
  47. #define RX_STALE_CNT GENMASK(23, 0)
  48. /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  49. #define PAR_CALC_EN BIT(0)
  50. #define PAR_MODE_MSK GENMASK(2, 1)
  51. #define PAR_MODE_SHFT 1
  52. #define PAR_EVEN 0x00
  53. #define PAR_ODD 0x01
  54. #define PAR_SPACE 0x10
  55. #define PAR_MARK 0x11
  56. /* SE_UART_MANUAL_RFR register fields */
  57. #define UART_MANUAL_RFR_EN BIT(31)
  58. #define UART_RFR_NOT_READY BIT(1)
  59. #define UART_RFR_READY BIT(0)
  60. /* UART M_CMD OP codes */
  61. #define UART_START_TX 0x1
  62. #define UART_START_BREAK 0x4
  63. #define UART_STOP_BREAK 0x5
  64. /* UART S_CMD OP codes */
  65. #define UART_START_READ 0x1
  66. #define UART_PARAM 0x1
  67. #define UART_OVERSAMPLING 32
  68. #define STALE_TIMEOUT 16
  69. #define DEFAULT_BITS_PER_CHAR 10
  70. #define GENI_UART_CONS_PORTS 1
  71. #define GENI_UART_PORTS 3
  72. #define DEF_FIFO_DEPTH_WORDS 16
  73. #define DEF_TX_WM 2
  74. #define DEF_FIFO_WIDTH_BITS 32
  75. #define UART_RX_WM 2
  76. #define MAX_LOOPBACK_CFG 3
  77. #ifdef CONFIG_CONSOLE_POLL
  78. #define RX_BYTES_PW 1
  79. #else
  80. #define RX_BYTES_PW 4
  81. #endif
  82. struct qcom_geni_serial_port {
  83. struct uart_port uport;
  84. struct geni_se se;
  85. char name[20];
  86. u32 tx_fifo_depth;
  87. u32 tx_fifo_width;
  88. u32 rx_fifo_depth;
  89. bool setup;
  90. int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
  91. unsigned int baud;
  92. unsigned int tx_bytes_pw;
  93. unsigned int rx_bytes_pw;
  94. u32 *rx_fifo;
  95. u32 loopback;
  96. bool brk;
  97. unsigned int tx_remaining;
  98. };
  99. static const struct uart_ops qcom_geni_console_pops;
  100. static const struct uart_ops qcom_geni_uart_pops;
  101. static struct uart_driver qcom_geni_console_driver;
  102. static struct uart_driver qcom_geni_uart_driver;
  103. static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
  104. static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
  105. static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
  106. static void qcom_geni_serial_stop_rx(struct uart_port *uport);
  107. static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
  108. static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
  109. 32000000, 48000000, 64000000, 80000000,
  110. 96000000, 100000000, 102400000,
  111. 112000000, 120000000, 128000000};
  112. #define to_dev_port(ptr, member) \
  113. container_of(ptr, struct qcom_geni_serial_port, member)
  114. static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
  115. [0] = {
  116. .uport = {
  117. .iotype = UPIO_MEM,
  118. .ops = &qcom_geni_uart_pops,
  119. .flags = UPF_BOOT_AUTOCONF,
  120. .line = 0,
  121. },
  122. },
  123. [1] = {
  124. .uport = {
  125. .iotype = UPIO_MEM,
  126. .ops = &qcom_geni_uart_pops,
  127. .flags = UPF_BOOT_AUTOCONF,
  128. .line = 1,
  129. },
  130. },
  131. [2] = {
  132. .uport = {
  133. .iotype = UPIO_MEM,
  134. .ops = &qcom_geni_uart_pops,
  135. .flags = UPF_BOOT_AUTOCONF,
  136. .line = 2,
  137. },
  138. },
  139. };
  140. static ssize_t loopback_show(struct device *dev,
  141. struct device_attribute *attr, char *buf)
  142. {
  143. struct platform_device *pdev = to_platform_device(dev);
  144. struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
  145. return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
  146. }
  147. static ssize_t loopback_store(struct device *dev,
  148. struct device_attribute *attr, const char *buf,
  149. size_t size)
  150. {
  151. struct platform_device *pdev = to_platform_device(dev);
  152. struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
  153. u32 loopback;
  154. if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
  155. dev_err(dev, "Invalid input\n");
  156. return -EINVAL;
  157. }
  158. port->loopback = loopback;
  159. return size;
  160. }
  161. static DEVICE_ATTR_RW(loopback);
  162. static struct qcom_geni_serial_port qcom_geni_console_port = {
  163. .uport = {
  164. .iotype = UPIO_MEM,
  165. .ops = &qcom_geni_console_pops,
  166. .flags = UPF_BOOT_AUTOCONF,
  167. .line = 0,
  168. },
  169. };
  170. static int qcom_geni_serial_request_port(struct uart_port *uport)
  171. {
  172. struct platform_device *pdev = to_platform_device(uport->dev);
  173. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  174. struct resource *res;
  175. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  176. uport->membase = devm_ioremap_resource(&pdev->dev, res);
  177. if (IS_ERR(uport->membase))
  178. return PTR_ERR(uport->membase);
  179. port->se.base = uport->membase;
  180. return 0;
  181. }
  182. static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
  183. {
  184. if (cfg_flags & UART_CONFIG_TYPE) {
  185. uport->type = PORT_MSM;
  186. qcom_geni_serial_request_port(uport);
  187. }
  188. }
  189. static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
  190. {
  191. unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
  192. u32 geni_ios;
  193. if (uart_console(uport)) {
  194. mctrl |= TIOCM_CTS;
  195. } else {
  196. geni_ios = readl(uport->membase + SE_GENI_IOS);
  197. if (!(geni_ios & IO2_DATA_IN))
  198. mctrl |= TIOCM_CTS;
  199. }
  200. return mctrl;
  201. }
  202. static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
  203. unsigned int mctrl)
  204. {
  205. u32 uart_manual_rfr = 0;
  206. if (uart_console(uport))
  207. return;
  208. if (!(mctrl & TIOCM_RTS))
  209. uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
  210. writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
  211. }
  212. static const char *qcom_geni_serial_get_type(struct uart_port *uport)
  213. {
  214. return "MSM";
  215. }
  216. static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
  217. {
  218. struct qcom_geni_serial_port *port;
  219. int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
  220. if (line < 0 || line >= nr_ports)
  221. return ERR_PTR(-ENXIO);
  222. port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
  223. return port;
  224. }
  225. static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
  226. int offset, int field, bool set)
  227. {
  228. u32 reg;
  229. struct qcom_geni_serial_port *port;
  230. unsigned int baud;
  231. unsigned int fifo_bits;
  232. unsigned long timeout_us = 20000;
  233. if (uport->private_data) {
  234. port = to_dev_port(uport, uport);
  235. baud = port->baud;
  236. if (!baud)
  237. baud = 115200;
  238. fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
  239. /*
  240. * Total polling iterations based on FIFO worth of bytes to be
  241. * sent at current baud. Add a little fluff to the wait.
  242. */
  243. timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
  244. }
  245. /*
  246. * Use custom implementation instead of readl_poll_atomic since ktimer
  247. * is not ready at the time of early console.
  248. */
  249. timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
  250. while (timeout_us) {
  251. reg = readl(uport->membase + offset);
  252. if ((bool)(reg & field) == set)
  253. return true;
  254. udelay(10);
  255. timeout_us -= 10;
  256. }
  257. return false;
  258. }
  259. static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
  260. {
  261. u32 m_cmd;
  262. writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
  263. m_cmd = UART_START_TX << M_OPCODE_SHFT;
  264. writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
  265. }
  266. static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
  267. {
  268. int done;
  269. u32 irq_clear = M_CMD_DONE_EN;
  270. done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  271. M_CMD_DONE_EN, true);
  272. if (!done) {
  273. writel(M_GENI_CMD_ABORT, uport->membase +
  274. SE_GENI_M_CMD_CTRL_REG);
  275. irq_clear |= M_CMD_ABORT_EN;
  276. qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  277. M_CMD_ABORT_EN, true);
  278. }
  279. writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
  280. }
  281. static void qcom_geni_serial_abort_rx(struct uart_port *uport)
  282. {
  283. u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
  284. writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
  285. qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
  286. S_GENI_CMD_ABORT, false);
  287. writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
  288. writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
  289. }
  290. #ifdef CONFIG_CONSOLE_POLL
  291. static int qcom_geni_serial_get_char(struct uart_port *uport)
  292. {
  293. u32 rx_fifo;
  294. u32 status;
  295. status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
  296. writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
  297. status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
  298. writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
  299. status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
  300. if (!(status & RX_FIFO_WC_MSK))
  301. return NO_POLL_CHAR;
  302. rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
  303. return rx_fifo & 0xff;
  304. }
  305. static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
  306. unsigned char c)
  307. {
  308. writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
  309. qcom_geni_serial_setup_tx(uport, 1);
  310. WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  311. M_TX_FIFO_WATERMARK_EN, true));
  312. writel(c, uport->membase + SE_GENI_TX_FIFOn);
  313. writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
  314. qcom_geni_serial_poll_tx_done(uport);
  315. }
  316. #endif
  317. #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
  318. static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
  319. {
  320. writel(ch, uport->membase + SE_GENI_TX_FIFOn);
  321. }
  322. static void
  323. __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
  324. unsigned int count)
  325. {
  326. int i;
  327. u32 bytes_to_send = count;
  328. for (i = 0; i < count; i++) {
  329. /*
  330. * uart_console_write() adds a carriage return for each newline.
  331. * Account for additional bytes to be written.
  332. */
  333. if (s[i] == '\n')
  334. bytes_to_send++;
  335. }
  336. writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
  337. qcom_geni_serial_setup_tx(uport, bytes_to_send);
  338. for (i = 0; i < count; ) {
  339. size_t chars_to_write = 0;
  340. size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
  341. /*
  342. * If the WM bit never set, then the Tx state machine is not
  343. * in a valid state, so break, cancel/abort any existing
  344. * command. Unfortunately the current data being written is
  345. * lost.
  346. */
  347. if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  348. M_TX_FIFO_WATERMARK_EN, true))
  349. break;
  350. chars_to_write = min_t(size_t, count - i, avail / 2);
  351. uart_console_write(uport, s + i, chars_to_write,
  352. qcom_geni_serial_wr_char);
  353. writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
  354. SE_GENI_M_IRQ_CLEAR);
  355. i += chars_to_write;
  356. }
  357. qcom_geni_serial_poll_tx_done(uport);
  358. }
  359. static void qcom_geni_serial_console_write(struct console *co, const char *s,
  360. unsigned int count)
  361. {
  362. struct uart_port *uport;
  363. struct qcom_geni_serial_port *port;
  364. bool locked = true;
  365. unsigned long flags;
  366. u32 geni_status;
  367. u32 irq_en;
  368. WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
  369. port = get_port_from_line(co->index, true);
  370. if (IS_ERR(port))
  371. return;
  372. uport = &port->uport;
  373. if (oops_in_progress)
  374. locked = spin_trylock_irqsave(&uport->lock, flags);
  375. else
  376. spin_lock_irqsave(&uport->lock, flags);
  377. geni_status = readl(uport->membase + SE_GENI_STATUS);
  378. /* Cancel the current write to log the fault */
  379. if (!locked) {
  380. geni_se_cancel_m_cmd(&port->se);
  381. if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  382. M_CMD_CANCEL_EN, true)) {
  383. geni_se_abort_m_cmd(&port->se);
  384. qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  385. M_CMD_ABORT_EN, true);
  386. writel(M_CMD_ABORT_EN, uport->membase +
  387. SE_GENI_M_IRQ_CLEAR);
  388. }
  389. writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
  390. } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
  391. /*
  392. * It seems we can't interrupt existing transfers if all data
  393. * has been sent, in which case we need to look for done first.
  394. */
  395. qcom_geni_serial_poll_tx_done(uport);
  396. if (uart_circ_chars_pending(&uport->state->xmit)) {
  397. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  398. writel(irq_en | M_TX_FIFO_WATERMARK_EN,
  399. uport->membase + SE_GENI_M_IRQ_EN);
  400. }
  401. }
  402. __qcom_geni_serial_console_write(uport, s, count);
  403. if (port->tx_remaining)
  404. qcom_geni_serial_setup_tx(uport, port->tx_remaining);
  405. if (locked)
  406. spin_unlock_irqrestore(&uport->lock, flags);
  407. }
  408. static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
  409. {
  410. u32 i;
  411. unsigned char buf[sizeof(u32)];
  412. struct tty_port *tport;
  413. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  414. tport = &uport->state->port;
  415. for (i = 0; i < bytes; ) {
  416. int c;
  417. int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
  418. ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
  419. i += chunk;
  420. if (drop)
  421. continue;
  422. for (c = 0; c < chunk; c++) {
  423. int sysrq;
  424. uport->icount.rx++;
  425. if (port->brk && buf[c] == 0) {
  426. port->brk = false;
  427. if (uart_handle_break(uport))
  428. continue;
  429. }
  430. sysrq = uart_handle_sysrq_char(uport, buf[c]);
  431. if (!sysrq)
  432. tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
  433. }
  434. }
  435. if (!drop)
  436. tty_flip_buffer_push(tport);
  437. return 0;
  438. }
  439. #else
  440. static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
  441. {
  442. return -EPERM;
  443. }
  444. #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
  445. static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
  446. {
  447. unsigned char *buf;
  448. struct tty_port *tport;
  449. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  450. u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
  451. u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
  452. int ret;
  453. tport = &uport->state->port;
  454. ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
  455. if (drop)
  456. return 0;
  457. buf = (unsigned char *)port->rx_fifo;
  458. ret = tty_insert_flip_string(tport, buf, bytes);
  459. if (ret != bytes) {
  460. dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
  461. __func__, ret, bytes);
  462. WARN_ON_ONCE(1);
  463. }
  464. uport->icount.rx += ret;
  465. tty_flip_buffer_push(tport);
  466. return ret;
  467. }
  468. static void qcom_geni_serial_start_tx(struct uart_port *uport)
  469. {
  470. u32 irq_en;
  471. u32 status;
  472. status = readl(uport->membase + SE_GENI_STATUS);
  473. if (status & M_GENI_CMD_ACTIVE)
  474. return;
  475. if (!qcom_geni_serial_tx_empty(uport))
  476. return;
  477. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  478. irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
  479. writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
  480. writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
  481. }
  482. static void qcom_geni_serial_stop_tx(struct uart_port *uport)
  483. {
  484. u32 irq_en;
  485. u32 status;
  486. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  487. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  488. irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
  489. writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
  490. writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
  491. status = readl(uport->membase + SE_GENI_STATUS);
  492. /* Possible stop tx is called multiple times. */
  493. if (!(status & M_GENI_CMD_ACTIVE))
  494. return;
  495. geni_se_cancel_m_cmd(&port->se);
  496. if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  497. M_CMD_CANCEL_EN, true)) {
  498. geni_se_abort_m_cmd(&port->se);
  499. qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
  500. M_CMD_ABORT_EN, true);
  501. writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
  502. }
  503. writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
  504. }
  505. static void qcom_geni_serial_start_rx(struct uart_port *uport)
  506. {
  507. u32 irq_en;
  508. u32 status;
  509. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  510. status = readl(uport->membase + SE_GENI_STATUS);
  511. if (status & S_GENI_CMD_ACTIVE)
  512. qcom_geni_serial_stop_rx(uport);
  513. geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
  514. irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
  515. irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
  516. writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
  517. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  518. irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
  519. writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
  520. }
  521. static void qcom_geni_serial_stop_rx(struct uart_port *uport)
  522. {
  523. u32 irq_en;
  524. u32 status;
  525. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  526. u32 s_irq_status;
  527. irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
  528. irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
  529. writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
  530. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  531. irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
  532. writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
  533. status = readl(uport->membase + SE_GENI_STATUS);
  534. /* Possible stop rx is called multiple times. */
  535. if (!(status & S_GENI_CMD_ACTIVE))
  536. return;
  537. geni_se_cancel_s_cmd(&port->se);
  538. qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
  539. S_CMD_CANCEL_EN, true);
  540. /*
  541. * If timeout occurs secondary engine remains active
  542. * and Abort sequence is executed.
  543. */
  544. s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
  545. /* Flush the Rx buffer */
  546. if (s_irq_status & S_RX_FIFO_LAST_EN)
  547. qcom_geni_serial_handle_rx(uport, true);
  548. writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
  549. status = readl(uport->membase + SE_GENI_STATUS);
  550. if (status & S_GENI_CMD_ACTIVE)
  551. qcom_geni_serial_abort_rx(uport);
  552. }
  553. static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
  554. {
  555. u32 status;
  556. u32 word_cnt;
  557. u32 last_word_byte_cnt;
  558. u32 last_word_partial;
  559. u32 total_bytes;
  560. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  561. status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
  562. word_cnt = status & RX_FIFO_WC_MSK;
  563. last_word_partial = status & RX_LAST;
  564. last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
  565. RX_LAST_BYTE_VALID_SHFT;
  566. if (!word_cnt)
  567. return;
  568. total_bytes = port->rx_bytes_pw * (word_cnt - 1);
  569. if (last_word_partial && last_word_byte_cnt)
  570. total_bytes += last_word_byte_cnt;
  571. else
  572. total_bytes += port->rx_bytes_pw;
  573. port->handle_rx(uport, total_bytes, drop);
  574. }
  575. static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
  576. bool active)
  577. {
  578. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  579. struct circ_buf *xmit = &uport->state->xmit;
  580. size_t avail;
  581. size_t remaining;
  582. size_t pending;
  583. int i;
  584. u32 status;
  585. u32 irq_en;
  586. unsigned int chunk;
  587. int tail;
  588. status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
  589. /* Complete the current tx command before taking newly added data */
  590. if (active)
  591. pending = port->tx_remaining;
  592. else
  593. pending = uart_circ_chars_pending(xmit);
  594. /* All data has been transmitted and acknowledged as received */
  595. if (!pending && !status && done) {
  596. qcom_geni_serial_stop_tx(uport);
  597. goto out_write_wakeup;
  598. }
  599. avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
  600. avail *= port->tx_bytes_pw;
  601. tail = xmit->tail;
  602. chunk = min(avail, pending);
  603. if (!chunk)
  604. goto out_write_wakeup;
  605. if (!port->tx_remaining) {
  606. qcom_geni_serial_setup_tx(uport, pending);
  607. port->tx_remaining = pending;
  608. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  609. if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
  610. writel(irq_en | M_TX_FIFO_WATERMARK_EN,
  611. uport->membase + SE_GENI_M_IRQ_EN);
  612. }
  613. remaining = chunk;
  614. for (i = 0; i < chunk; ) {
  615. unsigned int tx_bytes;
  616. u8 buf[sizeof(u32)];
  617. int c;
  618. memset(buf, 0, ARRAY_SIZE(buf));
  619. tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
  620. for (c = 0; c < tx_bytes ; c++) {
  621. buf[c] = xmit->buf[tail++];
  622. tail &= UART_XMIT_SIZE - 1;
  623. }
  624. iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
  625. i += tx_bytes;
  626. uport->icount.tx += tx_bytes;
  627. remaining -= tx_bytes;
  628. port->tx_remaining -= tx_bytes;
  629. }
  630. xmit->tail = tail;
  631. /*
  632. * The tx fifo watermark is level triggered and latched. Though we had
  633. * cleared it in qcom_geni_serial_isr it will have already reasserted
  634. * so we must clear it again here after our writes.
  635. */
  636. writel(M_TX_FIFO_WATERMARK_EN,
  637. uport->membase + SE_GENI_M_IRQ_CLEAR);
  638. out_write_wakeup:
  639. if (!port->tx_remaining) {
  640. irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  641. if (irq_en & M_TX_FIFO_WATERMARK_EN)
  642. writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
  643. uport->membase + SE_GENI_M_IRQ_EN);
  644. }
  645. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  646. uart_write_wakeup(uport);
  647. }
  648. static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
  649. {
  650. unsigned int m_irq_status;
  651. unsigned int s_irq_status;
  652. unsigned int geni_status;
  653. struct uart_port *uport = dev;
  654. unsigned long flags;
  655. unsigned int m_irq_en;
  656. bool drop_rx = false;
  657. struct tty_port *tport = &uport->state->port;
  658. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  659. if (uport->suspended)
  660. return IRQ_NONE;
  661. spin_lock_irqsave(&uport->lock, flags);
  662. m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
  663. s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
  664. geni_status = readl(uport->membase + SE_GENI_STATUS);
  665. m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
  666. writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
  667. writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
  668. if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
  669. goto out_unlock;
  670. if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
  671. uport->icount.overrun++;
  672. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  673. }
  674. if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
  675. qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
  676. geni_status & M_GENI_CMD_ACTIVE);
  677. if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
  678. if (s_irq_status & S_GP_IRQ_0_EN)
  679. uport->icount.parity++;
  680. drop_rx = true;
  681. } else if (s_irq_status & S_GP_IRQ_2_EN ||
  682. s_irq_status & S_GP_IRQ_3_EN) {
  683. uport->icount.brk++;
  684. port->brk = true;
  685. }
  686. if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
  687. s_irq_status & S_RX_FIFO_LAST_EN)
  688. qcom_geni_serial_handle_rx(uport, drop_rx);
  689. out_unlock:
  690. spin_unlock_irqrestore(&uport->lock, flags);
  691. return IRQ_HANDLED;
  692. }
  693. static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
  694. {
  695. struct uart_port *uport;
  696. uport = &port->uport;
  697. port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
  698. port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
  699. port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
  700. uport->fifosize =
  701. (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
  702. }
  703. static void qcom_geni_serial_shutdown(struct uart_port *uport)
  704. {
  705. unsigned long flags;
  706. /* Stop the console before stopping the current tx */
  707. if (uart_console(uport))
  708. console_stop(uport->cons);
  709. free_irq(uport->irq, uport);
  710. spin_lock_irqsave(&uport->lock, flags);
  711. qcom_geni_serial_stop_tx(uport);
  712. qcom_geni_serial_stop_rx(uport);
  713. spin_unlock_irqrestore(&uport->lock, flags);
  714. }
  715. static int qcom_geni_serial_port_setup(struct uart_port *uport)
  716. {
  717. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  718. unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
  719. u32 proto;
  720. if (uart_console(uport))
  721. port->tx_bytes_pw = 1;
  722. else
  723. port->tx_bytes_pw = 4;
  724. port->rx_bytes_pw = RX_BYTES_PW;
  725. proto = geni_se_read_proto(&port->se);
  726. if (proto != GENI_SE_UART) {
  727. dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
  728. return -ENXIO;
  729. }
  730. qcom_geni_serial_stop_rx(uport);
  731. get_tx_fifo_size(port);
  732. writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
  733. /*
  734. * Make an unconditional cancel on the main sequencer to reset
  735. * it else we could end up in data loss scenarios.
  736. */
  737. if (uart_console(uport))
  738. qcom_geni_serial_poll_tx_done(uport);
  739. geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
  740. false, true, false);
  741. geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
  742. false, false, true);
  743. geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
  744. geni_se_select_mode(&port->se, GENI_SE_FIFO);
  745. if (!uart_console(uport)) {
  746. port->rx_fifo = devm_kcalloc(uport->dev,
  747. port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
  748. if (!port->rx_fifo)
  749. return -ENOMEM;
  750. }
  751. port->setup = true;
  752. return 0;
  753. }
  754. static int qcom_geni_serial_startup(struct uart_port *uport)
  755. {
  756. int ret;
  757. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  758. scnprintf(port->name, sizeof(port->name),
  759. "qcom_serial_%s%d",
  760. (uart_console(uport) ? "console" : "uart"), uport->line);
  761. if (!port->setup) {
  762. ret = qcom_geni_serial_port_setup(uport);
  763. if (ret)
  764. return ret;
  765. }
  766. ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
  767. port->name, uport);
  768. if (ret)
  769. dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
  770. return ret;
  771. }
  772. static unsigned long get_clk_cfg(unsigned long clk_freq)
  773. {
  774. int i;
  775. for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
  776. if (!(root_freq[i] % clk_freq))
  777. return root_freq[i];
  778. }
  779. return 0;
  780. }
  781. static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
  782. {
  783. unsigned long ser_clk;
  784. unsigned long desired_clk;
  785. desired_clk = baud * UART_OVERSAMPLING;
  786. ser_clk = get_clk_cfg(desired_clk);
  787. if (!ser_clk) {
  788. pr_err("%s: Can't find matching DFS entry for baud %d\n",
  789. __func__, baud);
  790. return ser_clk;
  791. }
  792. *clk_div = ser_clk / desired_clk;
  793. return ser_clk;
  794. }
  795. static void qcom_geni_serial_set_termios(struct uart_port *uport,
  796. struct ktermios *termios, struct ktermios *old)
  797. {
  798. unsigned int baud;
  799. unsigned int bits_per_char;
  800. unsigned int tx_trans_cfg;
  801. unsigned int tx_parity_cfg;
  802. unsigned int rx_trans_cfg;
  803. unsigned int rx_parity_cfg;
  804. unsigned int stop_bit_len;
  805. unsigned int clk_div;
  806. unsigned long ser_clk_cfg;
  807. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  808. unsigned long clk_rate;
  809. qcom_geni_serial_stop_rx(uport);
  810. /* baud rate */
  811. baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
  812. port->baud = baud;
  813. clk_rate = get_clk_div_rate(baud, &clk_div);
  814. if (!clk_rate)
  815. goto out_restart_rx;
  816. uport->uartclk = clk_rate;
  817. clk_set_rate(port->se.clk, clk_rate);
  818. ser_clk_cfg = SER_CLK_EN;
  819. ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
  820. /* parity */
  821. tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
  822. tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
  823. rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
  824. rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
  825. if (termios->c_cflag & PARENB) {
  826. tx_trans_cfg |= UART_TX_PAR_EN;
  827. rx_trans_cfg |= UART_RX_PAR_EN;
  828. tx_parity_cfg |= PAR_CALC_EN;
  829. rx_parity_cfg |= PAR_CALC_EN;
  830. if (termios->c_cflag & PARODD) {
  831. tx_parity_cfg |= PAR_ODD;
  832. rx_parity_cfg |= PAR_ODD;
  833. } else if (termios->c_cflag & CMSPAR) {
  834. tx_parity_cfg |= PAR_SPACE;
  835. rx_parity_cfg |= PAR_SPACE;
  836. } else {
  837. tx_parity_cfg |= PAR_EVEN;
  838. rx_parity_cfg |= PAR_EVEN;
  839. }
  840. } else {
  841. tx_trans_cfg &= ~UART_TX_PAR_EN;
  842. rx_trans_cfg &= ~UART_RX_PAR_EN;
  843. tx_parity_cfg &= ~PAR_CALC_EN;
  844. rx_parity_cfg &= ~PAR_CALC_EN;
  845. }
  846. /* bits per char */
  847. switch (termios->c_cflag & CSIZE) {
  848. case CS5:
  849. bits_per_char = 5;
  850. break;
  851. case CS6:
  852. bits_per_char = 6;
  853. break;
  854. case CS7:
  855. bits_per_char = 7;
  856. break;
  857. case CS8:
  858. default:
  859. bits_per_char = 8;
  860. break;
  861. }
  862. /* stop bits */
  863. if (termios->c_cflag & CSTOPB)
  864. stop_bit_len = TX_STOP_BIT_LEN_2;
  865. else
  866. stop_bit_len = TX_STOP_BIT_LEN_1;
  867. /* flow control, clear the CTS_MASK bit if using flow control. */
  868. if (termios->c_cflag & CRTSCTS)
  869. tx_trans_cfg &= ~UART_CTS_MASK;
  870. else
  871. tx_trans_cfg |= UART_CTS_MASK;
  872. if (baud)
  873. uart_update_timeout(uport, termios->c_cflag, baud);
  874. if (!uart_console(uport))
  875. writel(port->loopback,
  876. uport->membase + SE_UART_LOOPBACK_CFG);
  877. writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
  878. writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
  879. writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
  880. writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
  881. writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
  882. writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
  883. writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
  884. writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
  885. writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
  886. out_restart_rx:
  887. qcom_geni_serial_start_rx(uport);
  888. }
  889. static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
  890. {
  891. return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
  892. }
  893. #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
  894. static int qcom_geni_console_setup(struct console *co, char *options)
  895. {
  896. struct uart_port *uport;
  897. struct qcom_geni_serial_port *port;
  898. int baud = 9600;
  899. int bits = 8;
  900. int parity = 'n';
  901. int flow = 'n';
  902. int ret;
  903. if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
  904. return -ENXIO;
  905. port = get_port_from_line(co->index, true);
  906. if (IS_ERR(port)) {
  907. pr_err("Invalid line %d\n", co->index);
  908. return PTR_ERR(port);
  909. }
  910. uport = &port->uport;
  911. if (unlikely(!uport->membase))
  912. return -ENXIO;
  913. if (!port->setup) {
  914. ret = qcom_geni_serial_port_setup(uport);
  915. if (ret)
  916. return ret;
  917. }
  918. if (options)
  919. uart_parse_options(options, &baud, &parity, &bits, &flow);
  920. return uart_set_options(uport, co, baud, parity, bits, flow);
  921. }
  922. static void qcom_geni_serial_earlycon_write(struct console *con,
  923. const char *s, unsigned int n)
  924. {
  925. struct earlycon_device *dev = con->data;
  926. __qcom_geni_serial_console_write(&dev->port, s, n);
  927. }
  928. static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
  929. const char *opt)
  930. {
  931. struct uart_port *uport = &dev->port;
  932. u32 tx_trans_cfg;
  933. u32 tx_parity_cfg = 0; /* Disable Tx Parity */
  934. u32 rx_trans_cfg = 0;
  935. u32 rx_parity_cfg = 0; /* Disable Rx Parity */
  936. u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
  937. u32 bits_per_char;
  938. struct geni_se se;
  939. if (!uport->membase)
  940. return -EINVAL;
  941. memset(&se, 0, sizeof(se));
  942. se.base = uport->membase;
  943. if (geni_se_read_proto(&se) != GENI_SE_UART)
  944. return -ENXIO;
  945. /*
  946. * Ignore Flow control.
  947. * n = 8.
  948. */
  949. tx_trans_cfg = UART_CTS_MASK;
  950. bits_per_char = BITS_PER_BYTE;
  951. /*
  952. * Make an unconditional cancel on the main sequencer to reset
  953. * it else we could end up in data loss scenarios.
  954. */
  955. qcom_geni_serial_poll_tx_done(uport);
  956. qcom_geni_serial_abort_rx(uport);
  957. geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
  958. geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
  959. geni_se_select_mode(&se, GENI_SE_FIFO);
  960. writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
  961. writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
  962. writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
  963. writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
  964. writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
  965. writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
  966. writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
  967. dev->con->write = qcom_geni_serial_earlycon_write;
  968. dev->con->setup = NULL;
  969. return 0;
  970. }
  971. OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
  972. qcom_geni_serial_earlycon_setup);
  973. static int __init console_register(struct uart_driver *drv)
  974. {
  975. return uart_register_driver(drv);
  976. }
  977. static void console_unregister(struct uart_driver *drv)
  978. {
  979. uart_unregister_driver(drv);
  980. }
  981. static struct console cons_ops = {
  982. .name = "ttyMSM",
  983. .write = qcom_geni_serial_console_write,
  984. .device = uart_console_device,
  985. .setup = qcom_geni_console_setup,
  986. .flags = CON_PRINTBUFFER,
  987. .index = -1,
  988. .data = &qcom_geni_console_driver,
  989. };
  990. static struct uart_driver qcom_geni_console_driver = {
  991. .owner = THIS_MODULE,
  992. .driver_name = "qcom_geni_console",
  993. .dev_name = "ttyMSM",
  994. .nr = GENI_UART_CONS_PORTS,
  995. .cons = &cons_ops,
  996. };
  997. #else
  998. static int console_register(struct uart_driver *drv)
  999. {
  1000. return 0;
  1001. }
  1002. static void console_unregister(struct uart_driver *drv)
  1003. {
  1004. }
  1005. #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
  1006. static struct uart_driver qcom_geni_uart_driver = {
  1007. .owner = THIS_MODULE,
  1008. .driver_name = "qcom_geni_uart",
  1009. .dev_name = "ttyHS",
  1010. .nr = GENI_UART_PORTS,
  1011. };
  1012. static void qcom_geni_serial_pm(struct uart_port *uport,
  1013. unsigned int new_state, unsigned int old_state)
  1014. {
  1015. struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
  1016. /* If we've never been called, treat it as off */
  1017. if (old_state == UART_PM_STATE_UNDEFINED)
  1018. old_state = UART_PM_STATE_OFF;
  1019. if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
  1020. geni_se_resources_on(&port->se);
  1021. else if (new_state == UART_PM_STATE_OFF &&
  1022. old_state == UART_PM_STATE_ON)
  1023. geni_se_resources_off(&port->se);
  1024. }
  1025. static const struct uart_ops qcom_geni_console_pops = {
  1026. .tx_empty = qcom_geni_serial_tx_empty,
  1027. .stop_tx = qcom_geni_serial_stop_tx,
  1028. .start_tx = qcom_geni_serial_start_tx,
  1029. .stop_rx = qcom_geni_serial_stop_rx,
  1030. .set_termios = qcom_geni_serial_set_termios,
  1031. .startup = qcom_geni_serial_startup,
  1032. .request_port = qcom_geni_serial_request_port,
  1033. .config_port = qcom_geni_serial_config_port,
  1034. .shutdown = qcom_geni_serial_shutdown,
  1035. .type = qcom_geni_serial_get_type,
  1036. .set_mctrl = qcom_geni_serial_set_mctrl,
  1037. .get_mctrl = qcom_geni_serial_get_mctrl,
  1038. #ifdef CONFIG_CONSOLE_POLL
  1039. .poll_get_char = qcom_geni_serial_get_char,
  1040. .poll_put_char = qcom_geni_serial_poll_put_char,
  1041. #endif
  1042. .pm = qcom_geni_serial_pm,
  1043. };
  1044. static const struct uart_ops qcom_geni_uart_pops = {
  1045. .tx_empty = qcom_geni_serial_tx_empty,
  1046. .stop_tx = qcom_geni_serial_stop_tx,
  1047. .start_tx = qcom_geni_serial_start_tx,
  1048. .stop_rx = qcom_geni_serial_stop_rx,
  1049. .set_termios = qcom_geni_serial_set_termios,
  1050. .startup = qcom_geni_serial_startup,
  1051. .request_port = qcom_geni_serial_request_port,
  1052. .config_port = qcom_geni_serial_config_port,
  1053. .shutdown = qcom_geni_serial_shutdown,
  1054. .type = qcom_geni_serial_get_type,
  1055. .set_mctrl = qcom_geni_serial_set_mctrl,
  1056. .get_mctrl = qcom_geni_serial_get_mctrl,
  1057. .pm = qcom_geni_serial_pm,
  1058. };
  1059. static int qcom_geni_serial_probe(struct platform_device *pdev)
  1060. {
  1061. int ret = 0;
  1062. int line = -1;
  1063. struct qcom_geni_serial_port *port;
  1064. struct uart_port *uport;
  1065. struct resource *res;
  1066. int irq;
  1067. bool console = false;
  1068. struct uart_driver *drv;
  1069. if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
  1070. console = true;
  1071. if (pdev->dev.of_node) {
  1072. if (console) {
  1073. drv = &qcom_geni_console_driver;
  1074. line = of_alias_get_id(pdev->dev.of_node, "serial");
  1075. } else {
  1076. drv = &qcom_geni_uart_driver;
  1077. line = of_alias_get_id(pdev->dev.of_node, "hsuart");
  1078. }
  1079. }
  1080. port = get_port_from_line(line, console);
  1081. if (IS_ERR(port)) {
  1082. dev_err(&pdev->dev, "Invalid line %d\n", line);
  1083. return PTR_ERR(port);
  1084. }
  1085. uport = &port->uport;
  1086. /* Don't allow 2 drivers to access the same port */
  1087. if (uport->private_data)
  1088. return -ENODEV;
  1089. uport->dev = &pdev->dev;
  1090. port->se.dev = &pdev->dev;
  1091. port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
  1092. port->se.clk = devm_clk_get(&pdev->dev, "se");
  1093. if (IS_ERR(port->se.clk)) {
  1094. ret = PTR_ERR(port->se.clk);
  1095. dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
  1096. return ret;
  1097. }
  1098. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1099. if (!res)
  1100. return -EINVAL;
  1101. uport->mapbase = res->start;
  1102. port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
  1103. port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
  1104. port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
  1105. irq = platform_get_irq(pdev, 0);
  1106. if (irq < 0) {
  1107. dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
  1108. return irq;
  1109. }
  1110. uport->irq = irq;
  1111. uport->private_data = drv;
  1112. platform_set_drvdata(pdev, port);
  1113. port->handle_rx = console ? handle_rx_console : handle_rx_uart;
  1114. if (!console)
  1115. device_create_file(uport->dev, &dev_attr_loopback);
  1116. return uart_add_one_port(drv, uport);
  1117. }
  1118. static int qcom_geni_serial_remove(struct platform_device *pdev)
  1119. {
  1120. struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
  1121. struct uart_driver *drv = port->uport.private_data;
  1122. uart_remove_one_port(drv, &port->uport);
  1123. return 0;
  1124. }
  1125. static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
  1126. {
  1127. struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
  1128. struct uart_port *uport = &port->uport;
  1129. if (uart_console(uport)) {
  1130. uart_suspend_port(uport->private_data, uport);
  1131. } else {
  1132. struct uart_state *state = uport->state;
  1133. /*
  1134. * If the port is open, deny system suspend.
  1135. */
  1136. if (state->pm_state == UART_PM_STATE_ON)
  1137. return -EBUSY;
  1138. }
  1139. return 0;
  1140. }
  1141. static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
  1142. {
  1143. struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
  1144. struct uart_port *uport = &port->uport;
  1145. if (uart_console(uport) &&
  1146. console_suspend_enabled && uport->suspended) {
  1147. uart_resume_port(uport->private_data, uport);
  1148. /*
  1149. * uart_suspend_port() invokes port shutdown which in turn
  1150. * frees the irq. uart_resume_port invokes port startup which
  1151. * performs request_irq. The request_irq auto-enables the IRQ.
  1152. * In addition, resume_noirq implicitly enables the IRQ and
  1153. * leads to an unbalanced IRQ enable warning. Disable the IRQ
  1154. * before returning so that the warning is suppressed.
  1155. */
  1156. disable_irq(uport->irq);
  1157. }
  1158. return 0;
  1159. }
  1160. static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
  1161. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
  1162. qcom_geni_serial_sys_resume_noirq)
  1163. };
  1164. static const struct of_device_id qcom_geni_serial_match_table[] = {
  1165. { .compatible = "qcom,geni-debug-uart", },
  1166. { .compatible = "qcom,geni-uart", },
  1167. {}
  1168. };
  1169. MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
  1170. static struct platform_driver qcom_geni_serial_platform_driver = {
  1171. .remove = qcom_geni_serial_remove,
  1172. .probe = qcom_geni_serial_probe,
  1173. .driver = {
  1174. .name = "qcom_geni_serial",
  1175. .of_match_table = qcom_geni_serial_match_table,
  1176. .pm = &qcom_geni_serial_pm_ops,
  1177. },
  1178. };
  1179. static int __init qcom_geni_serial_init(void)
  1180. {
  1181. int ret;
  1182. ret = console_register(&qcom_geni_console_driver);
  1183. if (ret)
  1184. return ret;
  1185. ret = uart_register_driver(&qcom_geni_uart_driver);
  1186. if (ret) {
  1187. console_unregister(&qcom_geni_console_driver);
  1188. return ret;
  1189. }
  1190. ret = platform_driver_register(&qcom_geni_serial_platform_driver);
  1191. if (ret) {
  1192. console_unregister(&qcom_geni_console_driver);
  1193. uart_unregister_driver(&qcom_geni_uart_driver);
  1194. }
  1195. return ret;
  1196. }
  1197. module_init(qcom_geni_serial_init);
  1198. static void __exit qcom_geni_serial_exit(void)
  1199. {
  1200. platform_driver_unregister(&qcom_geni_serial_platform_driver);
  1201. console_unregister(&qcom_geni_console_driver);
  1202. uart_unregister_driver(&qcom_geni_uart_driver);
  1203. }
  1204. module_exit(qcom_geni_serial_exit);
  1205. MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
  1206. MODULE_LICENSE("GPL v2");