sunzilog.c 41 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* sunzilog.c: Zilog serial driver for Sparc systems.
  3. *
  4. * Driver for Zilog serial chips found on Sun workstations and
  5. * servers. This driver could actually be made more generic.
  6. *
  7. * This is based on the old drivers/sbus/char/zs.c code. A lot
  8. * of code has been simply moved over directly from there but
  9. * much has been rewritten. Credits therefore go out to Eddie
  10. * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  11. * work there.
  12. *
  13. * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
  14. */
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/errno.h>
  18. #include <linux/delay.h>
  19. #include <linux/tty.h>
  20. #include <linux/tty_flip.h>
  21. #include <linux/major.h>
  22. #include <linux/string.h>
  23. #include <linux/ptrace.h>
  24. #include <linux/ioport.h>
  25. #include <linux/slab.h>
  26. #include <linux/circ_buf.h>
  27. #include <linux/serial.h>
  28. #include <linux/sysrq.h>
  29. #include <linux/console.h>
  30. #include <linux/spinlock.h>
  31. #ifdef CONFIG_SERIO
  32. #include <linux/serio.h>
  33. #endif
  34. #include <linux/init.h>
  35. #include <linux/of_device.h>
  36. #include <asm/io.h>
  37. #include <asm/irq.h>
  38. #include <asm/prom.h>
  39. #include <asm/setup.h>
  40. #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  41. #define SUPPORT_SYSRQ
  42. #endif
  43. #include <linux/serial_core.h>
  44. #include <linux/sunserialcore.h>
  45. #include "sunzilog.h"
  46. /* On 32-bit sparcs we need to delay after register accesses
  47. * to accommodate sun4 systems, but we do not need to flush writes.
  48. * On 64-bit sparc we only need to flush single writes to ensure
  49. * completion.
  50. */
  51. #ifndef CONFIG_SPARC64
  52. #define ZSDELAY() udelay(5)
  53. #define ZSDELAY_LONG() udelay(20)
  54. #define ZS_WSYNC(channel) do { } while (0)
  55. #else
  56. #define ZSDELAY()
  57. #define ZSDELAY_LONG()
  58. #define ZS_WSYNC(__channel) \
  59. readb(&((__channel)->control))
  60. #endif
  61. #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
  62. #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
  63. /*
  64. * We wrap our port structure around the generic uart_port.
  65. */
  66. struct uart_sunzilog_port {
  67. struct uart_port port;
  68. /* IRQ servicing chain. */
  69. struct uart_sunzilog_port *next;
  70. /* Current values of Zilog write registers. */
  71. unsigned char curregs[NUM_ZSREGS];
  72. unsigned int flags;
  73. #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
  74. #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
  75. #define SUNZILOG_FLAG_IS_CONS 0x00000004
  76. #define SUNZILOG_FLAG_IS_KGDB 0x00000008
  77. #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
  78. #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
  79. #define SUNZILOG_FLAG_REGS_HELD 0x00000040
  80. #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
  81. #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
  82. #define SUNZILOG_FLAG_ESCC 0x00000200
  83. #define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
  84. unsigned int cflag;
  85. unsigned char parity_mask;
  86. unsigned char prev_status;
  87. #ifdef CONFIG_SERIO
  88. struct serio serio;
  89. int serio_open;
  90. #endif
  91. };
  92. static void sunzilog_putchar(struct uart_port *port, int ch);
  93. #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
  94. #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
  95. #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
  96. #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
  97. #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
  98. #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
  99. #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
  100. #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
  101. #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
  102. #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
  103. #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
  104. /* Reading and writing Zilog8530 registers. The delays are to make this
  105. * driver work on the Sun4 which needs a settling delay after each chip
  106. * register access, other machines handle this in hardware via auxiliary
  107. * flip-flops which implement the settle time we do in software.
  108. *
  109. * The port lock must be held and local IRQs must be disabled
  110. * when {read,write}_zsreg is invoked.
  111. */
  112. static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
  113. unsigned char reg)
  114. {
  115. unsigned char retval;
  116. writeb(reg, &channel->control);
  117. ZSDELAY();
  118. retval = readb(&channel->control);
  119. ZSDELAY();
  120. return retval;
  121. }
  122. static void write_zsreg(struct zilog_channel __iomem *channel,
  123. unsigned char reg, unsigned char value)
  124. {
  125. writeb(reg, &channel->control);
  126. ZSDELAY();
  127. writeb(value, &channel->control);
  128. ZSDELAY();
  129. }
  130. static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
  131. {
  132. int i;
  133. for (i = 0; i < 32; i++) {
  134. unsigned char regval;
  135. regval = readb(&channel->control);
  136. ZSDELAY();
  137. if (regval & Rx_CH_AV)
  138. break;
  139. regval = read_zsreg(channel, R1);
  140. readb(&channel->data);
  141. ZSDELAY();
  142. if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
  143. writeb(ERR_RES, &channel->control);
  144. ZSDELAY();
  145. ZS_WSYNC(channel);
  146. }
  147. }
  148. }
  149. /* This function must only be called when the TX is not busy. The UART
  150. * port lock must be held and local interrupts disabled.
  151. */
  152. static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
  153. {
  154. int i;
  155. int escc;
  156. unsigned char r15;
  157. /* Let pending transmits finish. */
  158. for (i = 0; i < 1000; i++) {
  159. unsigned char stat = read_zsreg(channel, R1);
  160. if (stat & ALL_SNT)
  161. break;
  162. udelay(100);
  163. }
  164. writeb(ERR_RES, &channel->control);
  165. ZSDELAY();
  166. ZS_WSYNC(channel);
  167. sunzilog_clear_fifo(channel);
  168. /* Disable all interrupts. */
  169. write_zsreg(channel, R1,
  170. regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
  171. /* Set parity, sync config, stop bits, and clock divisor. */
  172. write_zsreg(channel, R4, regs[R4]);
  173. /* Set misc. TX/RX control bits. */
  174. write_zsreg(channel, R10, regs[R10]);
  175. /* Set TX/RX controls sans the enable bits. */
  176. write_zsreg(channel, R3, regs[R3] & ~RxENAB);
  177. write_zsreg(channel, R5, regs[R5] & ~TxENAB);
  178. /* Synchronous mode config. */
  179. write_zsreg(channel, R6, regs[R6]);
  180. write_zsreg(channel, R7, regs[R7]);
  181. /* Don't mess with the interrupt vector (R2, unused by us) and
  182. * master interrupt control (R9). We make sure this is setup
  183. * properly at probe time then never touch it again.
  184. */
  185. /* Disable baud generator. */
  186. write_zsreg(channel, R14, regs[R14] & ~BRENAB);
  187. /* Clock mode control. */
  188. write_zsreg(channel, R11, regs[R11]);
  189. /* Lower and upper byte of baud rate generator divisor. */
  190. write_zsreg(channel, R12, regs[R12]);
  191. write_zsreg(channel, R13, regs[R13]);
  192. /* Now rewrite R14, with BRENAB (if set). */
  193. write_zsreg(channel, R14, regs[R14]);
  194. /* External status interrupt control. */
  195. write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
  196. /* ESCC Extension Register */
  197. r15 = read_zsreg(channel, R15);
  198. if (r15 & 0x01) {
  199. write_zsreg(channel, R7, regs[R7p]);
  200. /* External status interrupt and FIFO control. */
  201. write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
  202. escc = 1;
  203. } else {
  204. /* Clear FIFO bit case it is an issue */
  205. regs[R15] &= ~FIFOEN;
  206. escc = 0;
  207. }
  208. /* Reset external status interrupts. */
  209. write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
  210. write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
  211. /* Rewrite R3/R5, this time without enables masked. */
  212. write_zsreg(channel, R3, regs[R3]);
  213. write_zsreg(channel, R5, regs[R5]);
  214. /* Rewrite R1, this time without IRQ enabled masked. */
  215. write_zsreg(channel, R1, regs[R1]);
  216. return escc;
  217. }
  218. /* Reprogram the Zilog channel HW registers with the copies found in the
  219. * software state struct. If the transmitter is busy, we defer this update
  220. * until the next TX complete interrupt. Else, we do it right now.
  221. *
  222. * The UART port lock must be held and local interrupts disabled.
  223. */
  224. static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
  225. struct zilog_channel __iomem *channel)
  226. {
  227. if (!ZS_REGS_HELD(up)) {
  228. if (ZS_TX_ACTIVE(up)) {
  229. up->flags |= SUNZILOG_FLAG_REGS_HELD;
  230. } else {
  231. __load_zsregs(channel, up->curregs);
  232. }
  233. }
  234. }
  235. static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
  236. {
  237. unsigned int cur_cflag = up->cflag;
  238. int brg, new_baud;
  239. up->cflag &= ~CBAUD;
  240. up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
  241. brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  242. up->curregs[R12] = (brg & 0xff);
  243. up->curregs[R13] = (brg >> 8) & 0xff;
  244. sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
  245. }
  246. static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
  247. unsigned char ch, int is_break)
  248. {
  249. if (ZS_IS_KEYB(up)) {
  250. /* Stop-A is handled by drivers/char/keyboard.c now. */
  251. #ifdef CONFIG_SERIO
  252. if (up->serio_open)
  253. serio_interrupt(&up->serio, ch, 0);
  254. #endif
  255. } else if (ZS_IS_MOUSE(up)) {
  256. int ret = suncore_mouse_baud_detection(ch, is_break);
  257. switch (ret) {
  258. case 2:
  259. sunzilog_change_mouse_baud(up);
  260. /* fallthru */
  261. case 1:
  262. break;
  263. case 0:
  264. #ifdef CONFIG_SERIO
  265. if (up->serio_open)
  266. serio_interrupt(&up->serio, ch, 0);
  267. #endif
  268. break;
  269. }
  270. }
  271. }
  272. static struct tty_port *
  273. sunzilog_receive_chars(struct uart_sunzilog_port *up,
  274. struct zilog_channel __iomem *channel)
  275. {
  276. struct tty_port *port = NULL;
  277. unsigned char ch, r1, flag;
  278. if (up->port.state != NULL) /* Unopened serial console */
  279. port = &up->port.state->port;
  280. for (;;) {
  281. r1 = read_zsreg(channel, R1);
  282. if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
  283. writeb(ERR_RES, &channel->control);
  284. ZSDELAY();
  285. ZS_WSYNC(channel);
  286. }
  287. ch = readb(&channel->control);
  288. ZSDELAY();
  289. /* This funny hack depends upon BRK_ABRT not interfering
  290. * with the other bits we care about in R1.
  291. */
  292. if (ch & BRK_ABRT)
  293. r1 |= BRK_ABRT;
  294. if (!(ch & Rx_CH_AV))
  295. break;
  296. ch = readb(&channel->data);
  297. ZSDELAY();
  298. ch &= up->parity_mask;
  299. if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
  300. sunzilog_kbdms_receive_chars(up, ch, 0);
  301. continue;
  302. }
  303. /* A real serial line, record the character and status. */
  304. flag = TTY_NORMAL;
  305. up->port.icount.rx++;
  306. if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
  307. if (r1 & BRK_ABRT) {
  308. r1 &= ~(PAR_ERR | CRC_ERR);
  309. up->port.icount.brk++;
  310. if (uart_handle_break(&up->port))
  311. continue;
  312. }
  313. else if (r1 & PAR_ERR)
  314. up->port.icount.parity++;
  315. else if (r1 & CRC_ERR)
  316. up->port.icount.frame++;
  317. if (r1 & Rx_OVR)
  318. up->port.icount.overrun++;
  319. r1 &= up->port.read_status_mask;
  320. if (r1 & BRK_ABRT)
  321. flag = TTY_BREAK;
  322. else if (r1 & PAR_ERR)
  323. flag = TTY_PARITY;
  324. else if (r1 & CRC_ERR)
  325. flag = TTY_FRAME;
  326. }
  327. if (uart_handle_sysrq_char(&up->port, ch) || !port)
  328. continue;
  329. if (up->port.ignore_status_mask == 0xff ||
  330. (r1 & up->port.ignore_status_mask) == 0) {
  331. tty_insert_flip_char(port, ch, flag);
  332. }
  333. if (r1 & Rx_OVR)
  334. tty_insert_flip_char(port, 0, TTY_OVERRUN);
  335. }
  336. return port;
  337. }
  338. static void sunzilog_status_handle(struct uart_sunzilog_port *up,
  339. struct zilog_channel __iomem *channel)
  340. {
  341. unsigned char status;
  342. status = readb(&channel->control);
  343. ZSDELAY();
  344. writeb(RES_EXT_INT, &channel->control);
  345. ZSDELAY();
  346. ZS_WSYNC(channel);
  347. if (status & BRK_ABRT) {
  348. if (ZS_IS_MOUSE(up))
  349. sunzilog_kbdms_receive_chars(up, 0, 1);
  350. if (ZS_IS_CONS(up)) {
  351. /* Wait for BREAK to deassert to avoid potentially
  352. * confusing the PROM.
  353. */
  354. while (1) {
  355. status = readb(&channel->control);
  356. ZSDELAY();
  357. if (!(status & BRK_ABRT))
  358. break;
  359. }
  360. sun_do_break();
  361. return;
  362. }
  363. }
  364. if (ZS_WANTS_MODEM_STATUS(up)) {
  365. if (status & SYNC)
  366. up->port.icount.dsr++;
  367. /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
  368. * But it does not tell us which bit has changed, we have to keep
  369. * track of this ourselves.
  370. */
  371. if ((status ^ up->prev_status) ^ DCD)
  372. uart_handle_dcd_change(&up->port,
  373. (status & DCD));
  374. if ((status ^ up->prev_status) ^ CTS)
  375. uart_handle_cts_change(&up->port,
  376. (status & CTS));
  377. wake_up_interruptible(&up->port.state->port.delta_msr_wait);
  378. }
  379. up->prev_status = status;
  380. }
  381. static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
  382. struct zilog_channel __iomem *channel)
  383. {
  384. struct circ_buf *xmit;
  385. if (ZS_IS_CONS(up)) {
  386. unsigned char status = readb(&channel->control);
  387. ZSDELAY();
  388. /* TX still busy? Just wait for the next TX done interrupt.
  389. *
  390. * It can occur because of how we do serial console writes. It would
  391. * be nice to transmit console writes just like we normally would for
  392. * a TTY line. (ie. buffered and TX interrupt driven). That is not
  393. * easy because console writes cannot sleep. One solution might be
  394. * to poll on enough port->xmit space becoming free. -DaveM
  395. */
  396. if (!(status & Tx_BUF_EMP))
  397. return;
  398. }
  399. up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
  400. if (ZS_REGS_HELD(up)) {
  401. __load_zsregs(channel, up->curregs);
  402. up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
  403. }
  404. if (ZS_TX_STOPPED(up)) {
  405. up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
  406. goto ack_tx_int;
  407. }
  408. if (up->port.x_char) {
  409. up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
  410. writeb(up->port.x_char, &channel->data);
  411. ZSDELAY();
  412. ZS_WSYNC(channel);
  413. up->port.icount.tx++;
  414. up->port.x_char = 0;
  415. return;
  416. }
  417. if (up->port.state == NULL)
  418. goto ack_tx_int;
  419. xmit = &up->port.state->xmit;
  420. if (uart_circ_empty(xmit))
  421. goto ack_tx_int;
  422. if (uart_tx_stopped(&up->port))
  423. goto ack_tx_int;
  424. up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
  425. writeb(xmit->buf[xmit->tail], &channel->data);
  426. ZSDELAY();
  427. ZS_WSYNC(channel);
  428. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  429. up->port.icount.tx++;
  430. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  431. uart_write_wakeup(&up->port);
  432. return;
  433. ack_tx_int:
  434. writeb(RES_Tx_P, &channel->control);
  435. ZSDELAY();
  436. ZS_WSYNC(channel);
  437. }
  438. static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
  439. {
  440. struct uart_sunzilog_port *up = dev_id;
  441. while (up) {
  442. struct zilog_channel __iomem *channel
  443. = ZILOG_CHANNEL_FROM_PORT(&up->port);
  444. struct tty_port *port;
  445. unsigned char r3;
  446. spin_lock(&up->port.lock);
  447. r3 = read_zsreg(channel, R3);
  448. /* Channel A */
  449. port = NULL;
  450. if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
  451. writeb(RES_H_IUS, &channel->control);
  452. ZSDELAY();
  453. ZS_WSYNC(channel);
  454. if (r3 & CHARxIP)
  455. port = sunzilog_receive_chars(up, channel);
  456. if (r3 & CHAEXT)
  457. sunzilog_status_handle(up, channel);
  458. if (r3 & CHATxIP)
  459. sunzilog_transmit_chars(up, channel);
  460. }
  461. spin_unlock(&up->port.lock);
  462. if (port)
  463. tty_flip_buffer_push(port);
  464. /* Channel B */
  465. up = up->next;
  466. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  467. spin_lock(&up->port.lock);
  468. port = NULL;
  469. if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
  470. writeb(RES_H_IUS, &channel->control);
  471. ZSDELAY();
  472. ZS_WSYNC(channel);
  473. if (r3 & CHBRxIP)
  474. port = sunzilog_receive_chars(up, channel);
  475. if (r3 & CHBEXT)
  476. sunzilog_status_handle(up, channel);
  477. if (r3 & CHBTxIP)
  478. sunzilog_transmit_chars(up, channel);
  479. }
  480. spin_unlock(&up->port.lock);
  481. if (port)
  482. tty_flip_buffer_push(port);
  483. up = up->next;
  484. }
  485. return IRQ_HANDLED;
  486. }
  487. /* A convenient way to quickly get R0 status. The caller must _not_ hold the
  488. * port lock, it is acquired here.
  489. */
  490. static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
  491. {
  492. struct zilog_channel __iomem *channel;
  493. unsigned char status;
  494. channel = ZILOG_CHANNEL_FROM_PORT(port);
  495. status = readb(&channel->control);
  496. ZSDELAY();
  497. return status;
  498. }
  499. /* The port lock is not held. */
  500. static unsigned int sunzilog_tx_empty(struct uart_port *port)
  501. {
  502. unsigned long flags;
  503. unsigned char status;
  504. unsigned int ret;
  505. spin_lock_irqsave(&port->lock, flags);
  506. status = sunzilog_read_channel_status(port);
  507. spin_unlock_irqrestore(&port->lock, flags);
  508. if (status & Tx_BUF_EMP)
  509. ret = TIOCSER_TEMT;
  510. else
  511. ret = 0;
  512. return ret;
  513. }
  514. /* The port lock is held and interrupts are disabled. */
  515. static unsigned int sunzilog_get_mctrl(struct uart_port *port)
  516. {
  517. unsigned char status;
  518. unsigned int ret;
  519. status = sunzilog_read_channel_status(port);
  520. ret = 0;
  521. if (status & DCD)
  522. ret |= TIOCM_CAR;
  523. if (status & SYNC)
  524. ret |= TIOCM_DSR;
  525. if (status & CTS)
  526. ret |= TIOCM_CTS;
  527. return ret;
  528. }
  529. /* The port lock is held and interrupts are disabled. */
  530. static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
  531. {
  532. struct uart_sunzilog_port *up =
  533. container_of(port, struct uart_sunzilog_port, port);
  534. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  535. unsigned char set_bits, clear_bits;
  536. set_bits = clear_bits = 0;
  537. if (mctrl & TIOCM_RTS)
  538. set_bits |= RTS;
  539. else
  540. clear_bits |= RTS;
  541. if (mctrl & TIOCM_DTR)
  542. set_bits |= DTR;
  543. else
  544. clear_bits |= DTR;
  545. /* NOTE: Not subject to 'transmitter active' rule. */
  546. up->curregs[R5] |= set_bits;
  547. up->curregs[R5] &= ~clear_bits;
  548. write_zsreg(channel, R5, up->curregs[R5]);
  549. }
  550. /* The port lock is held and interrupts are disabled. */
  551. static void sunzilog_stop_tx(struct uart_port *port)
  552. {
  553. struct uart_sunzilog_port *up =
  554. container_of(port, struct uart_sunzilog_port, port);
  555. up->flags |= SUNZILOG_FLAG_TX_STOPPED;
  556. }
  557. /* The port lock is held and interrupts are disabled. */
  558. static void sunzilog_start_tx(struct uart_port *port)
  559. {
  560. struct uart_sunzilog_port *up =
  561. container_of(port, struct uart_sunzilog_port, port);
  562. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  563. unsigned char status;
  564. up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
  565. up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
  566. status = readb(&channel->control);
  567. ZSDELAY();
  568. /* TX busy? Just wait for the TX done interrupt. */
  569. if (!(status & Tx_BUF_EMP))
  570. return;
  571. /* Send the first character to jump-start the TX done
  572. * IRQ sending engine.
  573. */
  574. if (port->x_char) {
  575. writeb(port->x_char, &channel->data);
  576. ZSDELAY();
  577. ZS_WSYNC(channel);
  578. port->icount.tx++;
  579. port->x_char = 0;
  580. } else {
  581. struct circ_buf *xmit = &port->state->xmit;
  582. if (uart_circ_empty(xmit))
  583. return;
  584. writeb(xmit->buf[xmit->tail], &channel->data);
  585. ZSDELAY();
  586. ZS_WSYNC(channel);
  587. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  588. port->icount.tx++;
  589. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  590. uart_write_wakeup(&up->port);
  591. }
  592. }
  593. /* The port lock is held. */
  594. static void sunzilog_stop_rx(struct uart_port *port)
  595. {
  596. struct uart_sunzilog_port *up = UART_ZILOG(port);
  597. struct zilog_channel __iomem *channel;
  598. if (ZS_IS_CONS(up))
  599. return;
  600. channel = ZILOG_CHANNEL_FROM_PORT(port);
  601. /* Disable all RX interrupts. */
  602. up->curregs[R1] &= ~RxINT_MASK;
  603. sunzilog_maybe_update_regs(up, channel);
  604. }
  605. /* The port lock is held. */
  606. static void sunzilog_enable_ms(struct uart_port *port)
  607. {
  608. struct uart_sunzilog_port *up =
  609. container_of(port, struct uart_sunzilog_port, port);
  610. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  611. unsigned char new_reg;
  612. new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
  613. if (new_reg != up->curregs[R15]) {
  614. up->curregs[R15] = new_reg;
  615. /* NOTE: Not subject to 'transmitter active' rule. */
  616. write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
  617. }
  618. }
  619. /* The port lock is not held. */
  620. static void sunzilog_break_ctl(struct uart_port *port, int break_state)
  621. {
  622. struct uart_sunzilog_port *up =
  623. container_of(port, struct uart_sunzilog_port, port);
  624. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  625. unsigned char set_bits, clear_bits, new_reg;
  626. unsigned long flags;
  627. set_bits = clear_bits = 0;
  628. if (break_state)
  629. set_bits |= SND_BRK;
  630. else
  631. clear_bits |= SND_BRK;
  632. spin_lock_irqsave(&port->lock, flags);
  633. new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
  634. if (new_reg != up->curregs[R5]) {
  635. up->curregs[R5] = new_reg;
  636. /* NOTE: Not subject to 'transmitter active' rule. */
  637. write_zsreg(channel, R5, up->curregs[R5]);
  638. }
  639. spin_unlock_irqrestore(&port->lock, flags);
  640. }
  641. static void __sunzilog_startup(struct uart_sunzilog_port *up)
  642. {
  643. struct zilog_channel __iomem *channel;
  644. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  645. up->prev_status = readb(&channel->control);
  646. /* Enable receiver and transmitter. */
  647. up->curregs[R3] |= RxENAB;
  648. up->curregs[R5] |= TxENAB;
  649. up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
  650. sunzilog_maybe_update_regs(up, channel);
  651. }
  652. static int sunzilog_startup(struct uart_port *port)
  653. {
  654. struct uart_sunzilog_port *up = UART_ZILOG(port);
  655. unsigned long flags;
  656. if (ZS_IS_CONS(up))
  657. return 0;
  658. spin_lock_irqsave(&port->lock, flags);
  659. __sunzilog_startup(up);
  660. spin_unlock_irqrestore(&port->lock, flags);
  661. return 0;
  662. }
  663. /*
  664. * The test for ZS_IS_CONS is explained by the following e-mail:
  665. *****
  666. * From: Russell King <rmk@arm.linux.org.uk>
  667. * Date: Sun, 8 Dec 2002 10:18:38 +0000
  668. *
  669. * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
  670. * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
  671. * > and I noticed that something is not right with reference
  672. * > counting in this case. It seems that when the console
  673. * > is open by kernel initially, this is not accounted
  674. * > as an open, and uart_startup is not called.
  675. *
  676. * That is correct. We are unable to call uart_startup when the serial
  677. * console is initialised because it may need to allocate memory (as
  678. * request_irq does) and the memory allocators may not have been
  679. * initialised.
  680. *
  681. * 1. initialise the port into a state where it can send characters in the
  682. * console write method.
  683. *
  684. * 2. don't do the actual hardware shutdown in your shutdown() method (but
  685. * do the normal software shutdown - ie, free irqs etc)
  686. *****
  687. */
  688. static void sunzilog_shutdown(struct uart_port *port)
  689. {
  690. struct uart_sunzilog_port *up = UART_ZILOG(port);
  691. struct zilog_channel __iomem *channel;
  692. unsigned long flags;
  693. if (ZS_IS_CONS(up))
  694. return;
  695. spin_lock_irqsave(&port->lock, flags);
  696. channel = ZILOG_CHANNEL_FROM_PORT(port);
  697. /* Disable receiver and transmitter. */
  698. up->curregs[R3] &= ~RxENAB;
  699. up->curregs[R5] &= ~TxENAB;
  700. /* Disable all interrupts and BRK assertion. */
  701. up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
  702. up->curregs[R5] &= ~SND_BRK;
  703. sunzilog_maybe_update_regs(up, channel);
  704. spin_unlock_irqrestore(&port->lock, flags);
  705. }
  706. /* Shared by TTY driver and serial console setup. The port lock is held
  707. * and local interrupts are disabled.
  708. */
  709. static void
  710. sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
  711. unsigned int iflag, int brg)
  712. {
  713. up->curregs[R10] = NRZ;
  714. up->curregs[R11] = TCBR | RCBR;
  715. /* Program BAUD and clock source. */
  716. up->curregs[R4] &= ~XCLK_MASK;
  717. up->curregs[R4] |= X16CLK;
  718. up->curregs[R12] = brg & 0xff;
  719. up->curregs[R13] = (brg >> 8) & 0xff;
  720. up->curregs[R14] = BRSRC | BRENAB;
  721. /* Character size, stop bits, and parity. */
  722. up->curregs[R3] &= ~RxN_MASK;
  723. up->curregs[R5] &= ~TxN_MASK;
  724. switch (cflag & CSIZE) {
  725. case CS5:
  726. up->curregs[R3] |= Rx5;
  727. up->curregs[R5] |= Tx5;
  728. up->parity_mask = 0x1f;
  729. break;
  730. case CS6:
  731. up->curregs[R3] |= Rx6;
  732. up->curregs[R5] |= Tx6;
  733. up->parity_mask = 0x3f;
  734. break;
  735. case CS7:
  736. up->curregs[R3] |= Rx7;
  737. up->curregs[R5] |= Tx7;
  738. up->parity_mask = 0x7f;
  739. break;
  740. case CS8:
  741. default:
  742. up->curregs[R3] |= Rx8;
  743. up->curregs[R5] |= Tx8;
  744. up->parity_mask = 0xff;
  745. break;
  746. }
  747. up->curregs[R4] &= ~0x0c;
  748. if (cflag & CSTOPB)
  749. up->curregs[R4] |= SB2;
  750. else
  751. up->curregs[R4] |= SB1;
  752. if (cflag & PARENB)
  753. up->curregs[R4] |= PAR_ENAB;
  754. else
  755. up->curregs[R4] &= ~PAR_ENAB;
  756. if (!(cflag & PARODD))
  757. up->curregs[R4] |= PAR_EVEN;
  758. else
  759. up->curregs[R4] &= ~PAR_EVEN;
  760. up->port.read_status_mask = Rx_OVR;
  761. if (iflag & INPCK)
  762. up->port.read_status_mask |= CRC_ERR | PAR_ERR;
  763. if (iflag & (IGNBRK | BRKINT | PARMRK))
  764. up->port.read_status_mask |= BRK_ABRT;
  765. up->port.ignore_status_mask = 0;
  766. if (iflag & IGNPAR)
  767. up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
  768. if (iflag & IGNBRK) {
  769. up->port.ignore_status_mask |= BRK_ABRT;
  770. if (iflag & IGNPAR)
  771. up->port.ignore_status_mask |= Rx_OVR;
  772. }
  773. if ((cflag & CREAD) == 0)
  774. up->port.ignore_status_mask = 0xff;
  775. }
  776. /* The port lock is not held. */
  777. static void
  778. sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
  779. struct ktermios *old)
  780. {
  781. struct uart_sunzilog_port *up =
  782. container_of(port, struct uart_sunzilog_port, port);
  783. unsigned long flags;
  784. int baud, brg;
  785. baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
  786. spin_lock_irqsave(&up->port.lock, flags);
  787. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  788. sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
  789. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  790. up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
  791. else
  792. up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
  793. up->cflag = termios->c_cflag;
  794. sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
  795. uart_update_timeout(port, termios->c_cflag, baud);
  796. spin_unlock_irqrestore(&up->port.lock, flags);
  797. }
  798. static const char *sunzilog_type(struct uart_port *port)
  799. {
  800. struct uart_sunzilog_port *up = UART_ZILOG(port);
  801. return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
  802. }
  803. /* We do not request/release mappings of the registers here, this
  804. * happens at early serial probe time.
  805. */
  806. static void sunzilog_release_port(struct uart_port *port)
  807. {
  808. }
  809. static int sunzilog_request_port(struct uart_port *port)
  810. {
  811. return 0;
  812. }
  813. /* These do not need to do anything interesting either. */
  814. static void sunzilog_config_port(struct uart_port *port, int flags)
  815. {
  816. }
  817. /* We do not support letting the user mess with the divisor, IRQ, etc. */
  818. static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
  819. {
  820. return -EINVAL;
  821. }
  822. #ifdef CONFIG_CONSOLE_POLL
  823. static int sunzilog_get_poll_char(struct uart_port *port)
  824. {
  825. unsigned char ch, r1;
  826. struct uart_sunzilog_port *up =
  827. container_of(port, struct uart_sunzilog_port, port);
  828. struct zilog_channel __iomem *channel
  829. = ZILOG_CHANNEL_FROM_PORT(&up->port);
  830. r1 = read_zsreg(channel, R1);
  831. if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
  832. writeb(ERR_RES, &channel->control);
  833. ZSDELAY();
  834. ZS_WSYNC(channel);
  835. }
  836. ch = readb(&channel->control);
  837. ZSDELAY();
  838. /* This funny hack depends upon BRK_ABRT not interfering
  839. * with the other bits we care about in R1.
  840. */
  841. if (ch & BRK_ABRT)
  842. r1 |= BRK_ABRT;
  843. if (!(ch & Rx_CH_AV))
  844. return NO_POLL_CHAR;
  845. ch = readb(&channel->data);
  846. ZSDELAY();
  847. ch &= up->parity_mask;
  848. return ch;
  849. }
  850. static void sunzilog_put_poll_char(struct uart_port *port,
  851. unsigned char ch)
  852. {
  853. struct uart_sunzilog_port *up =
  854. container_of(port, struct uart_sunzilog_port, port);
  855. sunzilog_putchar(&up->port, ch);
  856. }
  857. #endif /* CONFIG_CONSOLE_POLL */
  858. static const struct uart_ops sunzilog_pops = {
  859. .tx_empty = sunzilog_tx_empty,
  860. .set_mctrl = sunzilog_set_mctrl,
  861. .get_mctrl = sunzilog_get_mctrl,
  862. .stop_tx = sunzilog_stop_tx,
  863. .start_tx = sunzilog_start_tx,
  864. .stop_rx = sunzilog_stop_rx,
  865. .enable_ms = sunzilog_enable_ms,
  866. .break_ctl = sunzilog_break_ctl,
  867. .startup = sunzilog_startup,
  868. .shutdown = sunzilog_shutdown,
  869. .set_termios = sunzilog_set_termios,
  870. .type = sunzilog_type,
  871. .release_port = sunzilog_release_port,
  872. .request_port = sunzilog_request_port,
  873. .config_port = sunzilog_config_port,
  874. .verify_port = sunzilog_verify_port,
  875. #ifdef CONFIG_CONSOLE_POLL
  876. .poll_get_char = sunzilog_get_poll_char,
  877. .poll_put_char = sunzilog_put_poll_char,
  878. #endif
  879. };
  880. static int uart_chip_count;
  881. static struct uart_sunzilog_port *sunzilog_port_table;
  882. static struct zilog_layout __iomem **sunzilog_chip_regs;
  883. static struct uart_sunzilog_port *sunzilog_irq_chain;
  884. static struct uart_driver sunzilog_reg = {
  885. .owner = THIS_MODULE,
  886. .driver_name = "sunzilog",
  887. .dev_name = "ttyS",
  888. .major = TTY_MAJOR,
  889. };
  890. static int __init sunzilog_alloc_tables(int num_sunzilog)
  891. {
  892. struct uart_sunzilog_port *up;
  893. unsigned long size;
  894. int num_channels = num_sunzilog * 2;
  895. int i;
  896. size = num_channels * sizeof(struct uart_sunzilog_port);
  897. sunzilog_port_table = kzalloc(size, GFP_KERNEL);
  898. if (!sunzilog_port_table)
  899. return -ENOMEM;
  900. for (i = 0; i < num_channels; i++) {
  901. up = &sunzilog_port_table[i];
  902. spin_lock_init(&up->port.lock);
  903. if (i == 0)
  904. sunzilog_irq_chain = up;
  905. if (i < num_channels - 1)
  906. up->next = up + 1;
  907. else
  908. up->next = NULL;
  909. }
  910. size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
  911. sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
  912. if (!sunzilog_chip_regs) {
  913. kfree(sunzilog_port_table);
  914. sunzilog_irq_chain = NULL;
  915. return -ENOMEM;
  916. }
  917. return 0;
  918. }
  919. static void sunzilog_free_tables(void)
  920. {
  921. kfree(sunzilog_port_table);
  922. sunzilog_irq_chain = NULL;
  923. kfree(sunzilog_chip_regs);
  924. }
  925. #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
  926. static void sunzilog_putchar(struct uart_port *port, int ch)
  927. {
  928. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  929. int loops = ZS_PUT_CHAR_MAX_DELAY;
  930. /* This is a timed polling loop so do not switch the explicit
  931. * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
  932. */
  933. do {
  934. unsigned char val = readb(&channel->control);
  935. if (val & Tx_BUF_EMP) {
  936. ZSDELAY();
  937. break;
  938. }
  939. udelay(5);
  940. } while (--loops);
  941. writeb(ch, &channel->data);
  942. ZSDELAY();
  943. ZS_WSYNC(channel);
  944. }
  945. #ifdef CONFIG_SERIO
  946. static DEFINE_SPINLOCK(sunzilog_serio_lock);
  947. static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
  948. {
  949. struct uart_sunzilog_port *up = serio->port_data;
  950. unsigned long flags;
  951. spin_lock_irqsave(&sunzilog_serio_lock, flags);
  952. sunzilog_putchar(&up->port, ch);
  953. spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
  954. return 0;
  955. }
  956. static int sunzilog_serio_open(struct serio *serio)
  957. {
  958. struct uart_sunzilog_port *up = serio->port_data;
  959. unsigned long flags;
  960. int ret;
  961. spin_lock_irqsave(&sunzilog_serio_lock, flags);
  962. if (!up->serio_open) {
  963. up->serio_open = 1;
  964. ret = 0;
  965. } else
  966. ret = -EBUSY;
  967. spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
  968. return ret;
  969. }
  970. static void sunzilog_serio_close(struct serio *serio)
  971. {
  972. struct uart_sunzilog_port *up = serio->port_data;
  973. unsigned long flags;
  974. spin_lock_irqsave(&sunzilog_serio_lock, flags);
  975. up->serio_open = 0;
  976. spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
  977. }
  978. #endif /* CONFIG_SERIO */
  979. #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
  980. static void
  981. sunzilog_console_write(struct console *con, const char *s, unsigned int count)
  982. {
  983. struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
  984. unsigned long flags;
  985. int locked = 1;
  986. if (up->port.sysrq || oops_in_progress)
  987. locked = spin_trylock_irqsave(&up->port.lock, flags);
  988. else
  989. spin_lock_irqsave(&up->port.lock, flags);
  990. uart_console_write(&up->port, s, count, sunzilog_putchar);
  991. udelay(2);
  992. if (locked)
  993. spin_unlock_irqrestore(&up->port.lock, flags);
  994. }
  995. static int __init sunzilog_console_setup(struct console *con, char *options)
  996. {
  997. struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
  998. unsigned long flags;
  999. int baud, brg;
  1000. if (up->port.type != PORT_SUNZILOG)
  1001. return -1;
  1002. printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
  1003. (sunzilog_reg.minor - 64) + con->index, con->index);
  1004. /* Get firmware console settings. */
  1005. sunserial_console_termios(con, up->port.dev->of_node);
  1006. /* Firmware console speed is limited to 150-->38400 baud so
  1007. * this hackish cflag thing is OK.
  1008. */
  1009. switch (con->cflag & CBAUD) {
  1010. case B150: baud = 150; break;
  1011. case B300: baud = 300; break;
  1012. case B600: baud = 600; break;
  1013. case B1200: baud = 1200; break;
  1014. case B2400: baud = 2400; break;
  1015. case B4800: baud = 4800; break;
  1016. default: case B9600: baud = 9600; break;
  1017. case B19200: baud = 19200; break;
  1018. case B38400: baud = 38400; break;
  1019. }
  1020. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  1021. spin_lock_irqsave(&up->port.lock, flags);
  1022. up->curregs[R15] |= BRKIE;
  1023. sunzilog_convert_to_zs(up, con->cflag, 0, brg);
  1024. sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
  1025. __sunzilog_startup(up);
  1026. spin_unlock_irqrestore(&up->port.lock, flags);
  1027. return 0;
  1028. }
  1029. static struct console sunzilog_console_ops = {
  1030. .name = "ttyS",
  1031. .write = sunzilog_console_write,
  1032. .device = uart_console_device,
  1033. .setup = sunzilog_console_setup,
  1034. .flags = CON_PRINTBUFFER,
  1035. .index = -1,
  1036. .data = &sunzilog_reg,
  1037. };
  1038. static inline struct console *SUNZILOG_CONSOLE(void)
  1039. {
  1040. return &sunzilog_console_ops;
  1041. }
  1042. #else
  1043. #define SUNZILOG_CONSOLE() (NULL)
  1044. #endif
  1045. static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
  1046. {
  1047. int baud, brg;
  1048. if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
  1049. up->cflag = B1200 | CS8 | CLOCAL | CREAD;
  1050. baud = 1200;
  1051. } else {
  1052. up->cflag = B4800 | CS8 | CLOCAL | CREAD;
  1053. baud = 4800;
  1054. }
  1055. up->curregs[R15] |= BRKIE;
  1056. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  1057. sunzilog_convert_to_zs(up, up->cflag, 0, brg);
  1058. sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
  1059. __sunzilog_startup(up);
  1060. }
  1061. #ifdef CONFIG_SERIO
  1062. static void sunzilog_register_serio(struct uart_sunzilog_port *up)
  1063. {
  1064. struct serio *serio = &up->serio;
  1065. serio->port_data = up;
  1066. serio->id.type = SERIO_RS232;
  1067. if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
  1068. serio->id.proto = SERIO_SUNKBD;
  1069. strlcpy(serio->name, "zskbd", sizeof(serio->name));
  1070. } else {
  1071. serio->id.proto = SERIO_SUN;
  1072. serio->id.extra = 1;
  1073. strlcpy(serio->name, "zsms", sizeof(serio->name));
  1074. }
  1075. strlcpy(serio->phys,
  1076. ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
  1077. "zs/serio0" : "zs/serio1"),
  1078. sizeof(serio->phys));
  1079. serio->write = sunzilog_serio_write;
  1080. serio->open = sunzilog_serio_open;
  1081. serio->close = sunzilog_serio_close;
  1082. serio->dev.parent = up->port.dev;
  1083. serio_register_port(serio);
  1084. }
  1085. #endif
  1086. static void sunzilog_init_hw(struct uart_sunzilog_port *up)
  1087. {
  1088. struct zilog_channel __iomem *channel;
  1089. unsigned long flags;
  1090. int baud, brg;
  1091. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  1092. spin_lock_irqsave(&up->port.lock, flags);
  1093. if (ZS_IS_CHANNEL_A(up)) {
  1094. write_zsreg(channel, R9, FHWRES);
  1095. ZSDELAY_LONG();
  1096. (void) read_zsreg(channel, R0);
  1097. }
  1098. if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
  1099. SUNZILOG_FLAG_CONS_MOUSE)) {
  1100. up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
  1101. up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
  1102. up->curregs[R3] = RxENAB | Rx8;
  1103. up->curregs[R5] = TxENAB | Tx8;
  1104. up->curregs[R6] = 0x00; /* SDLC Address */
  1105. up->curregs[R7] = 0x7E; /* SDLC Flag */
  1106. up->curregs[R9] = NV;
  1107. up->curregs[R7p] = 0x00;
  1108. sunzilog_init_kbdms(up);
  1109. /* Only enable interrupts if an ISR handler available */
  1110. if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
  1111. up->curregs[R9] |= MIE;
  1112. write_zsreg(channel, R9, up->curregs[R9]);
  1113. } else {
  1114. /* Normal serial TTY. */
  1115. up->parity_mask = 0xff;
  1116. up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
  1117. up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
  1118. up->curregs[R3] = RxENAB | Rx8;
  1119. up->curregs[R5] = TxENAB | Tx8;
  1120. up->curregs[R6] = 0x00; /* SDLC Address */
  1121. up->curregs[R7] = 0x7E; /* SDLC Flag */
  1122. up->curregs[R9] = NV;
  1123. up->curregs[R10] = NRZ;
  1124. up->curregs[R11] = TCBR | RCBR;
  1125. baud = 9600;
  1126. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  1127. up->curregs[R12] = (brg & 0xff);
  1128. up->curregs[R13] = (brg >> 8) & 0xff;
  1129. up->curregs[R14] = BRSRC | BRENAB;
  1130. up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
  1131. up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
  1132. if (__load_zsregs(channel, up->curregs)) {
  1133. up->flags |= SUNZILOG_FLAG_ESCC;
  1134. }
  1135. /* Only enable interrupts if an ISR handler available */
  1136. if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
  1137. up->curregs[R9] |= MIE;
  1138. write_zsreg(channel, R9, up->curregs[R9]);
  1139. }
  1140. spin_unlock_irqrestore(&up->port.lock, flags);
  1141. #ifdef CONFIG_SERIO
  1142. if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
  1143. SUNZILOG_FLAG_CONS_MOUSE))
  1144. sunzilog_register_serio(up);
  1145. #endif
  1146. }
  1147. static int zilog_irq;
  1148. static int zs_probe(struct platform_device *op)
  1149. {
  1150. static int kbm_inst, uart_inst;
  1151. int inst;
  1152. struct uart_sunzilog_port *up;
  1153. struct zilog_layout __iomem *rp;
  1154. int keyboard_mouse = 0;
  1155. int err;
  1156. if (of_find_property(op->dev.of_node, "keyboard", NULL))
  1157. keyboard_mouse = 1;
  1158. /* uarts must come before keyboards/mice */
  1159. if (keyboard_mouse)
  1160. inst = uart_chip_count + kbm_inst;
  1161. else
  1162. inst = uart_inst;
  1163. sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
  1164. sizeof(struct zilog_layout),
  1165. "zs");
  1166. if (!sunzilog_chip_regs[inst])
  1167. return -ENOMEM;
  1168. rp = sunzilog_chip_regs[inst];
  1169. if (!zilog_irq)
  1170. zilog_irq = op->archdata.irqs[0];
  1171. up = &sunzilog_port_table[inst * 2];
  1172. /* Channel A */
  1173. up[0].port.mapbase = op->resource[0].start + 0x00;
  1174. up[0].port.membase = (void __iomem *) &rp->channelA;
  1175. up[0].port.iotype = UPIO_MEM;
  1176. up[0].port.irq = op->archdata.irqs[0];
  1177. up[0].port.uartclk = ZS_CLOCK;
  1178. up[0].port.fifosize = 1;
  1179. up[0].port.ops = &sunzilog_pops;
  1180. up[0].port.type = PORT_SUNZILOG;
  1181. up[0].port.flags = 0;
  1182. up[0].port.line = (inst * 2) + 0;
  1183. up[0].port.dev = &op->dev;
  1184. up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
  1185. if (keyboard_mouse)
  1186. up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
  1187. sunzilog_init_hw(&up[0]);
  1188. /* Channel B */
  1189. up[1].port.mapbase = op->resource[0].start + 0x04;
  1190. up[1].port.membase = (void __iomem *) &rp->channelB;
  1191. up[1].port.iotype = UPIO_MEM;
  1192. up[1].port.irq = op->archdata.irqs[0];
  1193. up[1].port.uartclk = ZS_CLOCK;
  1194. up[1].port.fifosize = 1;
  1195. up[1].port.ops = &sunzilog_pops;
  1196. up[1].port.type = PORT_SUNZILOG;
  1197. up[1].port.flags = 0;
  1198. up[1].port.line = (inst * 2) + 1;
  1199. up[1].port.dev = &op->dev;
  1200. up[1].flags |= 0;
  1201. if (keyboard_mouse)
  1202. up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
  1203. sunzilog_init_hw(&up[1]);
  1204. if (!keyboard_mouse) {
  1205. if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
  1206. &sunzilog_reg, up[0].port.line,
  1207. false))
  1208. up->flags |= SUNZILOG_FLAG_IS_CONS;
  1209. err = uart_add_one_port(&sunzilog_reg, &up[0].port);
  1210. if (err) {
  1211. of_iounmap(&op->resource[0],
  1212. rp, sizeof(struct zilog_layout));
  1213. return err;
  1214. }
  1215. if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
  1216. &sunzilog_reg, up[1].port.line,
  1217. false))
  1218. up->flags |= SUNZILOG_FLAG_IS_CONS;
  1219. err = uart_add_one_port(&sunzilog_reg, &up[1].port);
  1220. if (err) {
  1221. uart_remove_one_port(&sunzilog_reg, &up[0].port);
  1222. of_iounmap(&op->resource[0],
  1223. rp, sizeof(struct zilog_layout));
  1224. return err;
  1225. }
  1226. uart_inst++;
  1227. } else {
  1228. printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
  1229. "is a %s\n",
  1230. dev_name(&op->dev),
  1231. (unsigned long long) up[0].port.mapbase,
  1232. op->archdata.irqs[0], sunzilog_type(&up[0].port));
  1233. printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
  1234. "is a %s\n",
  1235. dev_name(&op->dev),
  1236. (unsigned long long) up[1].port.mapbase,
  1237. op->archdata.irqs[0], sunzilog_type(&up[1].port));
  1238. kbm_inst++;
  1239. }
  1240. platform_set_drvdata(op, &up[0]);
  1241. return 0;
  1242. }
  1243. static void zs_remove_one(struct uart_sunzilog_port *up)
  1244. {
  1245. if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
  1246. #ifdef CONFIG_SERIO
  1247. serio_unregister_port(&up->serio);
  1248. #endif
  1249. } else
  1250. uart_remove_one_port(&sunzilog_reg, &up->port);
  1251. }
  1252. static int zs_remove(struct platform_device *op)
  1253. {
  1254. struct uart_sunzilog_port *up = platform_get_drvdata(op);
  1255. struct zilog_layout __iomem *regs;
  1256. zs_remove_one(&up[0]);
  1257. zs_remove_one(&up[1]);
  1258. regs = sunzilog_chip_regs[up[0].port.line / 2];
  1259. of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
  1260. return 0;
  1261. }
  1262. static const struct of_device_id zs_match[] = {
  1263. {
  1264. .name = "zs",
  1265. },
  1266. {},
  1267. };
  1268. MODULE_DEVICE_TABLE(of, zs_match);
  1269. static struct platform_driver zs_driver = {
  1270. .driver = {
  1271. .name = "zs",
  1272. .of_match_table = zs_match,
  1273. },
  1274. .probe = zs_probe,
  1275. .remove = zs_remove,
  1276. };
  1277. static int __init sunzilog_init(void)
  1278. {
  1279. struct device_node *dp;
  1280. int err;
  1281. int num_keybms = 0;
  1282. int num_sunzilog = 0;
  1283. for_each_node_by_name(dp, "zs") {
  1284. num_sunzilog++;
  1285. if (of_find_property(dp, "keyboard", NULL))
  1286. num_keybms++;
  1287. }
  1288. if (num_sunzilog) {
  1289. err = sunzilog_alloc_tables(num_sunzilog);
  1290. if (err)
  1291. goto out;
  1292. uart_chip_count = num_sunzilog - num_keybms;
  1293. err = sunserial_register_minors(&sunzilog_reg,
  1294. uart_chip_count * 2);
  1295. if (err)
  1296. goto out_free_tables;
  1297. }
  1298. err = platform_driver_register(&zs_driver);
  1299. if (err)
  1300. goto out_unregister_uart;
  1301. if (zilog_irq) {
  1302. struct uart_sunzilog_port *up = sunzilog_irq_chain;
  1303. err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
  1304. "zs", sunzilog_irq_chain);
  1305. if (err)
  1306. goto out_unregister_driver;
  1307. /* Enable Interrupts */
  1308. while (up) {
  1309. struct zilog_channel __iomem *channel;
  1310. /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
  1311. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  1312. up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
  1313. up->curregs[R9] |= MIE;
  1314. write_zsreg(channel, R9, up->curregs[R9]);
  1315. up = up->next;
  1316. }
  1317. }
  1318. out:
  1319. return err;
  1320. out_unregister_driver:
  1321. platform_driver_unregister(&zs_driver);
  1322. out_unregister_uart:
  1323. if (num_sunzilog) {
  1324. sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
  1325. sunzilog_reg.cons = NULL;
  1326. }
  1327. out_free_tables:
  1328. sunzilog_free_tables();
  1329. goto out;
  1330. }
  1331. static void __exit sunzilog_exit(void)
  1332. {
  1333. platform_driver_unregister(&zs_driver);
  1334. if (zilog_irq) {
  1335. struct uart_sunzilog_port *up = sunzilog_irq_chain;
  1336. /* Disable Interrupts */
  1337. while (up) {
  1338. struct zilog_channel __iomem *channel;
  1339. /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
  1340. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  1341. up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
  1342. up->curregs[R9] &= ~MIE;
  1343. write_zsreg(channel, R9, up->curregs[R9]);
  1344. up = up->next;
  1345. }
  1346. free_irq(zilog_irq, sunzilog_irq_chain);
  1347. zilog_irq = 0;
  1348. }
  1349. if (sunzilog_reg.nr) {
  1350. sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
  1351. sunzilog_free_tables();
  1352. }
  1353. }
  1354. module_init(sunzilog_init);
  1355. module_exit(sunzilog_exit);
  1356. MODULE_AUTHOR("David S. Miller");
  1357. MODULE_DESCRIPTION("Sun Zilog serial port driver");
  1358. MODULE_VERSION("2.0");
  1359. MODULE_LICENSE("GPL");