ehci-hcd.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Enhanced Host Controller Interface (EHCI) driver for USB.
  4. *
  5. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  6. *
  7. * Copyright (c) 2000-2004 by David Brownell
  8. */
  9. #include <linux/module.h>
  10. #include <linux/pci.h>
  11. #include <linux/dmapool.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/ioport.h>
  15. #include <linux/sched.h>
  16. #include <linux/vmalloc.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/hrtimer.h>
  20. #include <linux/list.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/usb.h>
  23. #include <linux/usb/hcd.h>
  24. #include <linux/usb/otg.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/debugfs.h>
  28. #include <linux/slab.h>
  29. #include <asm/byteorder.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <asm/unaligned.h>
  33. #if defined(CONFIG_PPC_PS3)
  34. #include <asm/firmware.h>
  35. #endif
  36. /*-------------------------------------------------------------------------*/
  37. /*
  38. * EHCI hc_driver implementation ... experimental, incomplete.
  39. * Based on the final 1.0 register interface specification.
  40. *
  41. * USB 2.0 shows up in upcoming www.pcmcia.org technology.
  42. * First was PCMCIA, like ISA; then CardBus, which is PCI.
  43. * Next comes "CardBay", using USB 2.0 signals.
  44. *
  45. * Contains additional contributions by Brad Hards, Rory Bolt, and others.
  46. * Special thanks to Intel and VIA for providing host controllers to
  47. * test this driver on, and Cypress (including In-System Design) for
  48. * providing early devices for those host controllers to talk to!
  49. */
  50. #define DRIVER_AUTHOR "David Brownell"
  51. #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
  52. static const char hcd_name [] = "ehci_hcd";
  53. #undef EHCI_URB_TRACE
  54. /* magic numbers that can affect system performance */
  55. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  56. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  57. #define EHCI_TUNE_RL_TT 0
  58. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  59. #define EHCI_TUNE_MULT_TT 1
  60. /*
  61. * Some drivers think it's safe to schedule isochronous transfers more than
  62. * 256 ms into the future (partly as a result of an old bug in the scheduling
  63. * code). In an attempt to avoid trouble, we will use a minimum scheduling
  64. * length of 512 frames instead of 256.
  65. */
  66. #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
  67. /* Initial IRQ latency: faster than hw default */
  68. static int log2_irq_thresh = 0; // 0 to 6
  69. module_param (log2_irq_thresh, int, S_IRUGO);
  70. MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  71. /* initial park setting: slower than hw default */
  72. static unsigned park = 0;
  73. module_param (park, uint, S_IRUGO);
  74. MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
  75. /* for flakey hardware, ignore overcurrent indicators */
  76. static bool ignore_oc;
  77. module_param (ignore_oc, bool, S_IRUGO);
  78. MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
  79. #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
  80. /*-------------------------------------------------------------------------*/
  81. #include "ehci.h"
  82. #include "pci-quirks.h"
  83. static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE],
  84. struct ehci_tt *tt);
  85. /*
  86. * The MosChip MCS9990 controller updates its microframe counter
  87. * a little before the frame counter, and occasionally we will read
  88. * the invalid intermediate value. Avoid problems by checking the
  89. * microframe number (the low-order 3 bits); if they are 0 then
  90. * re-read the register to get the correct value.
  91. */
  92. static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
  93. {
  94. unsigned uf;
  95. uf = ehci_readl(ehci, &ehci->regs->frame_index);
  96. if (unlikely((uf & 7) == 0))
  97. uf = ehci_readl(ehci, &ehci->regs->frame_index);
  98. return uf;
  99. }
  100. static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
  101. {
  102. if (ehci->frame_index_bug)
  103. return ehci_moschip_read_frame_index(ehci);
  104. return ehci_readl(ehci, &ehci->regs->frame_index);
  105. }
  106. #include "ehci-dbg.c"
  107. /*-------------------------------------------------------------------------*/
  108. /*
  109. * ehci_handshake - spin reading hc until handshake completes or fails
  110. * @ptr: address of hc register to be read
  111. * @mask: bits to look at in result of read
  112. * @done: value of those bits when handshake succeeds
  113. * @usec: timeout in microseconds
  114. *
  115. * Returns negative errno, or zero on success
  116. *
  117. * Success happens when the "mask" bits have the specified value (hardware
  118. * handshake done). There are two failure modes: "usec" have passed (major
  119. * hardware flakeout), or the register reads as all-ones (hardware removed).
  120. *
  121. * That last failure should_only happen in cases like physical cardbus eject
  122. * before driver shutdown. But it also seems to be caused by bugs in cardbus
  123. * bridge shutdown: shutting down the bridge before the devices using it.
  124. */
  125. int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
  126. u32 mask, u32 done, int usec)
  127. {
  128. u32 result;
  129. do {
  130. result = ehci_readl(ehci, ptr);
  131. if (result == ~(u32)0) /* card removed */
  132. return -ENODEV;
  133. result &= mask;
  134. if (result == done)
  135. return 0;
  136. udelay (1);
  137. usec--;
  138. } while (usec > 0);
  139. return -ETIMEDOUT;
  140. }
  141. EXPORT_SYMBOL_GPL(ehci_handshake);
  142. /* check TDI/ARC silicon is in host mode */
  143. static int tdi_in_host_mode (struct ehci_hcd *ehci)
  144. {
  145. u32 tmp;
  146. tmp = ehci_readl(ehci, &ehci->regs->usbmode);
  147. return (tmp & 3) == USBMODE_CM_HC;
  148. }
  149. /*
  150. * Force HC to halt state from unknown (EHCI spec section 2.3).
  151. * Must be called with interrupts enabled and the lock not held.
  152. */
  153. static int ehci_halt (struct ehci_hcd *ehci)
  154. {
  155. u32 temp;
  156. spin_lock_irq(&ehci->lock);
  157. /* disable any irqs left enabled by previous code */
  158. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  159. if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
  160. spin_unlock_irq(&ehci->lock);
  161. return 0;
  162. }
  163. /*
  164. * This routine gets called during probe before ehci->command
  165. * has been initialized, so we can't rely on its value.
  166. */
  167. ehci->command &= ~CMD_RUN;
  168. temp = ehci_readl(ehci, &ehci->regs->command);
  169. temp &= ~(CMD_RUN | CMD_IAAD);
  170. ehci_writel(ehci, temp, &ehci->regs->command);
  171. spin_unlock_irq(&ehci->lock);
  172. synchronize_irq(ehci_to_hcd(ehci)->irq);
  173. return ehci_handshake(ehci, &ehci->regs->status,
  174. STS_HALT, STS_HALT, 16 * 125);
  175. }
  176. /* put TDI/ARC silicon into EHCI mode */
  177. static void tdi_reset (struct ehci_hcd *ehci)
  178. {
  179. u32 tmp;
  180. tmp = ehci_readl(ehci, &ehci->regs->usbmode);
  181. tmp |= USBMODE_CM_HC;
  182. /* The default byte access to MMR space is LE after
  183. * controller reset. Set the required endian mode
  184. * for transfer buffers to match the host microprocessor
  185. */
  186. if (ehci_big_endian_mmio(ehci))
  187. tmp |= USBMODE_BE;
  188. ehci_writel(ehci, tmp, &ehci->regs->usbmode);
  189. }
  190. /*
  191. * Reset a non-running (STS_HALT == 1) controller.
  192. * Must be called with interrupts enabled and the lock not held.
  193. */
  194. int ehci_reset(struct ehci_hcd *ehci)
  195. {
  196. int retval;
  197. u32 command = ehci_readl(ehci, &ehci->regs->command);
  198. /* If the EHCI debug controller is active, special care must be
  199. * taken before and after a host controller reset */
  200. if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
  201. ehci->debug = NULL;
  202. command |= CMD_RESET;
  203. dbg_cmd (ehci, "reset", command);
  204. ehci_writel(ehci, command, &ehci->regs->command);
  205. ehci->rh_state = EHCI_RH_HALTED;
  206. ehci->next_statechange = jiffies;
  207. retval = ehci_handshake(ehci, &ehci->regs->command,
  208. CMD_RESET, 0, 250 * 1000);
  209. if (ehci->has_hostpc) {
  210. ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
  211. &ehci->regs->usbmode_ex);
  212. ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
  213. }
  214. if (retval)
  215. return retval;
  216. if (ehci_is_TDI(ehci))
  217. tdi_reset (ehci);
  218. if (ehci->debug)
  219. dbgp_external_startup(ehci_to_hcd(ehci));
  220. ehci->port_c_suspend = ehci->suspended_ports =
  221. ehci->resuming_ports = 0;
  222. return retval;
  223. }
  224. EXPORT_SYMBOL_GPL(ehci_reset);
  225. /*
  226. * Idle the controller (turn off the schedules).
  227. * Must be called with interrupts enabled and the lock not held.
  228. */
  229. static void ehci_quiesce (struct ehci_hcd *ehci)
  230. {
  231. u32 temp;
  232. if (ehci->rh_state != EHCI_RH_RUNNING)
  233. return;
  234. /* wait for any schedule enables/disables to take effect */
  235. temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
  236. ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp,
  237. 16 * 125);
  238. /* then disable anything that's still active */
  239. spin_lock_irq(&ehci->lock);
  240. ehci->command &= ~(CMD_ASE | CMD_PSE);
  241. ehci_writel(ehci, ehci->command, &ehci->regs->command);
  242. spin_unlock_irq(&ehci->lock);
  243. /* hardware can take 16 microframes to turn off ... */
  244. ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0,
  245. 16 * 125);
  246. }
  247. /*-------------------------------------------------------------------------*/
  248. static void end_iaa_cycle(struct ehci_hcd *ehci);
  249. static void end_unlink_async(struct ehci_hcd *ehci);
  250. static void unlink_empty_async(struct ehci_hcd *ehci);
  251. static void ehci_work(struct ehci_hcd *ehci);
  252. static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
  253. static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
  254. static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable);
  255. #include "ehci-timer.c"
  256. #include "ehci-hub.c"
  257. #include "ehci-mem.c"
  258. #include "ehci-q.c"
  259. #include "ehci-sched.c"
  260. #include "ehci-sysfs.c"
  261. /*-------------------------------------------------------------------------*/
  262. /* On some systems, leaving remote wakeup enabled prevents system shutdown.
  263. * The firmware seems to think that powering off is a wakeup event!
  264. * This routine turns off remote wakeup and everything else, on all ports.
  265. */
  266. static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
  267. {
  268. int port = HCS_N_PORTS(ehci->hcs_params);
  269. while (port--) {
  270. spin_unlock_irq(&ehci->lock);
  271. ehci_port_power(ehci, port, false);
  272. spin_lock_irq(&ehci->lock);
  273. ehci_writel(ehci, PORT_RWC_BITS,
  274. &ehci->regs->port_status[port]);
  275. }
  276. }
  277. /*
  278. * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
  279. * Must be called with interrupts enabled and the lock not held.
  280. */
  281. static void ehci_silence_controller(struct ehci_hcd *ehci)
  282. {
  283. ehci_halt(ehci);
  284. spin_lock_irq(&ehci->lock);
  285. ehci->rh_state = EHCI_RH_HALTED;
  286. ehci_turn_off_all_ports(ehci);
  287. /* make BIOS/etc use companion controller during reboot */
  288. ehci_writel(ehci, 0, &ehci->regs->configured_flag);
  289. /* unblock posted writes */
  290. ehci_readl(ehci, &ehci->regs->configured_flag);
  291. spin_unlock_irq(&ehci->lock);
  292. }
  293. /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
  294. * This forcibly disables dma and IRQs, helping kexec and other cases
  295. * where the next system software may expect clean state.
  296. */
  297. static void ehci_shutdown(struct usb_hcd *hcd)
  298. {
  299. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  300. /**
  301. * Protect the system from crashing at system shutdown in cases where
  302. * usb host is not added yet from OTG controller driver.
  303. * As ehci_setup() not done yet, so stop accessing registers or
  304. * variables initialized in ehci_setup()
  305. */
  306. if (!ehci->sbrn)
  307. return;
  308. spin_lock_irq(&ehci->lock);
  309. ehci->shutdown = true;
  310. ehci->rh_state = EHCI_RH_STOPPING;
  311. ehci->enabled_hrtimer_events = 0;
  312. spin_unlock_irq(&ehci->lock);
  313. ehci_silence_controller(ehci);
  314. hrtimer_cancel(&ehci->hrtimer);
  315. }
  316. /*-------------------------------------------------------------------------*/
  317. /*
  318. * ehci_work is called from some interrupts, timers, and so on.
  319. * it calls driver completion functions, after dropping ehci->lock.
  320. */
  321. static void ehci_work (struct ehci_hcd *ehci)
  322. {
  323. /* another CPU may drop ehci->lock during a schedule scan while
  324. * it reports urb completions. this flag guards against bogus
  325. * attempts at re-entrant schedule scanning.
  326. */
  327. if (ehci->scanning) {
  328. ehci->need_rescan = true;
  329. return;
  330. }
  331. ehci->scanning = true;
  332. rescan:
  333. ehci->need_rescan = false;
  334. if (ehci->async_count)
  335. scan_async(ehci);
  336. if (ehci->intr_count > 0)
  337. scan_intr(ehci);
  338. if (ehci->isoc_count > 0)
  339. scan_isoc(ehci);
  340. if (ehci->need_rescan)
  341. goto rescan;
  342. ehci->scanning = false;
  343. /* the IO watchdog guards against hardware or driver bugs that
  344. * misplace IRQs, and should let us run completely without IRQs.
  345. * such lossage has been observed on both VT6202 and VT8235.
  346. */
  347. turn_on_io_watchdog(ehci);
  348. }
  349. /*
  350. * Called when the ehci_hcd module is removed.
  351. */
  352. static void ehci_stop (struct usb_hcd *hcd)
  353. {
  354. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  355. ehci_dbg (ehci, "stop\n");
  356. /* no more interrupts ... */
  357. spin_lock_irq(&ehci->lock);
  358. ehci->enabled_hrtimer_events = 0;
  359. spin_unlock_irq(&ehci->lock);
  360. ehci_quiesce(ehci);
  361. ehci_silence_controller(ehci);
  362. ehci_reset (ehci);
  363. hrtimer_cancel(&ehci->hrtimer);
  364. remove_sysfs_files(ehci);
  365. remove_debug_files (ehci);
  366. /* root hub is shut down separately (first, when possible) */
  367. spin_lock_irq (&ehci->lock);
  368. end_free_itds(ehci);
  369. spin_unlock_irq (&ehci->lock);
  370. ehci_mem_cleanup (ehci);
  371. if (ehci->amd_pll_fix == 1)
  372. usb_amd_dev_put();
  373. dbg_status (ehci, "ehci_stop completed",
  374. ehci_readl(ehci, &ehci->regs->status));
  375. }
  376. /* one-time init, only for memory state */
  377. static int ehci_init(struct usb_hcd *hcd)
  378. {
  379. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  380. u32 temp;
  381. int retval;
  382. u32 hcc_params;
  383. struct ehci_qh_hw *hw;
  384. spin_lock_init(&ehci->lock);
  385. /*
  386. * keep io watchdog by default, those good HCDs could turn off it later
  387. */
  388. ehci->need_io_watchdog = 1;
  389. hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
  390. ehci->hrtimer.function = ehci_hrtimer_func;
  391. ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
  392. hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
  393. /*
  394. * by default set standard 80% (== 100 usec/uframe) max periodic
  395. * bandwidth as required by USB 2.0
  396. */
  397. ehci->uframe_periodic_max = 100;
  398. /*
  399. * hw default: 1K periodic list heads, one per frame.
  400. * periodic_size can shrink by USBCMD update if hcc_params allows.
  401. */
  402. ehci->periodic_size = DEFAULT_I_TDPS;
  403. INIT_LIST_HEAD(&ehci->async_unlink);
  404. INIT_LIST_HEAD(&ehci->async_idle);
  405. INIT_LIST_HEAD(&ehci->intr_unlink_wait);
  406. INIT_LIST_HEAD(&ehci->intr_unlink);
  407. INIT_LIST_HEAD(&ehci->intr_qh_list);
  408. INIT_LIST_HEAD(&ehci->cached_itd_list);
  409. INIT_LIST_HEAD(&ehci->cached_sitd_list);
  410. INIT_LIST_HEAD(&ehci->tt_list);
  411. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  412. /* periodic schedule size can be smaller than default */
  413. switch (EHCI_TUNE_FLS) {
  414. case 0: ehci->periodic_size = 1024; break;
  415. case 1: ehci->periodic_size = 512; break;
  416. case 2: ehci->periodic_size = 256; break;
  417. default: BUG();
  418. }
  419. }
  420. if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
  421. return retval;
  422. /* controllers may cache some of the periodic schedule ... */
  423. if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
  424. ehci->i_thresh = 0;
  425. else // N microframes cached
  426. ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  427. /*
  428. * dedicate a qh for the async ring head, since we couldn't unlink
  429. * a 'real' qh without stopping the async schedule [4.8]. use it
  430. * as the 'reclamation list head' too.
  431. * its dummy is used in hw_alt_next of many tds, to prevent the qh
  432. * from automatically advancing to the next td after short reads.
  433. */
  434. ehci->async->qh_next.qh = NULL;
  435. hw = ehci->async->hw;
  436. hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
  437. hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
  438. #if defined(CONFIG_PPC_PS3)
  439. hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
  440. #endif
  441. hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
  442. hw->hw_qtd_next = EHCI_LIST_END(ehci);
  443. ehci->async->qh_state = QH_STATE_LINKED;
  444. hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
  445. /* clear interrupt enables, set irq latency */
  446. if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
  447. log2_irq_thresh = 0;
  448. temp = 1 << (16 + log2_irq_thresh);
  449. if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
  450. ehci->has_ppcd = 1;
  451. ehci_dbg(ehci, "enable per-port change event\n");
  452. temp |= CMD_PPCEE;
  453. }
  454. if (HCC_CANPARK(hcc_params)) {
  455. /* HW default park == 3, on hardware that supports it (like
  456. * NVidia and ALI silicon), maximizes throughput on the async
  457. * schedule by avoiding QH fetches between transfers.
  458. *
  459. * With fast usb storage devices and NForce2, "park" seems to
  460. * make problems: throughput reduction (!), data errors...
  461. */
  462. if (park) {
  463. park = min(park, (unsigned) 3);
  464. temp |= CMD_PARK;
  465. temp |= park << 8;
  466. }
  467. ehci_dbg(ehci, "park %d\n", park);
  468. }
  469. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  470. /* periodic schedule size can be smaller than default */
  471. temp &= ~(3 << 2);
  472. temp |= (EHCI_TUNE_FLS << 2);
  473. }
  474. ehci->command = temp;
  475. /* Accept arbitrarily long scatter-gather lists */
  476. if (!(hcd->driver->flags & HCD_LOCAL_MEM))
  477. hcd->self.sg_tablesize = ~0;
  478. /* Prepare for unlinking active QHs */
  479. ehci->old_current = ~0;
  480. return 0;
  481. }
  482. /* start HC running; it's halted, ehci_init() has been run (once) */
  483. static int ehci_run (struct usb_hcd *hcd)
  484. {
  485. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  486. u32 temp;
  487. u32 hcc_params;
  488. int rc;
  489. hcd->uses_new_polling = 1;
  490. /* EHCI spec section 4.1 */
  491. ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
  492. ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
  493. /*
  494. * hcc_params controls whether ehci->regs->segment must (!!!)
  495. * be used; it constrains QH/ITD/SITD and QTD locations.
  496. * dma_pool consistent memory always uses segment zero.
  497. * streaming mappings for I/O buffers, like pci_map_single(),
  498. * can return segments above 4GB, if the device allows.
  499. *
  500. * NOTE: the dma mask is visible through dev->dma_mask, so
  501. * drivers can pass this info along ... like NETIF_F_HIGHDMA,
  502. * Scsi_Host.highmem_io, and so forth. It's readonly to all
  503. * host side drivers though.
  504. */
  505. hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
  506. if (HCC_64BIT_ADDR(hcc_params)) {
  507. ehci_writel(ehci, 0, &ehci->regs->segment);
  508. #if 0
  509. // this is deeply broken on almost all architectures
  510. if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
  511. ehci_info(ehci, "enabled 64bit DMA\n");
  512. #endif
  513. }
  514. // Philips, Intel, and maybe others need CMD_RUN before the
  515. // root hub will detect new devices (why?); NEC doesn't
  516. ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  517. ehci->command |= CMD_RUN;
  518. ehci_writel(ehci, ehci->command, &ehci->regs->command);
  519. dbg_cmd (ehci, "init", ehci->command);
  520. /*
  521. * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
  522. * are explicitly handed to companion controller(s), so no TT is
  523. * involved with the root hub. (Except where one is integrated,
  524. * and there's no companion controller unless maybe for USB OTG.)
  525. *
  526. * Turning on the CF flag will transfer ownership of all ports
  527. * from the companions to the EHCI controller. If any of the
  528. * companions are in the middle of a port reset at the time, it
  529. * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
  530. * guarantees that no resets are in progress. After we set CF,
  531. * a short delay lets the hardware catch up; new resets shouldn't
  532. * be started before the port switching actions could complete.
  533. */
  534. down_write(&ehci_cf_port_reset_rwsem);
  535. ehci->rh_state = EHCI_RH_RUNNING;
  536. ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
  537. /* Wait until HC become operational */
  538. ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
  539. msleep(5);
  540. rc = ehci_handshake(ehci, &ehci->regs->status, STS_HALT, 0, 100 * 1000);
  541. up_write(&ehci_cf_port_reset_rwsem);
  542. if (rc) {
  543. ehci_err(ehci, "USB %x.%x, controller refused to start: %d\n",
  544. ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), rc);
  545. return rc;
  546. }
  547. ehci->last_periodic_enable = ktime_get_real();
  548. temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
  549. ehci_info (ehci,
  550. "USB %x.%x started, EHCI %x.%02x%s\n",
  551. ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
  552. temp >> 8, temp & 0xff,
  553. ignore_oc ? ", overcurrent ignored" : "");
  554. ehci_writel(ehci, INTR_MASK,
  555. &ehci->regs->intr_enable); /* Turn On Interrupts */
  556. /* GRR this is run-once init(), being done every time the HC starts.
  557. * So long as they're part of class devices, we can't do it init()
  558. * since the class device isn't created that early.
  559. */
  560. create_debug_files(ehci);
  561. create_sysfs_files(ehci);
  562. return 0;
  563. }
  564. int ehci_setup(struct usb_hcd *hcd)
  565. {
  566. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  567. int retval;
  568. ehci->regs = (void __iomem *)ehci->caps +
  569. HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
  570. dbg_hcs_params(ehci, "reset");
  571. dbg_hcc_params(ehci, "reset");
  572. /* cache this readonly data; minimize chip reads */
  573. ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
  574. ehci->sbrn = HCD_USB2;
  575. /* data structure init */
  576. retval = ehci_init(hcd);
  577. if (retval)
  578. return retval;
  579. retval = ehci_halt(ehci);
  580. if (retval) {
  581. ehci_mem_cleanup(ehci);
  582. return retval;
  583. }
  584. ehci_reset(ehci);
  585. return 0;
  586. }
  587. EXPORT_SYMBOL_GPL(ehci_setup);
  588. /*-------------------------------------------------------------------------*/
  589. static irqreturn_t ehci_irq (struct usb_hcd *hcd)
  590. {
  591. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  592. u32 status, masked_status, pcd_status = 0, cmd;
  593. int bh;
  594. unsigned long flags;
  595. /*
  596. * For threadirqs option we use spin_lock_irqsave() variant to prevent
  597. * deadlock with ehci hrtimer callback, because hrtimer callbacks run
  598. * in interrupt context even when threadirqs is specified. We can go
  599. * back to spin_lock() variant when hrtimer callbacks become threaded.
  600. */
  601. spin_lock_irqsave(&ehci->lock, flags);
  602. status = ehci_readl(ehci, &ehci->regs->status);
  603. /* e.g. cardbus physical eject */
  604. if (status == ~(u32) 0) {
  605. ehci_dbg (ehci, "device removed\n");
  606. goto dead;
  607. }
  608. /*
  609. * We don't use STS_FLR, but some controllers don't like it to
  610. * remain on, so mask it out along with the other status bits.
  611. */
  612. masked_status = status & (INTR_MASK | STS_FLR);
  613. /* Shared IRQ? */
  614. if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
  615. spin_unlock_irqrestore(&ehci->lock, flags);
  616. return IRQ_NONE;
  617. }
  618. /* clear (just) interrupts */
  619. ehci_writel(ehci, masked_status, &ehci->regs->status);
  620. cmd = ehci_readl(ehci, &ehci->regs->command);
  621. bh = 0;
  622. /* normal [4.15.1.2] or error [4.15.1.1] completion */
  623. if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
  624. if (likely ((status & STS_ERR) == 0))
  625. COUNT (ehci->stats.normal);
  626. else
  627. COUNT (ehci->stats.error);
  628. bh = 1;
  629. }
  630. /* complete the unlinking of some qh [4.15.2.3] */
  631. if (status & STS_IAA) {
  632. /* Turn off the IAA watchdog */
  633. ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
  634. /*
  635. * Mild optimization: Allow another IAAD to reset the
  636. * hrtimer, if one occurs before the next expiration.
  637. * In theory we could always cancel the hrtimer, but
  638. * tests show that about half the time it will be reset
  639. * for some other event anyway.
  640. */
  641. if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
  642. ++ehci->next_hrtimer_event;
  643. /* guard against (alleged) silicon errata */
  644. if (cmd & CMD_IAAD)
  645. ehci_dbg(ehci, "IAA with IAAD still set?\n");
  646. if (ehci->iaa_in_progress)
  647. COUNT(ehci->stats.iaa);
  648. end_iaa_cycle(ehci);
  649. }
  650. /* remote wakeup [4.3.1] */
  651. if (status & STS_PCD) {
  652. unsigned i = HCS_N_PORTS (ehci->hcs_params);
  653. u32 ppcd = ~0;
  654. /* kick root hub later */
  655. pcd_status = status;
  656. /* resume root hub? */
  657. if (ehci->rh_state == EHCI_RH_SUSPENDED)
  658. usb_hcd_resume_root_hub(hcd);
  659. /* get per-port change detect bits */
  660. if (ehci->has_ppcd)
  661. ppcd = status >> 16;
  662. while (i--) {
  663. int pstatus;
  664. /* leverage per-port change bits feature */
  665. if (!(ppcd & (1 << i)))
  666. continue;
  667. pstatus = ehci_readl(ehci,
  668. &ehci->regs->port_status[i]);
  669. if (pstatus & PORT_OWNER)
  670. continue;
  671. if (!(test_bit(i, &ehci->suspended_ports) &&
  672. ((pstatus & PORT_RESUME) ||
  673. !(pstatus & PORT_SUSPEND)) &&
  674. (pstatus & PORT_PE) &&
  675. ehci->reset_done[i] == 0))
  676. continue;
  677. /* start USB_RESUME_TIMEOUT msec resume signaling from
  678. * this port, and make hub_wq collect
  679. * PORT_STAT_C_SUSPEND to stop that signaling.
  680. */
  681. ehci->reset_done[i] = jiffies +
  682. msecs_to_jiffies(USB_RESUME_TIMEOUT);
  683. set_bit(i, &ehci->resuming_ports);
  684. ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
  685. usb_hcd_start_port_resume(&hcd->self, i);
  686. mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
  687. }
  688. }
  689. /* PCI errors [4.15.2.4] */
  690. if (unlikely ((status & STS_FATAL) != 0)) {
  691. ehci_err(ehci, "fatal error\n");
  692. dbg_cmd(ehci, "fatal", cmd);
  693. dbg_status(ehci, "fatal", status);
  694. dead:
  695. usb_hc_died(hcd);
  696. /* Don't let the controller do anything more */
  697. ehci->shutdown = true;
  698. ehci->rh_state = EHCI_RH_STOPPING;
  699. ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
  700. ehci_writel(ehci, ehci->command, &ehci->regs->command);
  701. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  702. ehci_handle_controller_death(ehci);
  703. /* Handle completions when the controller stops */
  704. bh = 0;
  705. }
  706. if (bh)
  707. ehci_work (ehci);
  708. spin_unlock_irqrestore(&ehci->lock, flags);
  709. if (pcd_status)
  710. usb_hcd_poll_rh_status(hcd);
  711. return IRQ_HANDLED;
  712. }
  713. /*-------------------------------------------------------------------------*/
  714. /*
  715. * non-error returns are a promise to giveback() the urb later
  716. * we drop ownership so next owner (or urb unlink) can get it
  717. *
  718. * urb + dev is in hcd.self.controller.urb_list
  719. * we're queueing TDs onto software and hardware lists
  720. *
  721. * hcd-specific init for hcpriv hasn't been done yet
  722. *
  723. * NOTE: control, bulk, and interrupt share the same code to append TDs
  724. * to a (possibly active) QH, and the same QH scanning code.
  725. */
  726. static int ehci_urb_enqueue (
  727. struct usb_hcd *hcd,
  728. struct urb *urb,
  729. gfp_t mem_flags
  730. ) {
  731. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  732. struct list_head qtd_list;
  733. INIT_LIST_HEAD (&qtd_list);
  734. switch (usb_pipetype (urb->pipe)) {
  735. case PIPE_CONTROL:
  736. /* qh_completions() code doesn't handle all the fault cases
  737. * in multi-TD control transfers. Even 1KB is rare anyway.
  738. */
  739. if (urb->transfer_buffer_length > (16 * 1024))
  740. return -EMSGSIZE;
  741. /* FALLTHROUGH */
  742. /* case PIPE_BULK: */
  743. default:
  744. if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
  745. return -ENOMEM;
  746. return submit_async(ehci, urb, &qtd_list, mem_flags);
  747. case PIPE_INTERRUPT:
  748. if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
  749. return -ENOMEM;
  750. return intr_submit(ehci, urb, &qtd_list, mem_flags);
  751. case PIPE_ISOCHRONOUS:
  752. if (urb->dev->speed == USB_SPEED_HIGH)
  753. return itd_submit (ehci, urb, mem_flags);
  754. else
  755. return sitd_submit (ehci, urb, mem_flags);
  756. }
  757. }
  758. /* remove from hardware lists
  759. * completions normally happen asynchronously
  760. */
  761. static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  762. {
  763. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  764. struct ehci_qh *qh;
  765. unsigned long flags;
  766. int rc;
  767. spin_lock_irqsave (&ehci->lock, flags);
  768. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  769. if (rc)
  770. goto done;
  771. if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
  772. /*
  773. * We don't expedite dequeue for isochronous URBs.
  774. * Just wait until they complete normally or their
  775. * time slot expires.
  776. */
  777. } else {
  778. qh = (struct ehci_qh *) urb->hcpriv;
  779. qh->unlink_reason |= QH_UNLINK_REQUESTED;
  780. switch (qh->qh_state) {
  781. case QH_STATE_LINKED:
  782. if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)
  783. start_unlink_intr(ehci, qh);
  784. else
  785. start_unlink_async(ehci, qh);
  786. break;
  787. case QH_STATE_COMPLETING:
  788. qh->dequeue_during_giveback = 1;
  789. break;
  790. case QH_STATE_UNLINK:
  791. case QH_STATE_UNLINK_WAIT:
  792. /* already started */
  793. break;
  794. case QH_STATE_IDLE:
  795. /* QH might be waiting for a Clear-TT-Buffer */
  796. qh_completions(ehci, qh);
  797. break;
  798. }
  799. }
  800. done:
  801. spin_unlock_irqrestore (&ehci->lock, flags);
  802. return rc;
  803. }
  804. /*-------------------------------------------------------------------------*/
  805. // bulk qh holds the data toggle
  806. static void
  807. ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  808. {
  809. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  810. unsigned long flags;
  811. struct ehci_qh *qh;
  812. /* ASSERT: any requests/urbs are being unlinked */
  813. /* ASSERT: nobody can be submitting urbs for this any more */
  814. rescan:
  815. spin_lock_irqsave (&ehci->lock, flags);
  816. qh = ep->hcpriv;
  817. if (!qh)
  818. goto done;
  819. /* endpoints can be iso streams. for now, we don't
  820. * accelerate iso completions ... so spin a while.
  821. */
  822. if (qh->hw == NULL) {
  823. struct ehci_iso_stream *stream = ep->hcpriv;
  824. if (!list_empty(&stream->td_list))
  825. goto idle_timeout;
  826. /* BUG_ON(!list_empty(&stream->free_list)); */
  827. reserve_release_iso_bandwidth(ehci, stream, -1);
  828. kfree(stream);
  829. goto done;
  830. }
  831. qh->unlink_reason |= QH_UNLINK_REQUESTED;
  832. switch (qh->qh_state) {
  833. case QH_STATE_LINKED:
  834. if (list_empty(&qh->qtd_list))
  835. qh->unlink_reason |= QH_UNLINK_QUEUE_EMPTY;
  836. else
  837. WARN_ON(1);
  838. if (usb_endpoint_type(&ep->desc) != USB_ENDPOINT_XFER_INT)
  839. start_unlink_async(ehci, qh);
  840. else
  841. start_unlink_intr(ehci, qh);
  842. /* FALL THROUGH */
  843. case QH_STATE_COMPLETING: /* already in unlinking */
  844. case QH_STATE_UNLINK: /* wait for hw to finish? */
  845. case QH_STATE_UNLINK_WAIT:
  846. idle_timeout:
  847. spin_unlock_irqrestore (&ehci->lock, flags);
  848. schedule_timeout_uninterruptible(1);
  849. goto rescan;
  850. case QH_STATE_IDLE: /* fully unlinked */
  851. if (qh->clearing_tt)
  852. goto idle_timeout;
  853. if (list_empty (&qh->qtd_list)) {
  854. if (qh->ps.bw_uperiod)
  855. reserve_release_intr_bandwidth(ehci, qh, -1);
  856. qh_destroy(ehci, qh);
  857. break;
  858. }
  859. /* fall through */
  860. default:
  861. /* caller was supposed to have unlinked any requests;
  862. * that's not our job. just leak this memory.
  863. */
  864. ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
  865. qh, ep->desc.bEndpointAddress, qh->qh_state,
  866. list_empty (&qh->qtd_list) ? "" : "(has tds)");
  867. break;
  868. }
  869. done:
  870. ep->hcpriv = NULL;
  871. spin_unlock_irqrestore (&ehci->lock, flags);
  872. }
  873. static void
  874. ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  875. {
  876. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  877. struct ehci_qh *qh;
  878. int eptype = usb_endpoint_type(&ep->desc);
  879. int epnum = usb_endpoint_num(&ep->desc);
  880. int is_out = usb_endpoint_dir_out(&ep->desc);
  881. unsigned long flags;
  882. if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
  883. return;
  884. spin_lock_irqsave(&ehci->lock, flags);
  885. qh = ep->hcpriv;
  886. /* For Bulk and Interrupt endpoints we maintain the toggle state
  887. * in the hardware; the toggle bits in udev aren't used at all.
  888. * When an endpoint is reset by usb_clear_halt() we must reset
  889. * the toggle bit in the QH.
  890. */
  891. if (qh) {
  892. if (!list_empty(&qh->qtd_list)) {
  893. WARN_ONCE(1, "clear_halt for a busy endpoint\n");
  894. } else {
  895. /* The toggle value in the QH can't be updated
  896. * while the QH is active. Unlink it now;
  897. * re-linking will call qh_refresh().
  898. */
  899. usb_settoggle(qh->ps.udev, epnum, is_out, 0);
  900. qh->unlink_reason |= QH_UNLINK_REQUESTED;
  901. if (eptype == USB_ENDPOINT_XFER_BULK)
  902. start_unlink_async(ehci, qh);
  903. else
  904. start_unlink_intr(ehci, qh);
  905. }
  906. }
  907. spin_unlock_irqrestore(&ehci->lock, flags);
  908. }
  909. static int ehci_get_frame (struct usb_hcd *hcd)
  910. {
  911. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  912. return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
  913. }
  914. /*-------------------------------------------------------------------------*/
  915. /* Device addition and removal */
  916. static void ehci_remove_device(struct usb_hcd *hcd, struct usb_device *udev)
  917. {
  918. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  919. spin_lock_irq(&ehci->lock);
  920. drop_tt(udev);
  921. spin_unlock_irq(&ehci->lock);
  922. }
  923. /*-------------------------------------------------------------------------*/
  924. #ifdef CONFIG_PM
  925. /* suspend/resume, section 4.3 */
  926. /* These routines handle the generic parts of controller suspend/resume */
  927. int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  928. {
  929. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  930. if (time_before(jiffies, ehci->next_statechange))
  931. msleep(10);
  932. /*
  933. * Root hub was already suspended. Disable IRQ emission and
  934. * mark HW unaccessible. The PM and USB cores make sure that
  935. * the root hub is either suspended or stopped.
  936. */
  937. ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
  938. spin_lock_irq(&ehci->lock);
  939. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  940. (void) ehci_readl(ehci, &ehci->regs->intr_enable);
  941. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  942. spin_unlock_irq(&ehci->lock);
  943. synchronize_irq(hcd->irq);
  944. /* Check for race with a wakeup request */
  945. if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
  946. ehci_resume(hcd, false);
  947. return -EBUSY;
  948. }
  949. return 0;
  950. }
  951. EXPORT_SYMBOL_GPL(ehci_suspend);
  952. /* Returns 0 if power was preserved, 1 if power was lost */
  953. int ehci_resume(struct usb_hcd *hcd, bool force_reset)
  954. {
  955. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  956. if (time_before(jiffies, ehci->next_statechange))
  957. msleep(100);
  958. /* Mark hardware accessible again as we are back to full power by now */
  959. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  960. if (ehci->shutdown)
  961. return 0; /* Controller is dead */
  962. /*
  963. * If CF is still set and reset isn't forced
  964. * then we maintained suspend power.
  965. * Just undo the effect of ehci_suspend().
  966. */
  967. if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
  968. !force_reset) {
  969. int mask = INTR_MASK;
  970. ehci_prepare_ports_for_controller_resume(ehci);
  971. spin_lock_irq(&ehci->lock);
  972. if (ehci->shutdown)
  973. goto skip;
  974. if (!hcd->self.root_hub->do_remote_wakeup)
  975. mask &= ~STS_PCD;
  976. ehci_writel(ehci, mask, &ehci->regs->intr_enable);
  977. ehci_readl(ehci, &ehci->regs->intr_enable);
  978. skip:
  979. spin_unlock_irq(&ehci->lock);
  980. return 0;
  981. }
  982. /*
  983. * Else reset, to cope with power loss or resume from hibernation
  984. * having let the firmware kick in during reboot.
  985. */
  986. usb_root_hub_lost_power(hcd->self.root_hub);
  987. (void) ehci_halt(ehci);
  988. (void) ehci_reset(ehci);
  989. spin_lock_irq(&ehci->lock);
  990. if (ehci->shutdown)
  991. goto skip;
  992. ehci_writel(ehci, ehci->command, &ehci->regs->command);
  993. ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
  994. ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
  995. ehci->rh_state = EHCI_RH_SUSPENDED;
  996. spin_unlock_irq(&ehci->lock);
  997. return 1;
  998. }
  999. EXPORT_SYMBOL_GPL(ehci_resume);
  1000. #endif
  1001. /*-------------------------------------------------------------------------*/
  1002. /*
  1003. * Generic structure: This gets copied for platform drivers so that
  1004. * individual entries can be overridden as needed.
  1005. */
  1006. static const struct hc_driver ehci_hc_driver = {
  1007. .description = hcd_name,
  1008. .product_desc = "EHCI Host Controller",
  1009. .hcd_priv_size = sizeof(struct ehci_hcd),
  1010. /*
  1011. * generic hardware linkage
  1012. */
  1013. .irq = ehci_irq,
  1014. .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
  1015. /*
  1016. * basic lifecycle operations
  1017. */
  1018. .reset = ehci_setup,
  1019. .start = ehci_run,
  1020. .stop = ehci_stop,
  1021. .shutdown = ehci_shutdown,
  1022. /*
  1023. * managing i/o requests and associated device resources
  1024. */
  1025. .urb_enqueue = ehci_urb_enqueue,
  1026. .urb_dequeue = ehci_urb_dequeue,
  1027. .endpoint_disable = ehci_endpoint_disable,
  1028. .endpoint_reset = ehci_endpoint_reset,
  1029. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  1030. /*
  1031. * scheduling support
  1032. */
  1033. .get_frame_number = ehci_get_frame,
  1034. /*
  1035. * root hub support
  1036. */
  1037. .hub_status_data = ehci_hub_status_data,
  1038. .hub_control = ehci_hub_control,
  1039. .bus_suspend = ehci_bus_suspend,
  1040. .bus_resume = ehci_bus_resume,
  1041. .relinquish_port = ehci_relinquish_port,
  1042. .port_handed_over = ehci_port_handed_over,
  1043. .get_resuming_ports = ehci_get_resuming_ports,
  1044. /*
  1045. * device support
  1046. */
  1047. .free_dev = ehci_remove_device,
  1048. };
  1049. void ehci_init_driver(struct hc_driver *drv,
  1050. const struct ehci_driver_overrides *over)
  1051. {
  1052. /* Copy the generic table to drv and then apply the overrides */
  1053. *drv = ehci_hc_driver;
  1054. if (over) {
  1055. drv->hcd_priv_size += over->extra_priv_size;
  1056. if (over->reset)
  1057. drv->reset = over->reset;
  1058. if (over->port_power)
  1059. drv->port_power = over->port_power;
  1060. }
  1061. }
  1062. EXPORT_SYMBOL_GPL(ehci_init_driver);
  1063. /*-------------------------------------------------------------------------*/
  1064. MODULE_DESCRIPTION(DRIVER_DESC);
  1065. MODULE_AUTHOR (DRIVER_AUTHOR);
  1066. MODULE_LICENSE ("GPL");
  1067. #ifdef CONFIG_USB_EHCI_SH
  1068. #include "ehci-sh.c"
  1069. #define PLATFORM_DRIVER ehci_hcd_sh_driver
  1070. #endif
  1071. #ifdef CONFIG_PPC_PS3
  1072. #include "ehci-ps3.c"
  1073. #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
  1074. #endif
  1075. #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
  1076. #include "ehci-ppc-of.c"
  1077. #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
  1078. #endif
  1079. #ifdef CONFIG_XPS_USB_HCD_XILINX
  1080. #include "ehci-xilinx-of.c"
  1081. #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
  1082. #endif
  1083. #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
  1084. #include "ehci-pmcmsp.c"
  1085. #define PLATFORM_DRIVER ehci_hcd_msp_driver
  1086. #endif
  1087. #ifdef CONFIG_SPARC_LEON
  1088. #include "ehci-grlib.c"
  1089. #define PLATFORM_DRIVER ehci_grlib_driver
  1090. #endif
  1091. #ifdef CONFIG_USB_EHCI_MV
  1092. #include "ehci-mv.c"
  1093. #define PLATFORM_DRIVER ehci_mv_driver
  1094. #endif
  1095. static int __init ehci_hcd_init(void)
  1096. {
  1097. int retval = 0;
  1098. if (usb_disabled())
  1099. return -ENODEV;
  1100. printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
  1101. set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
  1102. if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
  1103. test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
  1104. printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
  1105. " before uhci_hcd and ohci_hcd, not after\n");
  1106. pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd sitd %zd\n",
  1107. hcd_name,
  1108. sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
  1109. sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
  1110. #ifdef CONFIG_DYNAMIC_DEBUG
  1111. ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
  1112. #endif
  1113. #ifdef PLATFORM_DRIVER
  1114. retval = platform_driver_register(&PLATFORM_DRIVER);
  1115. if (retval < 0)
  1116. goto clean0;
  1117. #endif
  1118. #ifdef PS3_SYSTEM_BUS_DRIVER
  1119. retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
  1120. if (retval < 0)
  1121. goto clean2;
  1122. #endif
  1123. #ifdef OF_PLATFORM_DRIVER
  1124. retval = platform_driver_register(&OF_PLATFORM_DRIVER);
  1125. if (retval < 0)
  1126. goto clean3;
  1127. #endif
  1128. #ifdef XILINX_OF_PLATFORM_DRIVER
  1129. retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
  1130. if (retval < 0)
  1131. goto clean4;
  1132. #endif
  1133. return retval;
  1134. #ifdef XILINX_OF_PLATFORM_DRIVER
  1135. /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
  1136. clean4:
  1137. #endif
  1138. #ifdef OF_PLATFORM_DRIVER
  1139. platform_driver_unregister(&OF_PLATFORM_DRIVER);
  1140. clean3:
  1141. #endif
  1142. #ifdef PS3_SYSTEM_BUS_DRIVER
  1143. ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  1144. clean2:
  1145. #endif
  1146. #ifdef PLATFORM_DRIVER
  1147. platform_driver_unregister(&PLATFORM_DRIVER);
  1148. clean0:
  1149. #endif
  1150. #ifdef CONFIG_DYNAMIC_DEBUG
  1151. debugfs_remove(ehci_debug_root);
  1152. ehci_debug_root = NULL;
  1153. #endif
  1154. clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
  1155. return retval;
  1156. }
  1157. module_init(ehci_hcd_init);
  1158. static void __exit ehci_hcd_cleanup(void)
  1159. {
  1160. #ifdef XILINX_OF_PLATFORM_DRIVER
  1161. platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
  1162. #endif
  1163. #ifdef OF_PLATFORM_DRIVER
  1164. platform_driver_unregister(&OF_PLATFORM_DRIVER);
  1165. #endif
  1166. #ifdef PLATFORM_DRIVER
  1167. platform_driver_unregister(&PLATFORM_DRIVER);
  1168. #endif
  1169. #ifdef PS3_SYSTEM_BUS_DRIVER
  1170. ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  1171. #endif
  1172. #ifdef CONFIG_DYNAMIC_DEBUG
  1173. debugfs_remove(ehci_debug_root);
  1174. #endif
  1175. clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
  1176. }
  1177. module_exit(ehci_hcd_cleanup);