imx21-hcd.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB Host Controller Driver for IMX21
  4. *
  5. * Copyright (C) 2006 Loping Dog Embedded Systems
  6. * Copyright (C) 2009 Martin Fuzzey
  7. * Originally written by Jay Monkman <jtm@lopingdog.com>
  8. * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
  9. */
  10. /*
  11. * The i.MX21 USB hardware contains
  12. * * 32 transfer descriptors (called ETDs)
  13. * * 4Kb of Data memory
  14. *
  15. * The data memory is shared between the host and function controllers
  16. * (but this driver only supports the host controller)
  17. *
  18. * So setting up a transfer involves:
  19. * * Allocating a ETD
  20. * * Fill in ETD with appropriate information
  21. * * Allocating data memory (and putting the offset in the ETD)
  22. * * Activate the ETD
  23. * * Get interrupt when done.
  24. *
  25. * An ETD is assigned to each active endpoint.
  26. *
  27. * Low resource (ETD and Data memory) situations are handled differently for
  28. * isochronous and non insosynchronous transactions :
  29. *
  30. * Non ISOC transfers are queued if either ETDs or Data memory are unavailable
  31. *
  32. * ISOC transfers use 2 ETDs per endpoint to achieve double buffering.
  33. * They allocate both ETDs and Data memory during URB submission
  34. * (and fail if unavailable).
  35. */
  36. #include <linux/clk.h>
  37. #include <linux/io.h>
  38. #include <linux/kernel.h>
  39. #include <linux/list.h>
  40. #include <linux/platform_device.h>
  41. #include <linux/slab.h>
  42. #include <linux/usb.h>
  43. #include <linux/usb/hcd.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/module.h>
  46. #include "imx21-hcd.h"
  47. #ifdef CONFIG_DYNAMIC_DEBUG
  48. #define DEBUG
  49. #endif
  50. #ifdef DEBUG
  51. #define DEBUG_LOG_FRAME(imx21, etd, event) \
  52. (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
  53. #else
  54. #define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
  55. #endif
  56. static const char hcd_name[] = "imx21-hcd";
  57. static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd)
  58. {
  59. return (struct imx21 *)hcd->hcd_priv;
  60. }
  61. /* =========================================== */
  62. /* Hardware access helpers */
  63. /* =========================================== */
  64. static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask)
  65. {
  66. void __iomem *reg = imx21->regs + offset;
  67. writel(readl(reg) | mask, reg);
  68. }
  69. static inline void clear_register_bits(struct imx21 *imx21,
  70. u32 offset, u32 mask)
  71. {
  72. void __iomem *reg = imx21->regs + offset;
  73. writel(readl(reg) & ~mask, reg);
  74. }
  75. static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
  76. {
  77. void __iomem *reg = imx21->regs + offset;
  78. if (readl(reg) & mask)
  79. writel(mask, reg);
  80. }
  81. static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
  82. {
  83. void __iomem *reg = imx21->regs + offset;
  84. if (!(readl(reg) & mask))
  85. writel(mask, reg);
  86. }
  87. static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value)
  88. {
  89. writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword));
  90. }
  91. static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword)
  92. {
  93. return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword));
  94. }
  95. static inline int wrap_frame(int counter)
  96. {
  97. return counter & 0xFFFF;
  98. }
  99. static inline int frame_after(int frame, int after)
  100. {
  101. /* handle wrapping like jiffies time_afer */
  102. return (s16)((s16)after - (s16)frame) < 0;
  103. }
  104. static int imx21_hc_get_frame(struct usb_hcd *hcd)
  105. {
  106. struct imx21 *imx21 = hcd_to_imx21(hcd);
  107. return wrap_frame(readl(imx21->regs + USBH_FRMNUB));
  108. }
  109. static inline bool unsuitable_for_dma(dma_addr_t addr)
  110. {
  111. return (addr & 3) != 0;
  112. }
  113. #include "imx21-dbg.c"
  114. static void nonisoc_urb_completed_for_etd(
  115. struct imx21 *imx21, struct etd_priv *etd, int status);
  116. static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
  117. static void free_dmem(struct imx21 *imx21, struct etd_priv *etd);
  118. /* =========================================== */
  119. /* ETD management */
  120. /* =========================================== */
  121. static int alloc_etd(struct imx21 *imx21)
  122. {
  123. int i;
  124. struct etd_priv *etd = imx21->etd;
  125. for (i = 0; i < USB_NUM_ETD; i++, etd++) {
  126. if (etd->alloc == 0) {
  127. memset(etd, 0, sizeof(imx21->etd[0]));
  128. etd->alloc = 1;
  129. debug_etd_allocated(imx21);
  130. return i;
  131. }
  132. }
  133. return -1;
  134. }
  135. static void disactivate_etd(struct imx21 *imx21, int num)
  136. {
  137. int etd_mask = (1 << num);
  138. struct etd_priv *etd = &imx21->etd[num];
  139. writel(etd_mask, imx21->regs + USBH_ETDENCLR);
  140. clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
  141. writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR);
  142. clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
  143. etd->active_count = 0;
  144. DEBUG_LOG_FRAME(imx21, etd, disactivated);
  145. }
  146. static void reset_etd(struct imx21 *imx21, int num)
  147. {
  148. struct etd_priv *etd = imx21->etd + num;
  149. int i;
  150. disactivate_etd(imx21, num);
  151. for (i = 0; i < 4; i++)
  152. etd_writel(imx21, num, i, 0);
  153. etd->urb = NULL;
  154. etd->ep = NULL;
  155. etd->td = NULL;
  156. etd->bounce_buffer = NULL;
  157. }
  158. static void free_etd(struct imx21 *imx21, int num)
  159. {
  160. if (num < 0)
  161. return;
  162. if (num >= USB_NUM_ETD) {
  163. dev_err(imx21->dev, "BAD etd=%d!\n", num);
  164. return;
  165. }
  166. if (imx21->etd[num].alloc == 0) {
  167. dev_err(imx21->dev, "ETD %d already free!\n", num);
  168. return;
  169. }
  170. debug_etd_freed(imx21);
  171. reset_etd(imx21, num);
  172. memset(&imx21->etd[num], 0, sizeof(imx21->etd[0]));
  173. }
  174. static void setup_etd_dword0(struct imx21 *imx21,
  175. int etd_num, struct urb *urb, u8 dir, u16 maxpacket)
  176. {
  177. etd_writel(imx21, etd_num, 0,
  178. ((u32) usb_pipedevice(urb->pipe)) << DW0_ADDRESS |
  179. ((u32) usb_pipeendpoint(urb->pipe) << DW0_ENDPNT) |
  180. ((u32) dir << DW0_DIRECT) |
  181. ((u32) ((urb->dev->speed == USB_SPEED_LOW) ?
  182. 1 : 0) << DW0_SPEED) |
  183. ((u32) fmt_urb_to_etd[usb_pipetype(urb->pipe)] << DW0_FORMAT) |
  184. ((u32) maxpacket << DW0_MAXPKTSIZ));
  185. }
  186. /**
  187. * Copy buffer to data controller data memory.
  188. * We cannot use memcpy_toio() because the hardware requires 32bit writes
  189. */
  190. static void copy_to_dmem(
  191. struct imx21 *imx21, int dmem_offset, void *src, int count)
  192. {
  193. void __iomem *dmem = imx21->regs + USBOTG_DMEM + dmem_offset;
  194. u32 word = 0;
  195. u8 *p = src;
  196. int byte = 0;
  197. int i;
  198. for (i = 0; i < count; i++) {
  199. byte = i % 4;
  200. word += (*p++ << (byte * 8));
  201. if (byte == 3) {
  202. writel(word, dmem);
  203. dmem += 4;
  204. word = 0;
  205. }
  206. }
  207. if (count && byte != 3)
  208. writel(word, dmem);
  209. }
  210. static void activate_etd(struct imx21 *imx21, int etd_num, u8 dir)
  211. {
  212. u32 etd_mask = 1 << etd_num;
  213. struct etd_priv *etd = &imx21->etd[etd_num];
  214. if (etd->dma_handle && unsuitable_for_dma(etd->dma_handle)) {
  215. /* For non aligned isoc the condition below is always true */
  216. if (etd->len <= etd->dmem_size) {
  217. /* Fits into data memory, use PIO */
  218. if (dir != TD_DIR_IN) {
  219. copy_to_dmem(imx21,
  220. etd->dmem_offset,
  221. etd->cpu_buffer, etd->len);
  222. }
  223. etd->dma_handle = 0;
  224. } else {
  225. /* Too big for data memory, use bounce buffer */
  226. enum dma_data_direction dmadir;
  227. if (dir == TD_DIR_IN) {
  228. dmadir = DMA_FROM_DEVICE;
  229. etd->bounce_buffer = kmalloc(etd->len,
  230. GFP_ATOMIC);
  231. } else {
  232. dmadir = DMA_TO_DEVICE;
  233. etd->bounce_buffer = kmemdup(etd->cpu_buffer,
  234. etd->len,
  235. GFP_ATOMIC);
  236. }
  237. if (!etd->bounce_buffer) {
  238. dev_err(imx21->dev, "failed bounce alloc\n");
  239. goto err_bounce_alloc;
  240. }
  241. etd->dma_handle =
  242. dma_map_single(imx21->dev,
  243. etd->bounce_buffer,
  244. etd->len,
  245. dmadir);
  246. if (dma_mapping_error(imx21->dev, etd->dma_handle)) {
  247. dev_err(imx21->dev, "failed bounce map\n");
  248. goto err_bounce_map;
  249. }
  250. }
  251. }
  252. clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
  253. set_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
  254. clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
  255. clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
  256. if (etd->dma_handle) {
  257. set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask);
  258. clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask);
  259. clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask);
  260. writel(etd->dma_handle, imx21->regs + USB_ETDSMSA(etd_num));
  261. set_register_bits(imx21, USB_ETDDMAEN, etd_mask);
  262. } else {
  263. if (dir != TD_DIR_IN) {
  264. /* need to set for ZLP and PIO */
  265. set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
  266. set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
  267. }
  268. }
  269. DEBUG_LOG_FRAME(imx21, etd, activated);
  270. #ifdef DEBUG
  271. if (!etd->active_count) {
  272. int i;
  273. etd->activated_frame = readl(imx21->regs + USBH_FRMNUB);
  274. etd->disactivated_frame = -1;
  275. etd->last_int_frame = -1;
  276. etd->last_req_frame = -1;
  277. for (i = 0; i < 4; i++)
  278. etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i);
  279. }
  280. #endif
  281. etd->active_count = 1;
  282. writel(etd_mask, imx21->regs + USBH_ETDENSET);
  283. return;
  284. err_bounce_map:
  285. kfree(etd->bounce_buffer);
  286. err_bounce_alloc:
  287. free_dmem(imx21, etd);
  288. nonisoc_urb_completed_for_etd(imx21, etd, -ENOMEM);
  289. }
  290. /* =========================================== */
  291. /* Data memory management */
  292. /* =========================================== */
  293. static int alloc_dmem(struct imx21 *imx21, unsigned int size,
  294. struct usb_host_endpoint *ep)
  295. {
  296. unsigned int offset = 0;
  297. struct imx21_dmem_area *area;
  298. struct imx21_dmem_area *tmp;
  299. size += (~size + 1) & 0x3; /* Round to 4 byte multiple */
  300. if (size > DMEM_SIZE) {
  301. dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n",
  302. size, DMEM_SIZE);
  303. return -EINVAL;
  304. }
  305. list_for_each_entry(tmp, &imx21->dmem_list, list) {
  306. if ((size + offset) < offset)
  307. goto fail;
  308. if ((size + offset) <= tmp->offset)
  309. break;
  310. offset = tmp->size + tmp->offset;
  311. if ((offset + size) > DMEM_SIZE)
  312. goto fail;
  313. }
  314. area = kmalloc(sizeof(struct imx21_dmem_area), GFP_ATOMIC);
  315. if (area == NULL)
  316. return -ENOMEM;
  317. area->ep = ep;
  318. area->offset = offset;
  319. area->size = size;
  320. list_add_tail(&area->list, &tmp->list);
  321. debug_dmem_allocated(imx21, size);
  322. return offset;
  323. fail:
  324. return -ENOMEM;
  325. }
  326. /* Memory now available for a queued ETD - activate it */
  327. static void activate_queued_etd(struct imx21 *imx21,
  328. struct etd_priv *etd, u32 dmem_offset)
  329. {
  330. struct urb_priv *urb_priv = etd->urb->hcpriv;
  331. int etd_num = etd - &imx21->etd[0];
  332. u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD;
  333. u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03;
  334. dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n",
  335. etd_num);
  336. etd_writel(imx21, etd_num, 1,
  337. ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset);
  338. etd->dmem_offset = dmem_offset;
  339. urb_priv->active = 1;
  340. activate_etd(imx21, etd_num, dir);
  341. }
  342. static void free_dmem(struct imx21 *imx21, struct etd_priv *etd)
  343. {
  344. struct imx21_dmem_area *area;
  345. struct etd_priv *tmp;
  346. int found = 0;
  347. int offset;
  348. if (!etd->dmem_size)
  349. return;
  350. etd->dmem_size = 0;
  351. offset = etd->dmem_offset;
  352. list_for_each_entry(area, &imx21->dmem_list, list) {
  353. if (area->offset == offset) {
  354. debug_dmem_freed(imx21, area->size);
  355. list_del(&area->list);
  356. kfree(area);
  357. found = 1;
  358. break;
  359. }
  360. }
  361. if (!found) {
  362. dev_err(imx21->dev,
  363. "Trying to free unallocated DMEM %d\n", offset);
  364. return;
  365. }
  366. /* Try again to allocate memory for anything we've queued */
  367. list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) {
  368. offset = alloc_dmem(imx21, etd->dmem_size, etd->ep);
  369. if (offset >= 0) {
  370. list_del(&etd->queue);
  371. activate_queued_etd(imx21, etd, (u32)offset);
  372. }
  373. }
  374. }
  375. static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep)
  376. {
  377. struct imx21_dmem_area *area, *tmp;
  378. list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) {
  379. if (area->ep == ep) {
  380. dev_err(imx21->dev,
  381. "Active DMEM %d for disabled ep=%p\n",
  382. area->offset, ep);
  383. list_del(&area->list);
  384. kfree(area);
  385. }
  386. }
  387. }
  388. /* =========================================== */
  389. /* End handling */
  390. /* =========================================== */
  391. /* Endpoint now idle - release its ETD(s) or assign to queued request */
  392. static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv)
  393. {
  394. int i;
  395. for (i = 0; i < NUM_ISO_ETDS; i++) {
  396. int etd_num = ep_priv->etd[i];
  397. struct etd_priv *etd;
  398. if (etd_num < 0)
  399. continue;
  400. etd = &imx21->etd[etd_num];
  401. ep_priv->etd[i] = -1;
  402. free_dmem(imx21, etd); /* for isoc */
  403. if (list_empty(&imx21->queue_for_etd)) {
  404. free_etd(imx21, etd_num);
  405. continue;
  406. }
  407. dev_dbg(imx21->dev,
  408. "assigning idle etd %d for queued request\n", etd_num);
  409. ep_priv = list_first_entry(&imx21->queue_for_etd,
  410. struct ep_priv, queue);
  411. list_del(&ep_priv->queue);
  412. reset_etd(imx21, etd_num);
  413. ep_priv->waiting_etd = 0;
  414. ep_priv->etd[i] = etd_num;
  415. if (list_empty(&ep_priv->ep->urb_list)) {
  416. dev_err(imx21->dev, "No urb for queued ep!\n");
  417. continue;
  418. }
  419. schedule_nonisoc_etd(imx21, list_first_entry(
  420. &ep_priv->ep->urb_list, struct urb, urb_list));
  421. }
  422. }
  423. static void urb_done(struct usb_hcd *hcd, struct urb *urb, int status)
  424. __releases(imx21->lock)
  425. __acquires(imx21->lock)
  426. {
  427. struct imx21 *imx21 = hcd_to_imx21(hcd);
  428. struct ep_priv *ep_priv = urb->ep->hcpriv;
  429. struct urb_priv *urb_priv = urb->hcpriv;
  430. debug_urb_completed(imx21, urb, status);
  431. dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
  432. kfree(urb_priv->isoc_td);
  433. kfree(urb->hcpriv);
  434. urb->hcpriv = NULL;
  435. usb_hcd_unlink_urb_from_ep(hcd, urb);
  436. spin_unlock(&imx21->lock);
  437. usb_hcd_giveback_urb(hcd, urb, status);
  438. spin_lock(&imx21->lock);
  439. if (list_empty(&ep_priv->ep->urb_list))
  440. ep_idle(imx21, ep_priv);
  441. }
  442. static void nonisoc_urb_completed_for_etd(
  443. struct imx21 *imx21, struct etd_priv *etd, int status)
  444. {
  445. struct usb_host_endpoint *ep = etd->ep;
  446. urb_done(imx21->hcd, etd->urb, status);
  447. etd->urb = NULL;
  448. if (!list_empty(&ep->urb_list)) {
  449. struct urb *urb = list_first_entry(
  450. &ep->urb_list, struct urb, urb_list);
  451. dev_vdbg(imx21->dev, "next URB %p\n", urb);
  452. schedule_nonisoc_etd(imx21, urb);
  453. }
  454. }
  455. /* =========================================== */
  456. /* ISOC Handling ... */
  457. /* =========================================== */
  458. static void schedule_isoc_etds(struct usb_hcd *hcd,
  459. struct usb_host_endpoint *ep)
  460. {
  461. struct imx21 *imx21 = hcd_to_imx21(hcd);
  462. struct ep_priv *ep_priv = ep->hcpriv;
  463. struct etd_priv *etd;
  464. struct urb_priv *urb_priv;
  465. struct td *td;
  466. int etd_num;
  467. int i;
  468. int cur_frame;
  469. u8 dir;
  470. for (i = 0; i < NUM_ISO_ETDS; i++) {
  471. too_late:
  472. if (list_empty(&ep_priv->td_list))
  473. break;
  474. etd_num = ep_priv->etd[i];
  475. if (etd_num < 0)
  476. break;
  477. etd = &imx21->etd[etd_num];
  478. if (etd->urb)
  479. continue;
  480. td = list_entry(ep_priv->td_list.next, struct td, list);
  481. list_del(&td->list);
  482. urb_priv = td->urb->hcpriv;
  483. cur_frame = imx21_hc_get_frame(hcd);
  484. if (frame_after(cur_frame, td->frame)) {
  485. dev_dbg(imx21->dev, "isoc too late frame %d > %d\n",
  486. cur_frame, td->frame);
  487. urb_priv->isoc_status = -EXDEV;
  488. td->urb->iso_frame_desc[
  489. td->isoc_index].actual_length = 0;
  490. td->urb->iso_frame_desc[td->isoc_index].status = -EXDEV;
  491. if (--urb_priv->isoc_remaining == 0)
  492. urb_done(hcd, td->urb, urb_priv->isoc_status);
  493. goto too_late;
  494. }
  495. urb_priv->active = 1;
  496. etd->td = td;
  497. etd->ep = td->ep;
  498. etd->urb = td->urb;
  499. etd->len = td->len;
  500. etd->dma_handle = td->dma_handle;
  501. etd->cpu_buffer = td->cpu_buffer;
  502. debug_isoc_submitted(imx21, cur_frame, td);
  503. dir = usb_pipeout(td->urb->pipe) ? TD_DIR_OUT : TD_DIR_IN;
  504. setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size);
  505. etd_writel(imx21, etd_num, 1, etd->dmem_offset);
  506. etd_writel(imx21, etd_num, 2,
  507. (TD_NOTACCESSED << DW2_COMPCODE) |
  508. ((td->frame & 0xFFFF) << DW2_STARTFRM));
  509. etd_writel(imx21, etd_num, 3,
  510. (TD_NOTACCESSED << DW3_COMPCODE0) |
  511. (td->len << DW3_PKTLEN0));
  512. activate_etd(imx21, etd_num, dir);
  513. }
  514. }
  515. static void isoc_etd_done(struct usb_hcd *hcd, int etd_num)
  516. {
  517. struct imx21 *imx21 = hcd_to_imx21(hcd);
  518. int etd_mask = 1 << etd_num;
  519. struct etd_priv *etd = imx21->etd + etd_num;
  520. struct urb *urb = etd->urb;
  521. struct urb_priv *urb_priv = urb->hcpriv;
  522. struct td *td = etd->td;
  523. struct usb_host_endpoint *ep = etd->ep;
  524. int isoc_index = td->isoc_index;
  525. unsigned int pipe = urb->pipe;
  526. int dir_in = usb_pipein(pipe);
  527. int cc;
  528. int bytes_xfrd;
  529. disactivate_etd(imx21, etd_num);
  530. cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf;
  531. bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff;
  532. /* Input doesn't always fill the buffer, don't generate an error
  533. * when this happens.
  534. */
  535. if (dir_in && (cc == TD_DATAUNDERRUN))
  536. cc = TD_CC_NOERROR;
  537. if (cc == TD_NOTACCESSED)
  538. bytes_xfrd = 0;
  539. debug_isoc_completed(imx21,
  540. imx21_hc_get_frame(hcd), td, cc, bytes_xfrd);
  541. if (cc) {
  542. urb_priv->isoc_status = -EXDEV;
  543. dev_dbg(imx21->dev,
  544. "bad iso cc=0x%X frame=%d sched frame=%d "
  545. "cnt=%d len=%d urb=%p etd=%d index=%d\n",
  546. cc, imx21_hc_get_frame(hcd), td->frame,
  547. bytes_xfrd, td->len, urb, etd_num, isoc_index);
  548. }
  549. if (dir_in) {
  550. clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
  551. if (!etd->dma_handle)
  552. memcpy_fromio(etd->cpu_buffer,
  553. imx21->regs + USBOTG_DMEM + etd->dmem_offset,
  554. bytes_xfrd);
  555. }
  556. urb->actual_length += bytes_xfrd;
  557. urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd;
  558. urb->iso_frame_desc[isoc_index].status = cc_to_error[cc];
  559. etd->td = NULL;
  560. etd->urb = NULL;
  561. etd->ep = NULL;
  562. if (--urb_priv->isoc_remaining == 0)
  563. urb_done(hcd, urb, urb_priv->isoc_status);
  564. schedule_isoc_etds(hcd, ep);
  565. }
  566. static struct ep_priv *alloc_isoc_ep(
  567. struct imx21 *imx21, struct usb_host_endpoint *ep)
  568. {
  569. struct ep_priv *ep_priv;
  570. int i;
  571. ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
  572. if (!ep_priv)
  573. return NULL;
  574. for (i = 0; i < NUM_ISO_ETDS; i++)
  575. ep_priv->etd[i] = -1;
  576. INIT_LIST_HEAD(&ep_priv->td_list);
  577. ep_priv->ep = ep;
  578. ep->hcpriv = ep_priv;
  579. return ep_priv;
  580. }
  581. static int alloc_isoc_etds(struct imx21 *imx21, struct ep_priv *ep_priv)
  582. {
  583. int i, j;
  584. int etd_num;
  585. /* Allocate the ETDs if required */
  586. for (i = 0; i < NUM_ISO_ETDS; i++) {
  587. if (ep_priv->etd[i] < 0) {
  588. etd_num = alloc_etd(imx21);
  589. if (etd_num < 0)
  590. goto alloc_etd_failed;
  591. ep_priv->etd[i] = etd_num;
  592. imx21->etd[etd_num].ep = ep_priv->ep;
  593. }
  594. }
  595. return 0;
  596. alloc_etd_failed:
  597. dev_err(imx21->dev, "isoc: Couldn't allocate etd\n");
  598. for (j = 0; j < i; j++) {
  599. free_etd(imx21, ep_priv->etd[j]);
  600. ep_priv->etd[j] = -1;
  601. }
  602. return -ENOMEM;
  603. }
  604. static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd,
  605. struct usb_host_endpoint *ep,
  606. struct urb *urb, gfp_t mem_flags)
  607. {
  608. struct imx21 *imx21 = hcd_to_imx21(hcd);
  609. struct urb_priv *urb_priv;
  610. unsigned long flags;
  611. struct ep_priv *ep_priv;
  612. struct td *td = NULL;
  613. int i;
  614. int ret;
  615. int cur_frame;
  616. u16 maxpacket;
  617. urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
  618. if (urb_priv == NULL)
  619. return -ENOMEM;
  620. urb_priv->isoc_td = kcalloc(urb->number_of_packets, sizeof(struct td),
  621. mem_flags);
  622. if (urb_priv->isoc_td == NULL) {
  623. ret = -ENOMEM;
  624. goto alloc_td_failed;
  625. }
  626. spin_lock_irqsave(&imx21->lock, flags);
  627. if (ep->hcpriv == NULL) {
  628. ep_priv = alloc_isoc_ep(imx21, ep);
  629. if (ep_priv == NULL) {
  630. ret = -ENOMEM;
  631. goto alloc_ep_failed;
  632. }
  633. } else {
  634. ep_priv = ep->hcpriv;
  635. }
  636. ret = alloc_isoc_etds(imx21, ep_priv);
  637. if (ret)
  638. goto alloc_etd_failed;
  639. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  640. if (ret)
  641. goto link_failed;
  642. urb->status = -EINPROGRESS;
  643. urb->actual_length = 0;
  644. urb->error_count = 0;
  645. urb->hcpriv = urb_priv;
  646. urb_priv->ep = ep;
  647. /* allocate data memory for largest packets if not already done */
  648. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  649. for (i = 0; i < NUM_ISO_ETDS; i++) {
  650. struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]];
  651. if (etd->dmem_size > 0 && etd->dmem_size < maxpacket) {
  652. /* not sure if this can really occur.... */
  653. dev_err(imx21->dev, "increasing isoc buffer %d->%d\n",
  654. etd->dmem_size, maxpacket);
  655. ret = -EMSGSIZE;
  656. goto alloc_dmem_failed;
  657. }
  658. if (etd->dmem_size == 0) {
  659. etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep);
  660. if (etd->dmem_offset < 0) {
  661. dev_dbg(imx21->dev, "failed alloc isoc dmem\n");
  662. ret = -EAGAIN;
  663. goto alloc_dmem_failed;
  664. }
  665. etd->dmem_size = maxpacket;
  666. }
  667. }
  668. /* calculate frame */
  669. cur_frame = imx21_hc_get_frame(hcd);
  670. i = 0;
  671. if (list_empty(&ep_priv->td_list)) {
  672. urb->start_frame = wrap_frame(cur_frame + 5);
  673. } else {
  674. urb->start_frame = wrap_frame(list_entry(ep_priv->td_list.prev,
  675. struct td, list)->frame + urb->interval);
  676. if (frame_after(cur_frame, urb->start_frame)) {
  677. dev_dbg(imx21->dev,
  678. "enqueue: adjusting iso start %d (cur=%d) asap=%d\n",
  679. urb->start_frame, cur_frame,
  680. (urb->transfer_flags & URB_ISO_ASAP) != 0);
  681. i = DIV_ROUND_UP(wrap_frame(
  682. cur_frame - urb->start_frame),
  683. urb->interval);
  684. /* Treat underruns as if URB_ISO_ASAP was set */
  685. if ((urb->transfer_flags & URB_ISO_ASAP) ||
  686. i >= urb->number_of_packets) {
  687. urb->start_frame = wrap_frame(urb->start_frame
  688. + i * urb->interval);
  689. i = 0;
  690. }
  691. }
  692. }
  693. /* set up transfers */
  694. urb_priv->isoc_remaining = urb->number_of_packets - i;
  695. td = urb_priv->isoc_td;
  696. for (; i < urb->number_of_packets; i++, td++) {
  697. unsigned int offset = urb->iso_frame_desc[i].offset;
  698. td->ep = ep;
  699. td->urb = urb;
  700. td->len = urb->iso_frame_desc[i].length;
  701. td->isoc_index = i;
  702. td->frame = wrap_frame(urb->start_frame + urb->interval * i);
  703. td->dma_handle = urb->transfer_dma + offset;
  704. td->cpu_buffer = urb->transfer_buffer + offset;
  705. list_add_tail(&td->list, &ep_priv->td_list);
  706. }
  707. dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n",
  708. urb->number_of_packets, urb->start_frame, td->frame);
  709. debug_urb_submitted(imx21, urb);
  710. schedule_isoc_etds(hcd, ep);
  711. spin_unlock_irqrestore(&imx21->lock, flags);
  712. return 0;
  713. alloc_dmem_failed:
  714. usb_hcd_unlink_urb_from_ep(hcd, urb);
  715. link_failed:
  716. alloc_etd_failed:
  717. alloc_ep_failed:
  718. spin_unlock_irqrestore(&imx21->lock, flags);
  719. kfree(urb_priv->isoc_td);
  720. alloc_td_failed:
  721. kfree(urb_priv);
  722. return ret;
  723. }
  724. static void dequeue_isoc_urb(struct imx21 *imx21,
  725. struct urb *urb, struct ep_priv *ep_priv)
  726. {
  727. struct urb_priv *urb_priv = urb->hcpriv;
  728. struct td *td, *tmp;
  729. int i;
  730. if (urb_priv->active) {
  731. for (i = 0; i < NUM_ISO_ETDS; i++) {
  732. int etd_num = ep_priv->etd[i];
  733. if (etd_num != -1 && imx21->etd[etd_num].urb == urb) {
  734. struct etd_priv *etd = imx21->etd + etd_num;
  735. reset_etd(imx21, etd_num);
  736. free_dmem(imx21, etd);
  737. }
  738. }
  739. }
  740. list_for_each_entry_safe(td, tmp, &ep_priv->td_list, list) {
  741. if (td->urb == urb) {
  742. dev_vdbg(imx21->dev, "removing td %p\n", td);
  743. list_del(&td->list);
  744. }
  745. }
  746. }
  747. /* =========================================== */
  748. /* NON ISOC Handling ... */
  749. /* =========================================== */
  750. static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
  751. {
  752. unsigned int pipe = urb->pipe;
  753. struct urb_priv *urb_priv = urb->hcpriv;
  754. struct ep_priv *ep_priv = urb_priv->ep->hcpriv;
  755. int state = urb_priv->state;
  756. int etd_num = ep_priv->etd[0];
  757. struct etd_priv *etd;
  758. u32 count;
  759. u16 etd_buf_size;
  760. u16 maxpacket;
  761. u8 dir;
  762. u8 bufround;
  763. u8 datatoggle;
  764. u8 interval = 0;
  765. u8 relpolpos = 0;
  766. if (etd_num < 0) {
  767. dev_err(imx21->dev, "No valid ETD\n");
  768. return;
  769. }
  770. if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num))
  771. dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num);
  772. etd = &imx21->etd[etd_num];
  773. maxpacket = usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe));
  774. if (!maxpacket)
  775. maxpacket = 8;
  776. if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) {
  777. if (state == US_CTRL_SETUP) {
  778. dir = TD_DIR_SETUP;
  779. if (unsuitable_for_dma(urb->setup_dma))
  780. usb_hcd_unmap_urb_setup_for_dma(imx21->hcd,
  781. urb);
  782. etd->dma_handle = urb->setup_dma;
  783. etd->cpu_buffer = urb->setup_packet;
  784. bufround = 0;
  785. count = 8;
  786. datatoggle = TD_TOGGLE_DATA0;
  787. } else { /* US_CTRL_ACK */
  788. dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT;
  789. bufround = 0;
  790. count = 0;
  791. datatoggle = TD_TOGGLE_DATA1;
  792. }
  793. } else {
  794. dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN;
  795. bufround = (dir == TD_DIR_IN) ? 1 : 0;
  796. if (unsuitable_for_dma(urb->transfer_dma))
  797. usb_hcd_unmap_urb_for_dma(imx21->hcd, urb);
  798. etd->dma_handle = urb->transfer_dma;
  799. etd->cpu_buffer = urb->transfer_buffer;
  800. if (usb_pipebulk(pipe) && (state == US_BULK0))
  801. count = 0;
  802. else
  803. count = urb->transfer_buffer_length;
  804. if (usb_pipecontrol(pipe)) {
  805. datatoggle = TD_TOGGLE_DATA1;
  806. } else {
  807. if (usb_gettoggle(
  808. urb->dev,
  809. usb_pipeendpoint(urb->pipe),
  810. usb_pipeout(urb->pipe)))
  811. datatoggle = TD_TOGGLE_DATA1;
  812. else
  813. datatoggle = TD_TOGGLE_DATA0;
  814. }
  815. }
  816. etd->urb = urb;
  817. etd->ep = urb_priv->ep;
  818. etd->len = count;
  819. if (usb_pipeint(pipe)) {
  820. interval = urb->interval;
  821. relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff;
  822. }
  823. /* Write ETD to device memory */
  824. setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket);
  825. etd_writel(imx21, etd_num, 2,
  826. (u32) interval << DW2_POLINTERV |
  827. ((u32) relpolpos << DW2_RELPOLPOS) |
  828. ((u32) dir << DW2_DIRPID) |
  829. ((u32) bufround << DW2_BUFROUND) |
  830. ((u32) datatoggle << DW2_DATATOG) |
  831. ((u32) TD_NOTACCESSED << DW2_COMPCODE));
  832. /* DMA will always transfer buffer size even if TOBYCNT in DWORD3
  833. is smaller. Make sure we don't overrun the buffer!
  834. */
  835. if (count && count < maxpacket)
  836. etd_buf_size = count;
  837. else
  838. etd_buf_size = maxpacket;
  839. etd_writel(imx21, etd_num, 3,
  840. ((u32) (etd_buf_size - 1) << DW3_BUFSIZE) | (u32) count);
  841. if (!count)
  842. etd->dma_handle = 0;
  843. /* allocate x and y buffer space at once */
  844. etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket;
  845. etd->dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep);
  846. if (etd->dmem_offset < 0) {
  847. /* Setup everything we can in HW and update when we get DMEM */
  848. etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16);
  849. dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num);
  850. debug_urb_queued_for_dmem(imx21, urb);
  851. list_add_tail(&etd->queue, &imx21->queue_for_dmem);
  852. return;
  853. }
  854. etd_writel(imx21, etd_num, 1,
  855. (((u32) etd->dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) |
  856. (u32) etd->dmem_offset);
  857. urb_priv->active = 1;
  858. /* enable the ETD to kick off transfer */
  859. dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n",
  860. etd_num, count, dir != TD_DIR_IN ? "out" : "in");
  861. activate_etd(imx21, etd_num, dir);
  862. }
  863. static void nonisoc_etd_done(struct usb_hcd *hcd, int etd_num)
  864. {
  865. struct imx21 *imx21 = hcd_to_imx21(hcd);
  866. struct etd_priv *etd = &imx21->etd[etd_num];
  867. struct urb *urb = etd->urb;
  868. u32 etd_mask = 1 << etd_num;
  869. struct urb_priv *urb_priv = urb->hcpriv;
  870. int dir;
  871. int cc;
  872. u32 bytes_xfrd;
  873. int etd_done;
  874. disactivate_etd(imx21, etd_num);
  875. dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3;
  876. cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf;
  877. bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff);
  878. /* save toggle carry */
  879. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  880. usb_pipeout(urb->pipe),
  881. (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1);
  882. if (dir == TD_DIR_IN) {
  883. clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
  884. clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
  885. if (etd->bounce_buffer) {
  886. memcpy(etd->cpu_buffer, etd->bounce_buffer, bytes_xfrd);
  887. dma_unmap_single(imx21->dev,
  888. etd->dma_handle, etd->len, DMA_FROM_DEVICE);
  889. } else if (!etd->dma_handle && bytes_xfrd) {/* PIO */
  890. memcpy_fromio(etd->cpu_buffer,
  891. imx21->regs + USBOTG_DMEM + etd->dmem_offset,
  892. bytes_xfrd);
  893. }
  894. }
  895. kfree(etd->bounce_buffer);
  896. etd->bounce_buffer = NULL;
  897. free_dmem(imx21, etd);
  898. urb->error_count = 0;
  899. if (!(urb->transfer_flags & URB_SHORT_NOT_OK)
  900. && (cc == TD_DATAUNDERRUN))
  901. cc = TD_CC_NOERROR;
  902. if (cc != 0)
  903. dev_vdbg(imx21->dev, "cc is 0x%x\n", cc);
  904. etd_done = (cc_to_error[cc] != 0); /* stop if error */
  905. switch (usb_pipetype(urb->pipe)) {
  906. case PIPE_CONTROL:
  907. switch (urb_priv->state) {
  908. case US_CTRL_SETUP:
  909. if (urb->transfer_buffer_length > 0)
  910. urb_priv->state = US_CTRL_DATA;
  911. else
  912. urb_priv->state = US_CTRL_ACK;
  913. break;
  914. case US_CTRL_DATA:
  915. urb->actual_length += bytes_xfrd;
  916. urb_priv->state = US_CTRL_ACK;
  917. break;
  918. case US_CTRL_ACK:
  919. etd_done = 1;
  920. break;
  921. default:
  922. dev_err(imx21->dev,
  923. "Invalid pipe state %d\n", urb_priv->state);
  924. etd_done = 1;
  925. break;
  926. }
  927. break;
  928. case PIPE_BULK:
  929. urb->actual_length += bytes_xfrd;
  930. if ((urb_priv->state == US_BULK)
  931. && (urb->transfer_flags & URB_ZERO_PACKET)
  932. && urb->transfer_buffer_length > 0
  933. && ((urb->transfer_buffer_length %
  934. usb_maxpacket(urb->dev, urb->pipe,
  935. usb_pipeout(urb->pipe))) == 0)) {
  936. /* need a 0-packet */
  937. urb_priv->state = US_BULK0;
  938. } else {
  939. etd_done = 1;
  940. }
  941. break;
  942. case PIPE_INTERRUPT:
  943. urb->actual_length += bytes_xfrd;
  944. etd_done = 1;
  945. break;
  946. }
  947. if (etd_done)
  948. nonisoc_urb_completed_for_etd(imx21, etd, cc_to_error[cc]);
  949. else {
  950. dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state);
  951. schedule_nonisoc_etd(imx21, urb);
  952. }
  953. }
  954. static struct ep_priv *alloc_ep(void)
  955. {
  956. int i;
  957. struct ep_priv *ep_priv;
  958. ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
  959. if (!ep_priv)
  960. return NULL;
  961. for (i = 0; i < NUM_ISO_ETDS; ++i)
  962. ep_priv->etd[i] = -1;
  963. return ep_priv;
  964. }
  965. static int imx21_hc_urb_enqueue(struct usb_hcd *hcd,
  966. struct urb *urb, gfp_t mem_flags)
  967. {
  968. struct imx21 *imx21 = hcd_to_imx21(hcd);
  969. struct usb_host_endpoint *ep = urb->ep;
  970. struct urb_priv *urb_priv;
  971. struct ep_priv *ep_priv;
  972. struct etd_priv *etd;
  973. int ret;
  974. unsigned long flags;
  975. dev_vdbg(imx21->dev,
  976. "enqueue urb=%p ep=%p len=%d "
  977. "buffer=%p dma=%pad setupBuf=%p setupDma=%pad\n",
  978. urb, ep,
  979. urb->transfer_buffer_length,
  980. urb->transfer_buffer, &urb->transfer_dma,
  981. urb->setup_packet, &urb->setup_dma);
  982. if (usb_pipeisoc(urb->pipe))
  983. return imx21_hc_urb_enqueue_isoc(hcd, ep, urb, mem_flags);
  984. urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
  985. if (!urb_priv)
  986. return -ENOMEM;
  987. spin_lock_irqsave(&imx21->lock, flags);
  988. ep_priv = ep->hcpriv;
  989. if (ep_priv == NULL) {
  990. ep_priv = alloc_ep();
  991. if (!ep_priv) {
  992. ret = -ENOMEM;
  993. goto failed_alloc_ep;
  994. }
  995. ep->hcpriv = ep_priv;
  996. ep_priv->ep = ep;
  997. }
  998. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  999. if (ret)
  1000. goto failed_link;
  1001. urb->status = -EINPROGRESS;
  1002. urb->actual_length = 0;
  1003. urb->error_count = 0;
  1004. urb->hcpriv = urb_priv;
  1005. urb_priv->ep = ep;
  1006. switch (usb_pipetype(urb->pipe)) {
  1007. case PIPE_CONTROL:
  1008. urb_priv->state = US_CTRL_SETUP;
  1009. break;
  1010. case PIPE_BULK:
  1011. urb_priv->state = US_BULK;
  1012. break;
  1013. }
  1014. debug_urb_submitted(imx21, urb);
  1015. if (ep_priv->etd[0] < 0) {
  1016. if (ep_priv->waiting_etd) {
  1017. dev_dbg(imx21->dev,
  1018. "no ETD available already queued %p\n",
  1019. ep_priv);
  1020. debug_urb_queued_for_etd(imx21, urb);
  1021. goto out;
  1022. }
  1023. ep_priv->etd[0] = alloc_etd(imx21);
  1024. if (ep_priv->etd[0] < 0) {
  1025. dev_dbg(imx21->dev,
  1026. "no ETD available queueing %p\n", ep_priv);
  1027. debug_urb_queued_for_etd(imx21, urb);
  1028. list_add_tail(&ep_priv->queue, &imx21->queue_for_etd);
  1029. ep_priv->waiting_etd = 1;
  1030. goto out;
  1031. }
  1032. }
  1033. /* Schedule if no URB already active for this endpoint */
  1034. etd = &imx21->etd[ep_priv->etd[0]];
  1035. if (etd->urb == NULL) {
  1036. DEBUG_LOG_FRAME(imx21, etd, last_req);
  1037. schedule_nonisoc_etd(imx21, urb);
  1038. }
  1039. out:
  1040. spin_unlock_irqrestore(&imx21->lock, flags);
  1041. return 0;
  1042. failed_link:
  1043. failed_alloc_ep:
  1044. spin_unlock_irqrestore(&imx21->lock, flags);
  1045. kfree(urb_priv);
  1046. return ret;
  1047. }
  1048. static int imx21_hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
  1049. int status)
  1050. {
  1051. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1052. unsigned long flags;
  1053. struct usb_host_endpoint *ep;
  1054. struct ep_priv *ep_priv;
  1055. struct urb_priv *urb_priv = urb->hcpriv;
  1056. int ret = -EINVAL;
  1057. dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n",
  1058. urb, usb_pipeisoc(urb->pipe), status);
  1059. spin_lock_irqsave(&imx21->lock, flags);
  1060. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  1061. if (ret)
  1062. goto fail;
  1063. ep = urb_priv->ep;
  1064. ep_priv = ep->hcpriv;
  1065. debug_urb_unlinked(imx21, urb);
  1066. if (usb_pipeisoc(urb->pipe)) {
  1067. dequeue_isoc_urb(imx21, urb, ep_priv);
  1068. schedule_isoc_etds(hcd, ep);
  1069. } else if (urb_priv->active) {
  1070. int etd_num = ep_priv->etd[0];
  1071. if (etd_num != -1) {
  1072. struct etd_priv *etd = &imx21->etd[etd_num];
  1073. disactivate_etd(imx21, etd_num);
  1074. free_dmem(imx21, etd);
  1075. etd->urb = NULL;
  1076. kfree(etd->bounce_buffer);
  1077. etd->bounce_buffer = NULL;
  1078. }
  1079. }
  1080. urb_done(hcd, urb, status);
  1081. spin_unlock_irqrestore(&imx21->lock, flags);
  1082. return 0;
  1083. fail:
  1084. spin_unlock_irqrestore(&imx21->lock, flags);
  1085. return ret;
  1086. }
  1087. /* =========================================== */
  1088. /* Interrupt dispatch */
  1089. /* =========================================== */
  1090. static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof)
  1091. {
  1092. int etd_num;
  1093. int enable_sof_int = 0;
  1094. unsigned long flags;
  1095. spin_lock_irqsave(&imx21->lock, flags);
  1096. for (etd_num = 0; etd_num < USB_NUM_ETD; etd_num++) {
  1097. u32 etd_mask = 1 << etd_num;
  1098. u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask;
  1099. u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask;
  1100. struct etd_priv *etd = &imx21->etd[etd_num];
  1101. if (done) {
  1102. DEBUG_LOG_FRAME(imx21, etd, last_int);
  1103. } else {
  1104. /*
  1105. * Kludge warning!
  1106. *
  1107. * When multiple transfers are using the bus we sometimes get into a state
  1108. * where the transfer has completed (the CC field of the ETD is != 0x0F),
  1109. * the ETD has self disabled but the ETDDONESTAT flag is not set
  1110. * (and hence no interrupt occurs).
  1111. * This causes the transfer in question to hang.
  1112. * The kludge below checks for this condition at each SOF and processes any
  1113. * blocked ETDs (after an arbitrary 10 frame wait)
  1114. *
  1115. * With a single active transfer the usbtest test suite will run for days
  1116. * without the kludge.
  1117. * With other bus activity (eg mass storage) even just test1 will hang without
  1118. * the kludge.
  1119. */
  1120. u32 dword0;
  1121. int cc;
  1122. if (etd->active_count && !enabled) /* suspicious... */
  1123. enable_sof_int = 1;
  1124. if (!sof || enabled || !etd->active_count)
  1125. continue;
  1126. cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE;
  1127. if (cc == TD_NOTACCESSED)
  1128. continue;
  1129. if (++etd->active_count < 10)
  1130. continue;
  1131. dword0 = etd_readl(imx21, etd_num, 0);
  1132. dev_dbg(imx21->dev,
  1133. "unblock ETD %d dev=0x%X ep=0x%X cc=0x%02X!\n",
  1134. etd_num, dword0 & 0x7F,
  1135. (dword0 >> DW0_ENDPNT) & 0x0F,
  1136. cc);
  1137. #ifdef DEBUG
  1138. dev_dbg(imx21->dev,
  1139. "frame: act=%d disact=%d"
  1140. " int=%d req=%d cur=%d\n",
  1141. etd->activated_frame,
  1142. etd->disactivated_frame,
  1143. etd->last_int_frame,
  1144. etd->last_req_frame,
  1145. readl(imx21->regs + USBH_FRMNUB));
  1146. imx21->debug_unblocks++;
  1147. #endif
  1148. etd->active_count = 0;
  1149. /* End of kludge */
  1150. }
  1151. if (etd->ep == NULL || etd->urb == NULL) {
  1152. dev_dbg(imx21->dev,
  1153. "Interrupt for unexpected etd %d"
  1154. " ep=%p urb=%p\n",
  1155. etd_num, etd->ep, etd->urb);
  1156. disactivate_etd(imx21, etd_num);
  1157. continue;
  1158. }
  1159. if (usb_pipeisoc(etd->urb->pipe))
  1160. isoc_etd_done(hcd, etd_num);
  1161. else
  1162. nonisoc_etd_done(hcd, etd_num);
  1163. }
  1164. /* only enable SOF interrupt if it may be needed for the kludge */
  1165. if (enable_sof_int)
  1166. set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
  1167. else
  1168. clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
  1169. spin_unlock_irqrestore(&imx21->lock, flags);
  1170. }
  1171. static irqreturn_t imx21_irq(struct usb_hcd *hcd)
  1172. {
  1173. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1174. u32 ints = readl(imx21->regs + USBH_SYSISR);
  1175. if (ints & USBH_SYSIEN_HERRINT)
  1176. dev_dbg(imx21->dev, "Scheduling error\n");
  1177. if (ints & USBH_SYSIEN_SORINT)
  1178. dev_dbg(imx21->dev, "Scheduling overrun\n");
  1179. if (ints & (USBH_SYSISR_DONEINT | USBH_SYSISR_SOFINT))
  1180. process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT);
  1181. writel(ints, imx21->regs + USBH_SYSISR);
  1182. return IRQ_HANDLED;
  1183. }
  1184. static void imx21_hc_endpoint_disable(struct usb_hcd *hcd,
  1185. struct usb_host_endpoint *ep)
  1186. {
  1187. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1188. unsigned long flags;
  1189. struct ep_priv *ep_priv;
  1190. int i;
  1191. if (ep == NULL)
  1192. return;
  1193. spin_lock_irqsave(&imx21->lock, flags);
  1194. ep_priv = ep->hcpriv;
  1195. dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv);
  1196. if (!list_empty(&ep->urb_list))
  1197. dev_dbg(imx21->dev, "ep's URB list is not empty\n");
  1198. if (ep_priv != NULL) {
  1199. for (i = 0; i < NUM_ISO_ETDS; i++) {
  1200. if (ep_priv->etd[i] > -1)
  1201. dev_dbg(imx21->dev, "free etd %d for disable\n",
  1202. ep_priv->etd[i]);
  1203. free_etd(imx21, ep_priv->etd[i]);
  1204. }
  1205. kfree(ep_priv);
  1206. ep->hcpriv = NULL;
  1207. }
  1208. for (i = 0; i < USB_NUM_ETD; i++) {
  1209. if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) {
  1210. dev_err(imx21->dev,
  1211. "Active etd %d for disabled ep=%p!\n", i, ep);
  1212. free_etd(imx21, i);
  1213. }
  1214. }
  1215. free_epdmem(imx21, ep);
  1216. spin_unlock_irqrestore(&imx21->lock, flags);
  1217. }
  1218. /* =========================================== */
  1219. /* Hub handling */
  1220. /* =========================================== */
  1221. static int get_hub_descriptor(struct usb_hcd *hcd,
  1222. struct usb_hub_descriptor *desc)
  1223. {
  1224. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1225. desc->bDescriptorType = USB_DT_HUB; /* HUB descriptor */
  1226. desc->bHubContrCurrent = 0;
  1227. desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA)
  1228. & USBH_ROOTHUBA_NDNSTMPRT_MASK;
  1229. desc->bDescLength = 9;
  1230. desc->bPwrOn2PwrGood = 0;
  1231. desc->wHubCharacteristics = (__force __u16) cpu_to_le16(
  1232. HUB_CHAR_NO_LPSM | /* No power switching */
  1233. HUB_CHAR_NO_OCPM); /* No over current protection */
  1234. desc->u.hs.DeviceRemovable[0] = 1 << 1;
  1235. desc->u.hs.DeviceRemovable[1] = ~0;
  1236. return 0;
  1237. }
  1238. static int imx21_hc_hub_status_data(struct usb_hcd *hcd, char *buf)
  1239. {
  1240. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1241. int ports;
  1242. int changed = 0;
  1243. int i;
  1244. unsigned long flags;
  1245. spin_lock_irqsave(&imx21->lock, flags);
  1246. ports = readl(imx21->regs + USBH_ROOTHUBA)
  1247. & USBH_ROOTHUBA_NDNSTMPRT_MASK;
  1248. if (ports > 7) {
  1249. ports = 7;
  1250. dev_err(imx21->dev, "ports %d > 7\n", ports);
  1251. }
  1252. for (i = 0; i < ports; i++) {
  1253. if (readl(imx21->regs + USBH_PORTSTAT(i)) &
  1254. (USBH_PORTSTAT_CONNECTSC |
  1255. USBH_PORTSTAT_PRTENBLSC |
  1256. USBH_PORTSTAT_PRTSTATSC |
  1257. USBH_PORTSTAT_OVRCURIC |
  1258. USBH_PORTSTAT_PRTRSTSC)) {
  1259. changed = 1;
  1260. buf[0] |= 1 << (i + 1);
  1261. }
  1262. }
  1263. spin_unlock_irqrestore(&imx21->lock, flags);
  1264. if (changed)
  1265. dev_info(imx21->dev, "Hub status changed\n");
  1266. return changed;
  1267. }
  1268. static int imx21_hc_hub_control(struct usb_hcd *hcd,
  1269. u16 typeReq,
  1270. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  1271. {
  1272. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1273. int rc = 0;
  1274. u32 status_write = 0;
  1275. switch (typeReq) {
  1276. case ClearHubFeature:
  1277. dev_dbg(imx21->dev, "ClearHubFeature\n");
  1278. switch (wValue) {
  1279. case C_HUB_OVER_CURRENT:
  1280. dev_dbg(imx21->dev, " OVER_CURRENT\n");
  1281. break;
  1282. case C_HUB_LOCAL_POWER:
  1283. dev_dbg(imx21->dev, " LOCAL_POWER\n");
  1284. break;
  1285. default:
  1286. dev_dbg(imx21->dev, " unknown\n");
  1287. rc = -EINVAL;
  1288. break;
  1289. }
  1290. break;
  1291. case ClearPortFeature:
  1292. dev_dbg(imx21->dev, "ClearPortFeature\n");
  1293. switch (wValue) {
  1294. case USB_PORT_FEAT_ENABLE:
  1295. dev_dbg(imx21->dev, " ENABLE\n");
  1296. status_write = USBH_PORTSTAT_CURCONST;
  1297. break;
  1298. case USB_PORT_FEAT_SUSPEND:
  1299. dev_dbg(imx21->dev, " SUSPEND\n");
  1300. status_write = USBH_PORTSTAT_PRTOVRCURI;
  1301. break;
  1302. case USB_PORT_FEAT_POWER:
  1303. dev_dbg(imx21->dev, " POWER\n");
  1304. status_write = USBH_PORTSTAT_LSDEVCON;
  1305. break;
  1306. case USB_PORT_FEAT_C_ENABLE:
  1307. dev_dbg(imx21->dev, " C_ENABLE\n");
  1308. status_write = USBH_PORTSTAT_PRTENBLSC;
  1309. break;
  1310. case USB_PORT_FEAT_C_SUSPEND:
  1311. dev_dbg(imx21->dev, " C_SUSPEND\n");
  1312. status_write = USBH_PORTSTAT_PRTSTATSC;
  1313. break;
  1314. case USB_PORT_FEAT_C_CONNECTION:
  1315. dev_dbg(imx21->dev, " C_CONNECTION\n");
  1316. status_write = USBH_PORTSTAT_CONNECTSC;
  1317. break;
  1318. case USB_PORT_FEAT_C_OVER_CURRENT:
  1319. dev_dbg(imx21->dev, " C_OVER_CURRENT\n");
  1320. status_write = USBH_PORTSTAT_OVRCURIC;
  1321. break;
  1322. case USB_PORT_FEAT_C_RESET:
  1323. dev_dbg(imx21->dev, " C_RESET\n");
  1324. status_write = USBH_PORTSTAT_PRTRSTSC;
  1325. break;
  1326. default:
  1327. dev_dbg(imx21->dev, " unknown\n");
  1328. rc = -EINVAL;
  1329. break;
  1330. }
  1331. break;
  1332. case GetHubDescriptor:
  1333. dev_dbg(imx21->dev, "GetHubDescriptor\n");
  1334. rc = get_hub_descriptor(hcd, (void *)buf);
  1335. break;
  1336. case GetHubStatus:
  1337. dev_dbg(imx21->dev, " GetHubStatus\n");
  1338. *(__le32 *) buf = 0;
  1339. break;
  1340. case GetPortStatus:
  1341. dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n",
  1342. wIndex, USBH_PORTSTAT(wIndex - 1));
  1343. *(__le32 *) buf = readl(imx21->regs +
  1344. USBH_PORTSTAT(wIndex - 1));
  1345. break;
  1346. case SetHubFeature:
  1347. dev_dbg(imx21->dev, "SetHubFeature\n");
  1348. switch (wValue) {
  1349. case C_HUB_OVER_CURRENT:
  1350. dev_dbg(imx21->dev, " OVER_CURRENT\n");
  1351. break;
  1352. case C_HUB_LOCAL_POWER:
  1353. dev_dbg(imx21->dev, " LOCAL_POWER\n");
  1354. break;
  1355. default:
  1356. dev_dbg(imx21->dev, " unknown\n");
  1357. rc = -EINVAL;
  1358. break;
  1359. }
  1360. break;
  1361. case SetPortFeature:
  1362. dev_dbg(imx21->dev, "SetPortFeature\n");
  1363. switch (wValue) {
  1364. case USB_PORT_FEAT_SUSPEND:
  1365. dev_dbg(imx21->dev, " SUSPEND\n");
  1366. status_write = USBH_PORTSTAT_PRTSUSPST;
  1367. break;
  1368. case USB_PORT_FEAT_POWER:
  1369. dev_dbg(imx21->dev, " POWER\n");
  1370. status_write = USBH_PORTSTAT_PRTPWRST;
  1371. break;
  1372. case USB_PORT_FEAT_RESET:
  1373. dev_dbg(imx21->dev, " RESET\n");
  1374. status_write = USBH_PORTSTAT_PRTRSTST;
  1375. break;
  1376. default:
  1377. dev_dbg(imx21->dev, " unknown\n");
  1378. rc = -EINVAL;
  1379. break;
  1380. }
  1381. break;
  1382. default:
  1383. dev_dbg(imx21->dev, " unknown\n");
  1384. rc = -EINVAL;
  1385. break;
  1386. }
  1387. if (status_write)
  1388. writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1));
  1389. return rc;
  1390. }
  1391. /* =========================================== */
  1392. /* Host controller management */
  1393. /* =========================================== */
  1394. static int imx21_hc_reset(struct usb_hcd *hcd)
  1395. {
  1396. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1397. unsigned long timeout;
  1398. unsigned long flags;
  1399. spin_lock_irqsave(&imx21->lock, flags);
  1400. /* Reset the Host controller modules */
  1401. writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH |
  1402. USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC,
  1403. imx21->regs + USBOTG_RST_CTRL);
  1404. /* Wait for reset to finish */
  1405. timeout = jiffies + HZ;
  1406. while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) {
  1407. if (time_after(jiffies, timeout)) {
  1408. spin_unlock_irqrestore(&imx21->lock, flags);
  1409. dev_err(imx21->dev, "timeout waiting for reset\n");
  1410. return -ETIMEDOUT;
  1411. }
  1412. spin_unlock_irq(&imx21->lock);
  1413. schedule_timeout_uninterruptible(1);
  1414. spin_lock_irq(&imx21->lock);
  1415. }
  1416. spin_unlock_irqrestore(&imx21->lock, flags);
  1417. return 0;
  1418. }
  1419. static int imx21_hc_start(struct usb_hcd *hcd)
  1420. {
  1421. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1422. unsigned long flags;
  1423. int i, j;
  1424. u32 hw_mode = USBOTG_HWMODE_CRECFG_HOST;
  1425. u32 usb_control = 0;
  1426. hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) &
  1427. USBOTG_HWMODE_HOSTXCVR_MASK);
  1428. hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) &
  1429. USBOTG_HWMODE_OTGXCVR_MASK);
  1430. if (imx21->pdata->host1_txenoe)
  1431. usb_control |= USBCTRL_HOST1_TXEN_OE;
  1432. if (!imx21->pdata->host1_xcverless)
  1433. usb_control |= USBCTRL_HOST1_BYP_TLL;
  1434. if (imx21->pdata->otg_ext_xcvr)
  1435. usb_control |= USBCTRL_OTC_RCV_RXDP;
  1436. spin_lock_irqsave(&imx21->lock, flags);
  1437. writel((USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN),
  1438. imx21->regs + USBOTG_CLK_CTRL);
  1439. writel(hw_mode, imx21->regs + USBOTG_HWMODE);
  1440. writel(usb_control, imx21->regs + USBCTRL);
  1441. writel(USB_MISCCONTROL_SKPRTRY | USB_MISCCONTROL_ARBMODE,
  1442. imx21->regs + USB_MISCCONTROL);
  1443. /* Clear the ETDs */
  1444. for (i = 0; i < USB_NUM_ETD; i++)
  1445. for (j = 0; j < 4; j++)
  1446. etd_writel(imx21, i, j, 0);
  1447. /* Take the HC out of reset */
  1448. writel(USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL | USBH_HOST_CTRL_CTLBLKSR_1,
  1449. imx21->regs + USBH_HOST_CTRL);
  1450. /* Enable ports */
  1451. if (imx21->pdata->enable_otg_host)
  1452. writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
  1453. imx21->regs + USBH_PORTSTAT(0));
  1454. if (imx21->pdata->enable_host1)
  1455. writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
  1456. imx21->regs + USBH_PORTSTAT(1));
  1457. if (imx21->pdata->enable_host2)
  1458. writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
  1459. imx21->regs + USBH_PORTSTAT(2));
  1460. hcd->state = HC_STATE_RUNNING;
  1461. /* Enable host controller interrupts */
  1462. set_register_bits(imx21, USBH_SYSIEN,
  1463. USBH_SYSIEN_HERRINT |
  1464. USBH_SYSIEN_DONEINT | USBH_SYSIEN_SORINT);
  1465. set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
  1466. spin_unlock_irqrestore(&imx21->lock, flags);
  1467. return 0;
  1468. }
  1469. static void imx21_hc_stop(struct usb_hcd *hcd)
  1470. {
  1471. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1472. unsigned long flags;
  1473. spin_lock_irqsave(&imx21->lock, flags);
  1474. writel(0, imx21->regs + USBH_SYSIEN);
  1475. clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
  1476. clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN,
  1477. USBOTG_CLK_CTRL);
  1478. spin_unlock_irqrestore(&imx21->lock, flags);
  1479. }
  1480. /* =========================================== */
  1481. /* Driver glue */
  1482. /* =========================================== */
  1483. static const struct hc_driver imx21_hc_driver = {
  1484. .description = hcd_name,
  1485. .product_desc = "IMX21 USB Host Controller",
  1486. .hcd_priv_size = sizeof(struct imx21),
  1487. .flags = HCD_USB11,
  1488. .irq = imx21_irq,
  1489. .reset = imx21_hc_reset,
  1490. .start = imx21_hc_start,
  1491. .stop = imx21_hc_stop,
  1492. /* I/O requests */
  1493. .urb_enqueue = imx21_hc_urb_enqueue,
  1494. .urb_dequeue = imx21_hc_urb_dequeue,
  1495. .endpoint_disable = imx21_hc_endpoint_disable,
  1496. /* scheduling support */
  1497. .get_frame_number = imx21_hc_get_frame,
  1498. /* Root hub support */
  1499. .hub_status_data = imx21_hc_hub_status_data,
  1500. .hub_control = imx21_hc_hub_control,
  1501. };
  1502. static struct mx21_usbh_platform_data default_pdata = {
  1503. .host_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
  1504. .otg_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
  1505. .enable_host1 = 1,
  1506. .enable_host2 = 1,
  1507. .enable_otg_host = 1,
  1508. };
  1509. static int imx21_remove(struct platform_device *pdev)
  1510. {
  1511. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  1512. struct imx21 *imx21 = hcd_to_imx21(hcd);
  1513. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1514. remove_debug_files(imx21);
  1515. usb_remove_hcd(hcd);
  1516. if (res != NULL) {
  1517. clk_disable_unprepare(imx21->clk);
  1518. clk_put(imx21->clk);
  1519. iounmap(imx21->regs);
  1520. release_mem_region(res->start, resource_size(res));
  1521. }
  1522. kfree(hcd);
  1523. return 0;
  1524. }
  1525. static int imx21_probe(struct platform_device *pdev)
  1526. {
  1527. struct usb_hcd *hcd;
  1528. struct imx21 *imx21;
  1529. struct resource *res;
  1530. int ret;
  1531. int irq;
  1532. printk(KERN_INFO "%s\n", imx21_hc_driver.product_desc);
  1533. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1534. if (!res)
  1535. return -ENODEV;
  1536. irq = platform_get_irq(pdev, 0);
  1537. if (irq < 0) {
  1538. dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
  1539. return irq;
  1540. }
  1541. hcd = usb_create_hcd(&imx21_hc_driver,
  1542. &pdev->dev, dev_name(&pdev->dev));
  1543. if (hcd == NULL) {
  1544. dev_err(&pdev->dev, "Cannot create hcd (%s)\n",
  1545. dev_name(&pdev->dev));
  1546. return -ENOMEM;
  1547. }
  1548. imx21 = hcd_to_imx21(hcd);
  1549. imx21->hcd = hcd;
  1550. imx21->dev = &pdev->dev;
  1551. imx21->pdata = dev_get_platdata(&pdev->dev);
  1552. if (!imx21->pdata)
  1553. imx21->pdata = &default_pdata;
  1554. spin_lock_init(&imx21->lock);
  1555. INIT_LIST_HEAD(&imx21->dmem_list);
  1556. INIT_LIST_HEAD(&imx21->queue_for_etd);
  1557. INIT_LIST_HEAD(&imx21->queue_for_dmem);
  1558. create_debug_files(imx21);
  1559. res = request_mem_region(res->start, resource_size(res), hcd_name);
  1560. if (!res) {
  1561. ret = -EBUSY;
  1562. goto failed_request_mem;
  1563. }
  1564. imx21->regs = ioremap(res->start, resource_size(res));
  1565. if (imx21->regs == NULL) {
  1566. dev_err(imx21->dev, "Cannot map registers\n");
  1567. ret = -ENOMEM;
  1568. goto failed_ioremap;
  1569. }
  1570. /* Enable clocks source */
  1571. imx21->clk = clk_get(imx21->dev, NULL);
  1572. if (IS_ERR(imx21->clk)) {
  1573. dev_err(imx21->dev, "no clock found\n");
  1574. ret = PTR_ERR(imx21->clk);
  1575. goto failed_clock_get;
  1576. }
  1577. ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000));
  1578. if (ret)
  1579. goto failed_clock_set;
  1580. ret = clk_prepare_enable(imx21->clk);
  1581. if (ret)
  1582. goto failed_clock_enable;
  1583. dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n",
  1584. (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF);
  1585. ret = usb_add_hcd(hcd, irq, 0);
  1586. if (ret != 0) {
  1587. dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
  1588. goto failed_add_hcd;
  1589. }
  1590. device_wakeup_enable(hcd->self.controller);
  1591. return 0;
  1592. failed_add_hcd:
  1593. clk_disable_unprepare(imx21->clk);
  1594. failed_clock_enable:
  1595. failed_clock_set:
  1596. clk_put(imx21->clk);
  1597. failed_clock_get:
  1598. iounmap(imx21->regs);
  1599. failed_ioremap:
  1600. release_mem_region(res->start, resource_size(res));
  1601. failed_request_mem:
  1602. remove_debug_files(imx21);
  1603. usb_put_hcd(hcd);
  1604. return ret;
  1605. }
  1606. static struct platform_driver imx21_hcd_driver = {
  1607. .driver = {
  1608. .name = hcd_name,
  1609. },
  1610. .probe = imx21_probe,
  1611. .remove = imx21_remove,
  1612. .suspend = NULL,
  1613. .resume = NULL,
  1614. };
  1615. module_platform_driver(imx21_hcd_driver);
  1616. MODULE_DESCRIPTION("i.MX21 USB Host controller");
  1617. MODULE_AUTHOR("Martin Fuzzey");
  1618. MODULE_LICENSE("GPL");
  1619. MODULE_ALIAS("platform:imx21-hcd");