lowlevel_init.S 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  4. * Copyright (C) 2011, 2012 Renesas Solutions Corp.
  5. */
  6. #include <config.h>
  7. #include <asm/processor.h>
  8. #include <asm/macro.h>
  9. #include <asm/processor.h>
  10. .global lowlevel_init
  11. .text
  12. .align 2
  13. lowlevel_init:
  14. /* WDT */
  15. write32 WDTCSR_A, WDTCSR_D
  16. /* MMU */
  17. write32 MMUCR_A, MMUCR_D
  18. write32 FRQCR2_A, FRQCR2_D
  19. write32 FRQCR0_A, FRQCR0_D
  20. write32 CS0CTRL_A, CS0CTRL_D
  21. write32 CS1CTRL_A, CS1CTRL_D
  22. write32 CS0CTRL2_A, CS0CTRL2_D
  23. write32 CSPWCR0_A, CSPWCR0_D
  24. write32 CSPWCR1_A, CSPWCR1_D
  25. write32 CS1GDST_A, CS1GDST_D
  26. # clock mode check
  27. mov.l MODEMR, r1
  28. mov.l @r1, r0
  29. and #6, r0 /* Check 1 and 2 bit.*/
  30. cmp/eq #2, r0 /* 0x02 is 533Mhz mode */
  31. bt init_lbsc_533
  32. init_lbsc_400:
  33. write32 CSWCR0_A, CSWCR0_D_400
  34. write32 CSWCR1_A, CSWCR1_D
  35. bra init_dbsc3_400_pad
  36. nop
  37. .align 2
  38. MODEMR: .long 0xFFCC0020
  39. WDTCSR_A: .long 0xFFCC0004
  40. WDTCSR_D: .long 0xA5000000
  41. MMUCR_A: .long 0xFF000010
  42. MMUCR_D: .long 0x00000004
  43. FRQCR2_A: .long 0xFFC80008
  44. FRQCR2_D: .long 0x00000000
  45. FRQCR0_A: .long 0xFFC80000
  46. FRQCR0_D: .long 0xCF000001
  47. CS0CTRL_A: .long 0xFF800200
  48. CS0CTRL_D: .long 0x00000020
  49. CS1CTRL_A: .long 0xFF800204
  50. CS1CTRL_D: .long 0x00000020
  51. CS0CTRL2_A: .long 0xFF800220
  52. CS0CTRL2_D: .long 0x00004000
  53. CSPWCR0_A: .long 0xFF800280
  54. CSPWCR0_D: .long 0x00000000
  55. CSPWCR1_A: .long 0xFF800284
  56. CSPWCR1_D: .long 0x00000000
  57. CS1GDST_A: .long 0xFF8002C0
  58. CS1GDST_D: .long 0x00000011
  59. init_lbsc_533:
  60. write32 CSWCR0_A, CSWCR0_D_533
  61. write32 CSWCR1_A, CSWCR1_D
  62. bra init_dbsc3_533_pad
  63. nop
  64. .align 2
  65. CSWCR0_A: .long 0xFF800230
  66. CSWCR0_D_533: .long 0x01120104
  67. CSWCR0_D_400: .long 0x02120114
  68. CSWCR1_A: .long 0xFF800234
  69. CSWCR1_D: .long 0x077F077F
  70. init_dbsc3_400_pad:
  71. write32 DBPDCNT3_A, DBPDCNT3_D
  72. wait_timer WAIT_200US_400
  73. write32 DBPDCNT0_A, DBPDCNT0_D_400
  74. write32 DBPDCNT3_A, DBPDCNT3_D0
  75. write32 DBPDCNT1_A, DBPDCNT1_D
  76. write32 DBPDCNT3_A, DBPDCNT3_D1
  77. wait_timer WAIT_32MCLK
  78. write32 DBPDCNT3_A, DBPDCNT3_D2
  79. wait_timer WAIT_100US_400
  80. write32 DBPDCNT3_A, DBPDCNT3_D3
  81. wait_timer WAIT_16MCLK
  82. write32 DBPDCNT3_A, DBPDCNT3_D4
  83. wait_timer WAIT_200US_400
  84. write32 DBPDCNT3_A, DBPDCNT3_D5
  85. wait_timer WAIT_1MCLK
  86. write32 DBPDCNT3_A, DBPDCNT3_D6
  87. wait_timer WAIT_10KMCLK
  88. bra init_dbsc3_ctrl_400
  89. nop
  90. .align 2
  91. init_dbsc3_533_pad:
  92. write32 DBPDCNT3_A, DBPDCNT3_D
  93. wait_timer WAIT_200US_533
  94. write32 DBPDCNT0_A, DBPDCNT0_D_533
  95. write32 DBPDCNT3_A, DBPDCNT3_D0
  96. write32 DBPDCNT1_A, DBPDCNT1_D
  97. write32 DBPDCNT3_A, DBPDCNT3_D1
  98. wait_timer WAIT_32MCLK
  99. write32 DBPDCNT3_A, DBPDCNT3_D2
  100. wait_timer WAIT_100US_533
  101. write32 DBPDCNT3_A, DBPDCNT3_D3
  102. wait_timer WAIT_16MCLK
  103. write32 DBPDCNT3_A, DBPDCNT3_D4
  104. wait_timer WAIT_200US_533
  105. write32 DBPDCNT3_A, DBPDCNT3_D5
  106. wait_timer WAIT_1MCLK
  107. write32 DBPDCNT3_A, DBPDCNT3_D6
  108. wait_timer WAIT_10KMCLK
  109. bra init_dbsc3_ctrl_533
  110. nop
  111. .align 2
  112. WAIT_200US_400: .long 40000
  113. WAIT_200US_533: .long 53300
  114. WAIT_100US_400: .long 20000
  115. WAIT_100US_533: .long 26650
  116. WAIT_32MCLK: .long 32
  117. WAIT_16MCLK: .long 16
  118. WAIT_1MCLK: .long 1
  119. WAIT_10KMCLK: .long 10000
  120. DBPDCNT0_A: .long 0xFE800200
  121. DBPDCNT0_D_533: .long 0x00010245
  122. DBPDCNT0_D_400: .long 0x00010235
  123. DBPDCNT1_A: .long 0xFE800204
  124. DBPDCNT1_D: .long 0x00000014
  125. DBPDCNT3_A: .long 0xFE80020C
  126. DBPDCNT3_D: .long 0x80000000
  127. DBPDCNT3_D0: .long 0x800F0000
  128. DBPDCNT3_D1: .long 0x800F1000
  129. DBPDCNT3_D2: .long 0x820F1000
  130. DBPDCNT3_D3: .long 0x860F1000
  131. DBPDCNT3_D4: .long 0x870F1000
  132. DBPDCNT3_D5: .long 0x870F3000
  133. DBPDCNT3_D6: .long 0x870F7000
  134. init_dbsc3_ctrl_400:
  135. write32 DBKIND_A, DBKIND_D
  136. write32 DBCONF_A, DBCONF_D
  137. write32 DBTR0_A, DBTR0_D_400
  138. write32 DBTR1_A, DBTR1_D_400
  139. write32 DBTR2_A, DBTR2_D
  140. write32 DBTR3_A, DBTR3_D_400
  141. write32 DBTR4_A, DBTR4_D_400
  142. write32 DBTR5_A, DBTR5_D_400
  143. write32 DBTR6_A, DBTR6_D_400
  144. write32 DBTR7_A, DBTR7_D
  145. write32 DBTR8_A, DBTR8_D_400
  146. write32 DBTR9_A, DBTR9_D
  147. write32 DBTR10_A, DBTR10_D_400
  148. write32 DBTR11_A, DBTR11_D
  149. write32 DBTR12_A, DBTR12_D_400
  150. write32 DBTR13_A, DBTR13_D_400
  151. write32 DBTR14_A, DBTR14_D
  152. write32 DBTR15_A, DBTR15_D
  153. write32 DBTR16_A, DBTR16_D_400
  154. write32 DBTR17_A, DBTR17_D_400
  155. write32 DBTR18_A, DBTR18_D_400
  156. write32 DBBL_A, DBBL_D
  157. write32 DBRNK0_A, DBRNK0_D
  158. write32 DBCMD_A, DBCMD_D0_400
  159. write32 DBCMD_A, DBCMD_D1
  160. write32 DBCMD_A, DBCMD_D2
  161. write32 DBCMD_A, DBCMD_D3
  162. write32 DBCMD_A, DBCMD_D4
  163. write32 DBCMD_A, DBCMD_D5_400
  164. write32 DBCMD_A, DBCMD_D6
  165. write32 DBCMD_A, DBCMD_D7
  166. write32 DBCMD_A, DBCMD_D8
  167. write32 DBCMD_A, DBCMD_D9_400
  168. write32 DBCMD_A, DBCMD_D10
  169. write32 DBCMD_A, DBCMD_D11
  170. write32 DBCMD_A, DBCMD_D12
  171. write32 DBRFCNF0_A, DBRFCNF0_D
  172. write32 DBRFCNF1_A, DBRFCNF1_D_400
  173. write32 DBRFCNF2_A, DBRFCNF2_D
  174. write32 DBRFEN_A, DBRFEN_D
  175. write32 DBACEN_A, DBACEN_D
  176. write32 DBACEN_A, DBACEN_D
  177. /* Dummy read */
  178. mov.l DBWAIT_A, r1
  179. synco
  180. mov.l @r1, r0
  181. synco
  182. /* Dummy read */
  183. mov.l SDRAM_A, r1
  184. synco
  185. mov.l @r1, r0
  186. synco
  187. /* need sleep 186A0 */
  188. bra finish_init_sh7734
  189. nop
  190. .align 2
  191. init_dbsc3_ctrl_533:
  192. write32 DBKIND_A, DBKIND_D
  193. write32 DBCONF_A, DBCONF_D
  194. write32 DBTR0_A, DBTR0_D_533
  195. write32 DBTR1_A, DBTR1_D_533
  196. write32 DBTR2_A, DBTR2_D
  197. write32 DBTR3_A, DBTR3_D_533
  198. write32 DBTR4_A, DBTR4_D_533
  199. write32 DBTR5_A, DBTR5_D_533
  200. write32 DBTR6_A, DBTR6_D_533
  201. write32 DBTR7_A, DBTR7_D
  202. write32 DBTR8_A, DBTR8_D_533
  203. write32 DBTR9_A, DBTR9_D
  204. write32 DBTR10_A, DBTR10_D_533
  205. write32 DBTR11_A, DBTR11_D
  206. write32 DBTR12_A, DBTR12_D_533
  207. write32 DBTR13_A, DBTR13_D_533
  208. write32 DBTR14_A, DBTR14_D
  209. write32 DBTR15_A, DBTR15_D
  210. write32 DBTR16_A, DBTR16_D_533
  211. write32 DBTR17_A, DBTR17_D_533
  212. write32 DBTR18_A, DBTR18_D_533
  213. write32 DBBL_A, DBBL_D
  214. write32 DBRNK0_A, DBRNK0_D
  215. write32 DBCMD_A, DBCMD_D0_533
  216. write32 DBCMD_A, DBCMD_D1
  217. write32 DBCMD_A, DBCMD_D2
  218. write32 DBCMD_A, DBCMD_D3
  219. write32 DBCMD_A, DBCMD_D4
  220. write32 DBCMD_A, DBCMD_D5_533
  221. write32 DBCMD_A, DBCMD_D6
  222. write32 DBCMD_A, DBCMD_D7
  223. write32 DBCMD_A, DBCMD_D8
  224. write32 DBCMD_A, DBCMD_D9_533
  225. write32 DBCMD_A, DBCMD_D10
  226. write32 DBCMD_A, DBCMD_D11
  227. write32 DBCMD_A, DBCMD_D12
  228. write32 DBRFCNF0_A, DBRFCNF0_D
  229. write32 DBRFCNF1_A, DBRFCNF1_D_533
  230. write32 DBRFCNF2_A, DBRFCNF2_D
  231. write32 DBRFEN_A, DBRFEN_D
  232. write32 DBACEN_A, DBACEN_D
  233. write32 DBACEN_A, DBACEN_D
  234. /* Dummy read */
  235. mov.l DBWAIT_A, r1
  236. synco
  237. mov.l @r1, r0
  238. synco
  239. /* Dummy read */
  240. mov.l SDRAM_A, r1
  241. synco
  242. mov.l @r1, r0
  243. synco
  244. /* need sleep 186A0 */
  245. bra finish_init_sh7734
  246. nop
  247. .align 2
  248. DBKIND_A: .long 0xFE800020
  249. DBKIND_D: .long 0x00000005
  250. DBCONF_A: .long 0xFE800024
  251. DBCONF_D: .long 0x0D020A01
  252. DBTR0_A: .long 0xFE800040
  253. DBTR0_D_533:.long 0x00000004
  254. DBTR0_D_400:.long 0x00000003
  255. DBTR1_A: .long 0xFE800044
  256. DBTR1_D_533:.long 0x00000003
  257. DBTR1_D_400:.long 0x00000002
  258. DBTR2_A: .long 0xFE800048
  259. DBTR2_D: .long 0x00000000
  260. DBTR3_A: .long 0xFE800050
  261. DBTR3_D_533:.long 0x00000004
  262. DBTR3_D_400:.long 0x00000003
  263. DBTR4_A: .long 0xFE800054
  264. DBTR4_D_533:.long 0x00050004
  265. DBTR4_D_400:.long 0x00050003
  266. DBTR5_A: .long 0xFE800058
  267. DBTR5_D_533:.long 0x0000000F
  268. DBTR5_D_400:.long 0x0000000B
  269. DBTR6_A: .long 0xFE80005C
  270. DBTR6_D_533:.long 0x0000000B
  271. DBTR6_D_400:.long 0x00000008
  272. DBTR7_A: .long 0xFE800060
  273. DBTR7_D: .long 0x00000002
  274. DBTR8_A: .long 0xFE800064
  275. DBTR8_D_533:.long 0x0000000D
  276. DBTR8_D_400:.long 0x0000000A
  277. DBTR9_A: .long 0xFE800068
  278. DBTR9_D: .long 0x00000002
  279. DBTR10_A: .long 0xFE80006C
  280. DBTR10_D_533:.long 0x00000004
  281. DBTR10_D_400:.long 0x00000003
  282. DBTR11_A: .long 0xFE800070
  283. DBTR11_D: .long 0x00000008
  284. DBTR12_A: .long 0xFE800074
  285. DBTR12_D_533:.long 0x00000009
  286. DBTR12_D_400:.long 0x00000008
  287. DBTR13_A: .long 0xFE800078
  288. DBTR13_D_533:.long 0x00000022
  289. DBTR13_D_400:.long 0x0000001A
  290. DBTR14_A: .long 0xFE80007C
  291. DBTR14_D: .long 0x00070002
  292. DBTR15_A: .long 0xFE800080
  293. DBTR15_D: .long 0x00000003
  294. DBTR16_A: .long 0xFE800084
  295. DBTR16_D_533:.long 0x120A1001
  296. DBTR16_D_400:.long 0x12091001
  297. DBTR17_A: .long 0xFE800088
  298. DBTR17_D_533:.long 0x00040000
  299. DBTR17_D_400:.long 0x00030000
  300. DBTR18_A: .long 0xFE80008C
  301. DBTR18_D_533:.long 0x02010200
  302. DBTR18_D_400:.long 0x02000207
  303. DBBL_A: .long 0xFE8000B0
  304. DBBL_D: .long 0x00000000
  305. DBRNK0_A: .long 0xFE800100
  306. DBRNK0_D: .long 0x00000001
  307. DBCMD_A: .long 0xFE800018
  308. DBCMD_D0_533: .long 0x1100006B
  309. DBCMD_D0_400: .long 0x11000050
  310. DBCMD_D1: .long 0x0B000000
  311. DBCMD_D2: .long 0x2A004000
  312. DBCMD_D3: .long 0x2B006000
  313. DBCMD_D4: .long 0x29002044
  314. DBCMD_D5_533: .long 0x28000743
  315. DBCMD_D5_400: .long 0x28000533
  316. DBCMD_D6: .long 0x0B000000
  317. DBCMD_D7: .long 0x0C000000
  318. DBCMD_D8: .long 0x0C000000
  319. DBCMD_D9_533: .long 0x28000643
  320. DBCMD_D9_400: .long 0x28000433
  321. DBCMD_D10: .long 0x000000C8
  322. DBCMD_D11: .long 0x290023C4
  323. DBCMD_D12: .long 0x29002004
  324. DBRFCNF0_A: .long 0xFE8000E0
  325. DBRFCNF0_D: .long 0x000001FF
  326. DBRFCNF1_A: .long 0xFE8000E4
  327. DBRFCNF1_D_533: .long 0x00000805
  328. DBRFCNF1_D_400: .long 0x00000618
  329. DBRFCNF2_A: .long 0xFE8000E8
  330. DBRFCNF2_D: .long 0x00000000
  331. DBRFEN_A: .long 0xFE800014
  332. DBRFEN_D: .long 0x00000001
  333. DBACEN_A: .long 0xFE800010
  334. DBACEN_D: .long 0x00000001
  335. DBWAIT_A: .long 0xFE80001C
  336. SDRAM_A: .long 0x0C000000
  337. finish_init_sh7734:
  338. write32 CCR_A, CCR_D
  339. stc sr, r0
  340. mov.l SR_MASK_D, r1
  341. and r1, r0
  342. ldc r0, sr
  343. rts
  344. nop
  345. .align 2
  346. CCR_A: .long 0xFF00001C
  347. CCR_D: .long 0x0000090B
  348. SR_MASK_D: .long 0xEFFFFF0F