as3722_init.c 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012-2016 Toradex, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch-tegra/tegra_i2c.h>
  8. #include "as3722_init.h"
  9. /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  10. void tegra_i2c_ll_write_addr(uint addr, uint config)
  11. {
  12. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  13. writel(addr, &reg->cmd_addr0);
  14. writel(config, &reg->cnfg);
  15. }
  16. void tegra_i2c_ll_write_data(uint data, uint config)
  17. {
  18. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  19. writel(data, &reg->cmd_data1);
  20. writel(config, &reg->cnfg);
  21. }
  22. void pmic_enable_cpu_vdd(void)
  23. {
  24. debug("%s entry\n", __func__);
  25. #ifdef AS3722_SD1VOLTAGE_DATA
  26. /* Set up VDD_CORE, for boards where OTP is incorrect*/
  27. debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
  28. /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
  29. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  30. tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  31. /*
  32. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  33. * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
  34. */
  35. udelay(10 * 1000);
  36. #endif
  37. debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  38. /*
  39. * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  40. * First set VDD to 1.0V, then enable the VDD regulator.
  41. */
  42. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  43. tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  44. /*
  45. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  46. * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  47. */
  48. udelay(10 * 1000);
  49. debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  50. /*
  51. * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  52. * First set VDD to 1.0V, then enable the VDD regulator.
  53. */
  54. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  55. tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  56. /*
  57. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  58. * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  59. */
  60. udelay(10 * 1000);
  61. debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  62. /*
  63. * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  64. * First set VDD to 1.2V, then enable the VDD regulator.
  65. */
  66. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  67. tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
  68. /*
  69. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  70. * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
  71. */
  72. udelay(10 * 1000);
  73. debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
  74. /*
  75. * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
  76. * First set it to value closest to 3.3V, then enable the regulator
  77. *
  78. * NOTE: We do this early because doing it later seems to hose the CPU
  79. * power rail/partition startup. Need to debug.
  80. */
  81. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  82. tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  83. /*
  84. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  85. * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
  86. */
  87. udelay(10 * 1000);
  88. debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
  89. /*
  90. * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
  91. * First set it to bypass 3.3V straight thru, then enable the regulator
  92. *
  93. * NOTE: We do this early because doing it later seems to hose the CPU
  94. * power rail/partition startup. Need to debug.
  95. */
  96. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  97. tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  98. /*
  99. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  100. * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
  101. */
  102. udelay(10 * 1000);
  103. }